December 2004
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128FT18B
3.3V 128K × 18 Flow Through Synchronous SRAM
®
12/10/04; v.1.3 Alliance Semiconductor P. 1 of 19
Features
• Organization: 131,072 words × 18 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
•Fast OE
access time: 3.5/4.0 ns
• Fully synchronou s flow through operation
• Asynchronous output enable cont rol
• Economical 100-pin TQFP package
• Individual byte write and Global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced pow er standby
• Common data input s and data outputs
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
17
15
17
A[16:0]
17
Address
DQ
CS
CLK
register
128K × 18
Memory
array
18
18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
Buffers
Input
registers
Power
down
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
CLK
BWE
GWE
18
DQ [a,b]
2
2
Selection guide –65 -75 -80 -10 Units
Minimum cycle time 7.5 8.5 10 12 ns
Maximum clock access time 6.5 7.5 8.0 10.0 ns
Maximum operating current 250 225 200 175 mA
Maximum standby current 120 100 90 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 2 of 19
2 Mb Synchronous SRAM products list1,2
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycl e Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRA M
Org Part Number Mode Speed
128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz
64KX32
AS7C3364PFS32B PL-SCD 200/166/133 MHz
64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz
128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz
64KX32
AS7C3364PFD32B PL-DCD 200/166/133 MHz
64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz
128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns
64KX32
AS7C3364FT32B FT 6.5/7.5/8.0/10 ns
64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 3 of 19
Pin arrangement
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQpb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQpa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
VSS
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
TQFP 14 × 20mm
NC
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 4 of 19
Functional description
The AS7C33128FT18B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as
131,072 words × 18 bits.
Fast cycle times of 7.5/8.5/10/12 ns with clock access times ( tCD) of 6.5/7.5/8 .0/10 ns. Three chip enable (CE ) inputs p ermit easy memory
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).
The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address
register when ADSP is sampled low, the chip enables are sampled active, and the output buf fer is enabled wit h OE. In a read operation, the
data accessed by the current address registered in the address registers by the positiv e edge of CLK are carried to the data-out buf fer. ADV
is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally
for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mo de is selec table with the
LBO
input.
With
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
LBO
driven low, the device uses a linear
count sequence.
Write cycles are pe rformed by d isa bling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a,b] inputs. Altern ately, when GWE is high, one or more byte s may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled
when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is
incremented interna lly to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP
are as follows:
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
•WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enabl e CE0 blocks ADSP, but not ADSC.
The AS7C33128FT18B family operates f rom a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP package.
TQFP capacitance
*Guaranteed not tested
TQFP thermal resistance
Parameter Symbol Test conditions Min Max Unit
Input capacitance CIN*VIN = 0V - 5 pF
I/O capacitanc e CI/O*VOUT = 0V - 7 pF
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 5 of 19
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guara nteed after the time tZZI is met. After entering SNOO ZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully com-
plete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when
exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
Pin I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, ZZ , and LBO are synchronous to this clock.
A,A0,A1 I SYNC Address. Sampled when all chip enable s are active and when ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE1, CE2 I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe processor. Asserted low to load a new address or to enter stan dby mode.
ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
ADV I SYNC Advance. Asserted low to continue burst read/write.
GWE I SYNC Global write enable. Asserted low to write all 18 bits. When high , BWE and BW[a,b] control write
enable.
BWE I SYNC Byte write enable. Asserted low with GWE high to enable ef fect of BW[a,b] inputs.
BW[a,b] I SYNC Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a ,b] are in ac tive,
the cycle is a read cycle.
OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
LBO ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 6 of 19
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function GWE BWE BWa BWb
Write All Bytes LXXX
HLLL
Write Byte a HLLH
Write Byte b HLHL
Read HHXX
HLHH
Operation ZZ OE I/O Status
Snooze mode H X High-Z
Read LLDout
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
1st Address 0 00 11 01 1
1st Address 0 00 11 01 1
2nd Address 0 10 01 11 0
2nd Address 0 11 01 10 0
3rd Address 1 01 10 00 1
3rd Address 1 01 10 00 1
4th Address 1 11 00 10 0
4th Address 1 11 00 11 0
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 7 of 19
Synchronous truth table[4]
CE01
1 X = don’t care, L = low, H = high
CE1 CE2 ADSP ADSC ADV
WRITE
[2]
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, G WE HIGH. See
"Write enable truth table (per byte)," on page 6 for more information.
OE Address accessed CLK Operation DQ
HXXXLX X X NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Q
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X H L External L to H Begin read Q
L H L H L X H H External L to H Begin read Hi−Z
XXXHHL H L Next L to HContinue readQ
XXXHHL H H Next L to HContinue readHi−Z
XXXHHH H L Current L to HSuspend readQ
XXXHHH H H Current L to HSuspend readHi−Z
HXXXHL H L Next L to HContinue readQ
HXXXHL H H Next L to HContinue readHi−Z
HXXXHH H L Current L to HSuspend readQ
HXXXHH H H Current L to HSuspend readHi−Z
L H L H L X L X External L to H Begin write D3
3 For write operation following a READ,
OE must be high before the input data set up time and held hig h throughout the input hold time
4 ZZ pin is always Low.
XXXHHL L X Next L to HContinue writeD
HXXXHL L X Next L to HContinue writeD
XXXHHH L X Current L to HSuspend writeD
HXXXHH L X Current L to HSuspend writeD
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 8 of 19
.
Recommended operating conditions at 3.3V I/O
Recommended operating conditions at 2.5V I/O
Absolute maximum ratings1
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Parameter Symbol Min Max Unit
Power supply voltage rela tive to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to G ND (i nput pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pi ns) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (plastic) Tstg –65 +150 °C
Temperature under bias Tbias –65 +135 °C
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 3.135 3.3 3.465 V
Ground supply Vss 0 0 0 V
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 2.375 2.5 2.625 V
Ground supply Vss 0 0 0 V
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 9 of 19
DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter Sym Conditions Min Max Unit
Input leakage current† |ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH Address and control pins 2* VDD+0.3 V
I/O pins 2* VDDQ+0.3
Input low (logic 0) voltage VIL Address and control pins -0.3** 0.8 V
I/O pins -0.5** 0.8
Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V
Parameter Sym Conditions Min Max Unit
Input leakage current† |ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH Address and control pins 1.7* VDD+0.3 V
I/O pins 1.7* VDDQ+0.3 V
Input low (logic 0) voltage VIL Address and control pins -0.3** 0.7 V
I/O pins -0.3** 0.7 V
Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V
Parameter Sym Conditions -65 -75 -80 -10 Unit
Operating power supply current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL 250 225 200 175 mA
Stand by power supply current
ISB All VIN ≤ 0.2V or >
V
DD
– 0.2V,
Deselected,
f = fMax, ZZ < VIL 120 100 90 90
mA
ISB1 Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30 30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V,
all VIN ≤ VIL or ≥ VIH 30 30 30 30
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter Sym
–65 -75 -80 –10
Unit Notes
1
1 See “Notes” on page 16.
Min Max Min Max Min Max Min Max
Cycle time tCYC 7.5 – 8.5 – 10 – 12 – ns
Clock access time tCD – 6.5 – 7.5 – 8.0 – 10 ns
Output enable LOW to data valid tOE – 3.5 – 3.5 – 4.0 – 4.0 ns
Clock HIGH to output Low Z tLZC 2.5 – 2.5 – 2.5 – 2.5 – ns 2,3,4
Data output invalid from clock HIGH tOH 2.5 – 2.5 – 2.5 – 2.5 – ns 2
Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – 0 – ns 2,3,4
Output enable HIGH to output H igh Z tHZOE – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4
Clock HIGH to output High Z tHZC – 3.0 – 3.5 – 4.0 – 5.0 ns 2,3,4
Output enable HIGH to invalid output tOHOE 0–0–0– 0 – ns
Clock HIGH pulse width tCH 2.5 – 3.0 – 4.0 – 4.0 – ns 5
Clock LOW pulse width tCL 2.5 – 3.0 – 4.0 – 4.0 – ns 5
Address setup to clock HIGH tAS 1.5 – 2.0 – 2.0 – 2.0 – ns 6
Data setup to clock HIGH tDS 1.5 – 2.0 – 2.0 – 2.0 – ns 6
Write setup to clock HIGH tWS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,7
Chip select setup to clock HIG H tCSS 1.5 – 2.0 – 2.0 – 2.0 – ns 6,8
Address hold fr om clock HIGH tAH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Data hold from clock HIGH tDH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Write hold from clock HIGH tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock HIGH tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8
ADV setup to clock HIGH tADVS 1.5 – 2.0 – 2.0 – 2.0 – ns 6
ADSP setup to clock HIGH tADSPS 1.5 – 2.0 – 2.0 – 2.0 – ns 6
ADSC setup to clock HIGH tADSCS 1.5 – 2.0 – 2.0 – 2.0 – ns 6
ADV hold from clock HIGH tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
ADSP hold from clock HIGH tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
ADSC hold from clock HIGH tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > VIH ISB2 30 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SNOOZE current tZZI 2cycle
ZZ inactive to exit SNOOZE current tRZZI 0
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 11 of 19
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
don’t careFalling inputRising input Undefined
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
t
CSS
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV inserts wait states
A2A1 A3
Dout
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
t
HZC
t
LZOE
t
CSH
Read
Q(A1) Suspend
Read
Q(A1)
Read
Q(A2) Burst
Read
Q(A2Ý01)
Read
Q(A3) DSEL
Burst
Read
Q(A2Ý10)
Suspend
Read
Q(A2Ý10)
Burst
Read
Q(A2Ý11)
Burst
Read
Q(A3Ý01)
Burst
Read
Q(A3Ý10)
Burst
Read
Q(A3Ý11)
t
OE
CE1
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 12 of 19
Timing waveform of write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Din
t
CSH
t
ADVH
D(A2Ý01)
D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
t
CH
CE1
BW[a:b]
Read
Q(A1) Suspend
Write
D(A1)
Read
Q(A2) Suspend
Write
D(A2)
ADV
Burst
Write
D(A2Ý01)
Suspend
Write
D(A2Ý01)
ADV
Burst
Write
D(A2Ý10)
Write
D(A3)Burst
Write
D(A3Ý01)
ADV
Burst
Write
D(A2Ý11)
ADV
Burst
Write
D(A3Ý10)
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 13 of 19
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
BWE
CE0, CE2
ADV
OE
Din
Dout
t
CD
t
ADVH
t
LZOE
t
OE
t
LZC
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
Suspend
Read
Q(A1)
Read
Q(A1) Suspend
Write
D(A2)
ADV
Burst
Read
Q(A3Ý01)
Suspend
Read
Q(A3Ý11)
ADV
Burst
Read
Q(A3Ý10)
ADV
Burst
Read
Q(A3Ý11)
Read
Q(A2) Read
Q(A3)
BW[a:b]
AS7C33128FT18B
®
12/10/04; v.1.3 Alliance Semiconductor P. 14 of 19
Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
Note: ADV is don’t care here.
t
CYC
t
CH
t
CL
t
ADSCH
CLK
ADSC
ADDRESS
A2
A1
t
ADSCS
A3 A4 A6
A5 A7 A8 A9
t
AH
t
AS
BWE t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
t
LZOE
t
OE
t
HZOE
Q(A1) Q(A2) Q(A3) Q(A4) Q(A9) Q(A10)
t
CD
t
OH
D(A6) D(A7)
D(A5)
t
DS
t
DH
OE
Dout
Din
READ
Q(A1) READ
Q(A2) READ
Q(A3) READ
Q(A4) WRITE
D(A5) WRITE
D(A6) WRITE
D(A7) WRITE
D(A8) READ
Q(A10)
CE1
A10
D(A8)
READ
Q(A9)
BW[a:b]
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 15 of 19
Timing waveform of power down cycle
t
CYC
t
CH
t
CL
t
ADSPS
CLK
ADSP
A
DDRESS A1
t
ADSPS
A2
BWE t
WH
t
WS
t
CSH
CE0,CE2
t
CSS
ADV
t
LZOE
t
OE
t
HZOE
Q(A1) Q(A2)
OE
Dout
Din
ADSC
t
HZC
t
PDS
Sleep
ZZ Setup Cycle
t
PUS
ZZ Recovery Cycle Normal Operation Mode
CE1
ZZ
Q(A2(
Ý
01))
BW[a:b]
READ
Q(A1) READ
Q(A1Ý01) READ
Q(A2) READ
Q(A2Ý01)
State
t
ZZI
I
SB2
t
RZZI
I
supply
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 16 of 19
AC test conditions
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
353
Ω / 1538Ω
5 pF*
319
Ω / 1667Ω
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitan
c
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to
GWE
,
BWE
,
BW[a,b].
8 Chip select refers to
CE0
,
CE1
,
CE2
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 17 of 19
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b 0.22 0.38
c 0.09 0.20
D 13.90 14.10
E 19.90 20.10
e 0.65 nominal
Hd 15.85 16.15
He 21.80 22.20
L 0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
He E
Hd
D
b
e
A1 A2
L1
L
α
®
AS7C33128FT18B
12/10/04; v.1.3 Alliance Semiconductor P. 18 of 19
Note: Ass suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33128FT18B-65TQCN)
1. Alliance Semiconductor SRAM Prefix
2. Operating voltage: 33=3.3V
3. Organization: 128=128K
4. Flowthrough.
5. Organization: 18=x18
6. Production version: B= product revision
7.Clock access time: [-65 = 6.5 ns; -75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]
8. Package type: TQ=TQFP
9. Operating temperature: C=Commercial (
0° C to 70° C); I=Industrial (
-40
° C to 85° C)
10. X = Lead free part
Ordering information
Package Width –65 -75 –80 –10
TQFP x18 AS7C33128FT18B-
65TQC AS7C33128FT18B-
75TQC AS7C33128FT18B-
80TQC AS7C33128FT18B-
10TQC
TQFP x18 AS7C33128FT18B-
65TQI AS7C33128FT18B-
75TQI AS7C33128FT18B-
80TQI AS7C33128FT18B-
10TQI
Part numbering guide
AS7C 33 128 FT 18 B –XX TQ C/I X
12345678910
AS7C33128FT18B
®
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related
to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33128FT18B
Document Version: v.1.3
®
