100 MHz to 4000 MHz
RF/IF Digitally Controlled VGA
Data Sheet
ADL5243
Rev. B
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FEATURES
Operating frequency from 100 MHz to 4000 MHz
Digitally controlled VGA with serial and parallel interfaces
6-bit, 0.5 dB digital step attenuator
31.5 dB gain control range with ±0.25 dB step accuracy
Gain Block Amplifier 1
Gain: 19.2 dB at 2140 MHz
OIP3: 40.2 dBm at 2140 MHz
P1dB: 19.8 dBm at 2140 MHz
Noise figure: 2.9 dB at 2140 MHz
¼ W Driver Amplifier 2
Gain: 14.2 dB at 2140 MHz
OIP3: 41.1 dBm at 2140 MHz
P1dB: 26.0 dBm at 2140 MHz
Noise figure: 3.7 dB at 2140 MHz
Gain block, DSA, or ¼ W driver amplifier can be first
Low quiescent current of 175 mA
The companion ADL5240 integrates a gain block with DSA
APPLICATIONS
Wireless infrastructure
Automated test equipment
RF/IF gain control
GENERAL DESCRIPTION
The ADL5243 is a high performance, digitally controlled
variable gain amplifier operating from 100 MHz to 4000 MHz.
The VGA integrates two high performance amplifiers and a
digital step attenuator (DSA). Amplifier 1 (AMP1) is an
internally matched gain block amplifier with 20 dB gain, and
Amplifier 2 (AMP2) is a broadband ¼ W driver amplifier that
requires very few external tuning components. The DSA is 6-bit
with a 31.5 dB gain control range, 0.5 dB steps, and ±0.25 dB
step accuracy. The attenuation of the DSA can be controlled
using a serial or parallel interface.
The gain block and DSA are internally matched to 50 Ω at their
inputs and outputs, and all three internal devices are separately
biased. The separate bias allows all or part of the ADL5243 to be
used, which allows for easy reuse throughout a design. The
pinout of the ADL5243 also enables the gain block, DSA, or
¼ W driver amplifier to be first, giving the VGA maximum
flexibility in a signal chain.
The ADL5243 consumes 175 mA and operates off a single
supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a
thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully
specified for operation from −40°C to +85°C. A fully populated
evaluation board is available.
FUNCTIONAL BLOCK DIAGRAM
ADL5243
AMP1
9
NC
10
AMP1IN
11
NC
12
NC
13
NC
14
NC
15
AMP2OUT/VCC2
16
VBIAS
SERI AL/P ARALLEL INTERFACE
24
VDD
23
NC
22
NC
21
DSAOUT
20
NC
19
AMP2IN
18
NC
17
NC
0.5dB 1dB 2dB 4dB 8dB 16dB
32
SEL
31
D0/CLK
30
D1/DATA
29
D2/LE
28
D3
27
D4
26
D5
25
D6
1
VDD
2
NC
3
NC
4
DSAIN
5
NC
6
AMP1OUT/VCC
7
NC
8
NC
AMP2
09431-001
Figure 1.
ADL5243 Data Sheet
Rev. B | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 12
Applications Information .............................................................. 22
Basic Layout Connections ......................................................... 22
SPI Timing................................................................................... 23
ADL5243 Amplifier 2 Matching .............................................. 25
ADL5243 Loop Performance .................................................... 31
Proper Driving Level for the Optimum ACLR ...................... 32
Thermal Considerations ............................................................ 32
Soldering Information and Recommended PCB Land Pattern
....................................................................................................... 32
Evaluation Board ............................................................................ 33
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
8/12—Rev. A to Rev. B
Changes to General Description Section ....................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 3 ........................................................................... 11
Changes to Figure 3 ......................................................................... 12
Changes to Figure 33 ....................................................................... 17
Added Figure 47 and Figure 49, Renumbered Sequentially ...... 19
Change to Figure 58 ........................................................................ 22
Changes to ADL5243 Amplifier 2 Matching Section, Table 8,
and Table 9 ........................................................................................ 25
Added Figure 61 and Figure 62...................................................... 26
Changes to Figure 63 and Figure 64 .............................................. 27
Added Figure 65; Changes to Figure 66........................................ 28
Added Figure 67; Changes to Figure 68........................................ 29
Added Figure 69 ............................................................................... 30
Changes to ADL5243 Loop Performance Section; Added
Figure 71, Figure 72, and Table 10, Renumbered Sequentially ....... 31
Added Proper Driving Level for the Optimum ACLR Section
and Figure 73 .................................................................................... 32
Changes to Evaluation Board Section and Table 11 ................... 33
Changes to Figure 75 ....................................................................... 34
Added Figure 76 .............................................................................. 35
Changes to Figure 77 and Figure 78.............................................. 36
Added Figure 79 .............................................................................. 37
8/11—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
7/11—Revision 0: Initial Version
Data Sheet ADL5243
Rev. B | Page 3 of 40
SPECIFICATIONS
VDD = 5 V, VCC = 5 V, VCC2 = 5 V, TA = 25°C.
Table 1.
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range
100
4000
MHz
AMPLIFIER 1 FREQUENCY = 150 MHz Using the AMP1IN and AMP1OUT pins
Gain
dB
vs. Frequency ±50 MHz ±0.97 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.07 dB
vs. Supply 4.75 V to 5.25 V ±0.03 dB
Input Return Loss S11 −10.4 dB
Output Return Loss S22 −8.2 dB
Output 1 dB Compression Point
dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 29.5 dBm
Noise Figure 2.8 dB
AMPLIFIER 1 FREQUENCY = 450 MHz
Using the AMP1IN and AMP1OUT pins
Gain 20.6 dB
vs. Frequency ±50 MHz ±0.10 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.36 dB
vs. Supply 4.75 V to 5.25 V ±0.01 dB
Input Return Loss
S11
dB
Output Return Loss S22 −16.5 dB
Output 1 dB Compression Point 19.5 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 38.4 dBm
Noise Figure 2.8 dB
AMPLIFIER 1 FREQUENCY = 748 MHz Using the AMP1IN and AMP1OUT pins
Gain 20.8 dB
vs. Frequency ±50 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.32 dB
vs. Supply
4.75 V to 5.25 V
dB
Input Return Loss S11 −22.0 dB
Output Return Loss S22 −21.6 dB
Output 1 dB Compression Point 19.6 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 39.6 dBm
Noise Figure
dB
AMPLIFIER 1 FREQUENCY = 943 MHz Using the AMP1IN and AMP1OUT pins
Gain 19.0 20.3 22.0 dB
vs. Frequency
±18 MHz
dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.28 dB
vs. Supply 4.75 V to 5.25 V ±0.02 dB
Input Return Loss S11 −24.0 dB
Output Return Loss S22 −21.5 dB
Output 1 dB Compression Point 18.5 19.9 dBm
Output Third-Order Intercept
∆f = 1 MHz, P
OUT
= 3 dBm/tone
dBm
Noise Figure 2.7 dB
ADL5243 Data Sheet
Rev. B | Page 4 of 40
Parameter Conditions Min Typ Max Unit
AMPLIFIER 1 FREQUENCY = 1960 MHz Using the AMP1IN and AMP1OUT pins
Gain 19.5 dB
vs. Frequency ±30 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.26 dB
vs. Supply
4.75 V to 5.25 V
dB
Input Return Loss S11 −13.5 dB
Output Return Loss S22 −12.4 dB
Output 1 dB Compression Point 19.6 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 40.4 dBm
Noise Figure 2.9 dB
AMPLIFIER 1 FREQUENCY = 2140 MHz Using the AMP1IN and AMP1OUT pins
Gain 17.5 19.2 21.5 dB
vs. Frequency ±30 MHz ±0.02 dB
vs. Temperature
−40°C ≤ T
A
≤ +85°C
dB
vs. Supply 4.75 V to 5.25 V ±0.05 dB
Input Return Loss S11 −13.3 dB
Output Return Loss S22 −12.2 dB
Output 1 dB Compression Point 17.5 19.8 dBm
Output Third-Order Intercept
∆f = 1 MHz, P
OUT
= 3 dBm/tone
dBm
Noise Figure 2.9 dB
AMPLIFIER 1 FREQUENCY = 2630 MHz Using the AMP1IN and AMP1OUT pins
Gain
17.5
21.5
dB
vs. Frequency ±60 MHz ±0.03 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.22 dB
vs. Supply 4.75 V to 5.25 V ±0.05 dB
Input Return Loss S11 −17.3 dB
Output Return Loss S22 −12.3 dB
Output 1 dB Compression Point
17.5
dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 39.5 dBm
Noise Figure 2.9 dB
AMPLIFIER 1 FREQUENCY = 3600 MHz Using the AMP1IN and AMP1OUT pins
Gain 18.0 dB
vs. Frequency ±100 MHz ±0.10 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.05 dB
vs. Supply 4.75 V to 5.25 V ±0.12 dB
Input Return Loss
S11
dB
Output Return Loss S22 −9.0 dB
Output 1 dB Compression Point 18.0 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 3 dBm/tone 34.6 dBm
Noise Figure 3.3 dB
AMPLIFIER 2 FREQUENCY = 150 MHz Using the AMP2IN and AMP2OUT pins
Gain 20.8 dB
vs. Frequency ±50 MHz ±1.1 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.3 dB
vs. Supply 4.75 V to 5.25 V ±0.03 dB
Input Return Loss S11 −11.0 dB
Output Return Loss S22 −6.5 dB
Output 1 dB Compression Point 22.8 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 40.6 dBm
Noise Figure
dB
Data Sheet ADL5243
Rev. B | Page 5 of 40
Parameter Conditions Min Typ Max Unit
AMPLIFIER 2 FREQUENCY = 450 MHz Using the AMP2IN and AMP2OUT pins
Gain 16.4 dB
vs. Frequency ±50 MHz ±0.5 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.35 dB
vs. Supply
4.75 V to 5.25 V
dB
Input Return Loss S11 −9.0 dB
Output Return Loss S22 −8.0 dB
Output 1 dB Compression Point 23.2 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 38.1 dBm
Noise Figure 6.2 dB
AMPLIFIER 2 FREQUENCY = 748 MHz Using the AMP2IN and AMP2OUT pins
Gain 17.5 dB
vs. Frequency ±50 MHz ±0.14 dB
Input Return Loss
S11
dB
Output Return Loss S22 −8.6 dB
Output 1 dB Compression Point 24.7 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 41.5 dBm
Noise Figure 5.6 dB
AMPLIFIER 2 FREQUENCY = 943 MHz Using the AMP2IN and AMP2OUT pins
Gain 16.5 dB
vs. Frequency ±18 MHz ±0.05 dB
vs. Temperature
−40°C ≤ T
A
≤ +85°C
dB
vs. Supply 4.75 V to 5.25 V ±0.10 dB
Input Return Loss S11 −11.2 dB
Output Return Loss S22 −8.1 dB
Output 1 dB Compression Point 25.0 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 43.3 dBm
Noise Figure
dB
AMPLIFIER 2 FREQUENCY = 1960 MHz Using the AMP2IN and AMP2OUT pins
Gain 14.9 dB
vs. Frequency ±30 MHz ±0.15 dB
Input Return Loss S11 −14 dB
Output Return Loss S22 −7.0 dB
Output 1 dB Compression Point 26.0 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 39.9 dBm
Noise Figure
dB
AMPLIFIER 2 FREQUENCY = 2140 MHz Using the AMP2IN and AMP2OUT pins
Gain 13.0 14.2 15.5 dB
vs. Frequency
±30 MHz
dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.50 dB
vs. Supply 4.75 V to 5.25 V ±0.09 dB
Input Return Loss S11 −10.7 dB
Output Return Loss S22 −8.1 dB
Output 1 dB Compression Point 26.0 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 41.1 dBm
Noise Figure 3.7 dB
ADL5243 Data Sheet
Rev. B | Page 6 of 40
Parameter Conditions Min Typ Max Unit
AMPLIFIER 2 FREQUENCY = 2630 MHz Using the AMP2IN and AMP2OUT pins
Gain 13.0 dB
vs. Frequency ±60 MHz ±0.13 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.56 dB
vs. Supply
4.75 V to 5.25 V
dB
Input Return Loss S11 −9.4 dB
Output Return Loss S22 −8.3 dB
Output 1 dB Compression Point 24.5 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 40.4 dBm
Noise Figure 4.1 dB
AMPLIFIER 2 FREQUENCY = 3600 MHz Using the AMP2IN and AMP2OUT pins
Gain 12.3 dB
vs. Frequency ±200 MHz ±1.23 dB
vs. Temperature
−40°C ≤ T
A
≤ +85°C
dB
vs. Supply 4.75 V to 5.25 V ±0.07 dB
Input Return Loss S11 −15.0 dB
Output Return Loss S22 −11.0 dB
Output 1 dB Compression Point 26.2 dBm
Output Third-Order Intercept
∆f = 1 MHz, P
OUT
= 5 dBm/tone
dBm
Noise Figure 5.5 dB
DSA FREQUENCY = 150 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss
dB
vs. Frequency ±50 MHz ±0.12 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.10 dB
Attenuation Range Between maximum and minimum attenuation states 28.8 dB
Attenuation Step Error All attenuation states ±0.18 dB
Attenuation Absolute Error All attenuation states ±1.35 dB
Input Return Loss
dB
Output Return Loss −13.3 dB
Input Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 48.2 dBm
DSA FREQUENCY = 450 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −1.4 dB
vs. Frequency ±50 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.12 dB
Attenuation Range Between maximum and minimum attenuation states 30.7 dB
Attenuation Step Error
All attenuation states
dB
Attenuation Absolute Error All attenuation states ±0.39 dB
Input Return Loss −17.7 dB
Output Return Loss −17.4 dB
Input Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 44.0 dBm
DSA FREQUENCY = 748 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −1.5 dB
vs. Frequency ±50 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.12 dB
Attenuation Range Between maximum and minimum attenuation states 30.9 dB
Attenuation Step Error All attenuation states ±0.15 dB
Attenuation Absolute Error All attenuation states ±0.30 dB
Input Return Loss −17.1 dB
Output Return Loss −17.1 dB
Input Third-Order Intercept
∆f = 1 MHz, P
OUT
= 5 dBm/tone
dBm
Data Sheet ADL5243
Rev. B | Page 7 of 40
Parameter Conditions Min Typ Max Unit
DSA FREQUENCY = 943 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −1.6 dB
vs. Frequency ±18 MHz ±0.01 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.13 dB
Attenuation Range
Between maximum and minimum attenuation states
dB
Attenuation Step Error All attenuation states ±0.15 dB
Attenuation Absolute Error All attenuation states ±0.28 dB
Input Return Loss −16.0 dB
Output Return Loss −15.9 dB
Input 1 dB Compression Point 30.5 dBm
Input Third-Order Intercept
∆f = 1 MHz, P
OUT
= 5 dBm/tone
dBm
DSA FREQUENCY = 1960 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −2.5 dB
vs. Frequency
±30 MHz
dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.18 dB
Attenuation Range Between maximum and minimum attenuation states 30.8 dB
Attenuation Step Error All attenuation states ±0.15 dB
Attenuation Absolute Error All attenuation states ±0.35 dB
Input Return Loss
dB
Output Return Loss −9.6 dB
Input 1 dB Compression Point 31.5 dBm
Input Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 49.6 dBm
DSA FREQUENCY = 2140 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −2.6 dB
vs. Frequency ±30 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.19 dB
Attenuation Range Between maximum and minimum attenuation states 30.9 dB
Attenuation Step Error
All attenuation states
dB
Attenuation Absolute Error All attenuation states ±0.32 dB
Input Return Loss −9.8 dB
Output Return Loss −9.3 dB
Input 1 dB Compression Point 31.5 dBm
Input Third-Order Intercept
∆f = 1 MHz, P
OUT
= 5 dBm/tone
dBm
DSA FREQUENCY = 2630 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −2.8 dB
vs. Frequency
±60 MHz
dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.21 dB
Attenuation Range Between maximum and minimum attenuation states 31.2 dB
Attenuation Step Error All attenuation states ±0.18 dB
Attenuation Absolute Error All attenuation states ±0.24 dB
Input Return Loss −10.0 dB
Output Return Loss
dB
Input 1 dB Compression Point 31.5 dBm
Input Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 48.3 dBm
ADL5243 Data Sheet
Rev. B | Page 8 of 40
Parameter Conditions Min Typ Max Unit
DSA FREQUENCY = 3600 MHz Using the DSAIN and DSAOUT pins, minimum attenuation
Insertion Loss −3.0 dB
vs. Frequency ±100 MHz ±0.02 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.23 dB
Attenuation Range
Between maximum and minimum attenuation states
dB
Attenuation Step Error All attenuation states ±0.38 dB
Attenuation Absolute Error All attenuation states ±0.35 dB
Input Return Loss −12.3 dB
Output Return Loss −11.7 dB
Input 1 dB Compression Point 31.0 dBm
Input Third-Order Intercept
∆f = 1 MHz, P
OUT
= 5 dBm/tone
dBm
DSA Gain Settling Using the DSAIN and DSAOUT pins
Minimum Attenuation to Maximum
Attenuation
36 ns
Maximum Attenuation to Minimum
Attenuation
36 ns
LOOP FREQUENCY = 150 MHz AMP1 – DSA – AMP2, DSA at minimum attenuation
Gain 37.4 dB
vs. Frequency ±50 MHz ±0.1 dB
Gain Range Between maximum and minimum attenuation states 28.0 dB
Input Return Loss S11 −10.0 dB
Output Return Loss S22 −7.0 dB
Output 1 dB Compression Point 22.5 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 38.5 dBm
Noise Figure 3.0 dB
LOOP FREQUENCY = 450 MHz AMP1 – DSA – AMP2, DSA at minimum attenuation
Gain 35.8 dB
vs. Frequency ±50 MHz ±0.43 dB
Gain Range Between maximum and minimum attenuation states 31.0 dB
Input Return Loss S11 −12.5 dB
Output Return Loss S22 −6.4 dB
Output 1 dB Compression Point 23.1 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 37.6 dBm
Noise Figure 3.1 dB
LOOP FREQUENCY = 943 MHz AMP1–DSA–AMP2, DSA at minimum attenuation
Gain 34.0 dB
vs. Frequency ±18 MHz ±0.10 dB
Gain Range Between maximum and minimum attenuation states 29.3 dB
Input Return Loss
S11
dB
Output Return Loss S22 −10.1 dB
Output 1 dB Compression Point 25.1 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 42.8 dBm
Noise Figure 2.9 dB
LOOP FREQUENCY = 2140 MHz AMP1 – DSA – AMP2, DSA at minimum attenuation
Gain 31.3 dB
vs. Frequency ±30 MHz ±0.03 dB
Gain Range Between maximum and minimum attenuation states 32.5 dB
Input Return Loss S11 −9.3 dB
Output Return Loss S22 −5.4 dB
Output 1 dB Compression Point 25.3 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 40.0 dBm
Noise Figure 3.1 dB
Data Sheet ADL5243
Rev. B | Page 9 of 40
Parameter Conditions Min Typ Max Unit
LOOP FREQUENCY = 2630 MHz AMP1 – DSA – AMP2, DSA at minimum attenuation
Gain 29.5 dB
vs. Frequency ±60 MHz ±0.56 dB
Gain Range Between maximum and minimum attenuation states 30.0 dB
Input Return Loss
S11
dB
Output Return Loss S22 −5.8 dB
Output 1 dB Compression Point 24.6 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 39.3 dBm
Noise Figure 3.1 dB
LOOP FREQUENCY = 3600 MHz AMP1 – DSA – AMP2, DSA at minimum attenuation
Gain 26.5 dB
vs. Frequency ±200 MHz ±1.3 dB
Gain Range Between maximum and minimum attenuation states 33.0 dB
Input Return Loss
S11
dB
Output Return Loss S22 −8.0 dB
Output 1 dB Compression Point 24.7 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 5 dBm/tone 36.0 dBm
Noise Figure 3.7 dB
LOGIC INPUTS CLK, DATA, LE, SEL, D0~D6
Input High Voltage, VINH 2.5 V
Input Low Voltage, VINL 0.8 V
Input Current, I
INH
/I
INL
µA
Input Capacitance, CIN 1.5 pF
POWER SUPPLIES
Voltage
4.75
5.25
V
Supply Current AMP1 89 120 mA
AMP2 86 120 mA
DSA 0.5 mA
ADL5243 Data Sheet
Rev. B | Page 10 of 40
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VDD, VCC, VCC2) 6.5 V
Input Power
AMP1IN 16 dBm
AMP2IN (50
Ω
Impedance) 20 dBm
DSAIN
30 dBm
Internal Power Dissipation 1.0 W
θJA (Exposed Paddle Soldered Down) 34.8°C/W
θJC (Exposed Paddle) 6.2°C/W
Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 60 sec) 240°C
Operating Temperature Range
−40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet ADL5243
Rev. B | Page 11 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CO NNE CT. DO NOT CONNE CT T O THIS PIN.
2. THE EX P OSED P AD M US T BE CO NNE CTED T O G ROUND.
PIN 1
INDICATOR
1VDD 2NC 3NC 4DSAIN 5NC 6AMP1OUT/VCC 7NC 8NC
24 VDD
23 NC
22 NC
21 DSAOUT
20 NC
19 AMP2IN
18 NC
17 NC
9NC 10AMP1IN 11NC 12
NC 13NC 14NC 15AMP2OUT/VCC2 16VBIAS
32 SEL
31 D0/CLK
30 D1/DATA
29 D2/LE
28 D3
27 D4
26 D5
25 D6
TOP VIEW
(No t t o Scal e)
ADL5243
09431-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 24 VDD Supply Voltage for DSA. Connect this pin to a 5 V supply.
2, 3, 5, 7, 8, 9, 11, 12, 13, 14,
17, 18, 20, 22, 23
NC No Connect. Do not connect to this pin.
4 DSAIN RF Input to DSA.
6
AMP1OUT/VCC
RF Output from Amplifier 1/Supply Voltage for Amplifier 1. Bias to Gain Block Amplifier 1 is
provided through a choke to this pin when connected to VCC.
10 AMP1IN RF Input to Gain Block Amplifier 1.
15 AMP2OUT/VCC2 RF Output from Amplifier 2/Supply Voltage for Amplifier 2. Bias to Driver Amplifier 2 is
provided through a choke to this pin when connected to VCC2.
16 VBIAS Bias for Driver Amplifier 2.
19
AMP2IN
RF Input to Amplifier 2.
21 DSAOUT RF Output from DSA.
25 D6 Data Bit in Parallel Mode (LSB). Connect to supply in serial mode.
26 D5 Data Bit in Parallel Mode. Connect to ground in serial mode.
27 D4 Data Bit in Parallel Mode. Connect to ground in serial mode.
28 D3 Data Bit in Parallel Mode. Connect to ground in serial mode.
29 D2/LE Data Bit in Parallel Mode/Latch Enable in Serial Mode.
30 D1/DATA Data Bit in Parallel Mode (MSB)/Data in Serial Mode.
31 D0/CLK Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode.
32 SEL Select Pin. For parallel mode operation , connect this pin to the supply. For serial mode
operation, connect this pin to ground.
EPAD
Exposed Paddle. The exposed paddle must be connected to ground.
ADL5243 Data Sheet
Rev. B | Page 12 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
10
15
20
25
30
35
40
45
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FRE QUENCY ( GHz)
09431-003
00.4 0.8 1.2 1.6 2.0 2.4
2.8 3.2 3.6 4.0
GAIN
P1dB
NOISE FIGURE
OIP3
Figure 3. AMP1: Gain, P1dB, OIP3 at POUT = 3 dBm/Tone and Noise Figure vs.
Frequency
17.0
17.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
00.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
–40°C
+85°C
GAIN (d B)
FRE QUENCY ( GHz)
+25°C
09431-004
Figure 4. AMP1: Gain vs. Frequency and Temperature
–50
–40
–45
–35
–30
–25
–20
–15
–10
–5
0
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
S12
S-PARAMETERS (dB)
FRE QUENCY ( GHz)
S11
S22
09431-005
Figure 5. AMP1: Input Return Loss (S11), Output Return Loss (S22), and
Reverse Isolation (S12) vs. Frequency
16
14
28
26
24
22
20
18
10
45
40
35
30
25
20
15
P1d B ( dBm)
OIP3 (dBm)
FRE QUENCY ( GHz)
00.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
–40°C
+25°C
+85°C
09431-006
Figure 6. AMP1: OIP3 at POUT = 3 dBm/Tone and P1dB vs. Frequency and
Temperature
22
20
42
40
38
36
34
32
30
28
26
24
–4 1614121086420–2
OIP3 (dBm)
P
OUT
PER TONE ( dBm)
150MHz
450MHz
748MHz
943MHz
1960MHz 2140MHz
2630MHz
3600MHz
09431-007
Figure 7. AMP1: OIP3 vs. POUT and Frequency
1.5
2.0
2.5
3.0
3.5
4.0
5.0
4.5
04.03.63.22.82.42.01.61.20.80.4
NOISE FIGURE (dB)
FRE QUENCY ( GHz)
–40°C
+25°C
+85°C
09431-008
Figure 8. AMP1: Noise Figure vs. Frequency and Temperature
Data Sheet ADL5243
Rev. B | Page 13 of 40
0
5
10
15
20
25
30
35
40
50
45
0.925 0.930 0.935 0.940 0.945 0.950 0.955 0.960 0.965
OIP3
P1dB
GAIN
NF
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FRE QUENCY ( GHz)
09431-009
Figure 9. AMP2–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise
Figure vs. Frequency
FRE QUENCY ( GHz)
15.0
18.0
17.5
17.0
16.5
16.0
15.5
–40°C
+85°C
GAIN (d B)
FRE QUENCY ( GHz)
+25°C
09431-010
0.925 0.930 0.935 0.940 0.945 0.950 0.955 0.960 0.965
Figure 10. AMP2–943 MHz: Gain vs. Frequency and Temperature
–35
–30
–25
–20
–15
–10
–5
0
S-PARAMETERS (dB)
FRE QUENCY ( GHz)
0.80 0.85 0.90 0.95 1.00 1.05 1.10
S12
S11
S22
09431-011
Figure 11. AMP2–943 MHz: Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
24.5
24.0
27.0
26.5
26.0
25.5
25.0
33
45
43
41
39
37
35
P1d B ( dBm)
OIP3 (dBm)
FRE QUENCY ( GHz)
–40°C
+25°C
+85°C
09431-012
0.925 0.930 0.935 0.940 0.945 0.950 0.955 0.960 0.965
Figure 12. AMP2–943 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs.
Frequency and Temperature
38
37
45
44
43
42
41
40
39
–4 1816121086420–2
OIP3 (dBm)
P
OUT
PER TONE ( dBm)
14
925MHz
943MHz
961MHz
09431-013
Figure 13. AMP2–943 MHz: OIP3 vs. POUT and Frequency
3.5
4.5
5.0
5.5
6.0
6.5
7.5
7.0
0.80 1.101.071.041.010.980.950.920.890.860.83
NOISE FIGURE (dB)
FRE QUENCY ( GHz)
4.0
–40°C
–40°C
+25°C
+85°C
09431-014
Figure 14. AMP2–943 MHz: Noise Figure vs. Frequency and Temperature
ADL5243 Data Sheet
Rev. B | Page 14 of 40
0
5
10
15
20
25
30
35
40
45
2.11 2.12 2.13 2.14 2.15 2.16 2.17
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (GHz)
P1dB
OIP3
GAIN
NF
09431-015
Figure 15. AMP2–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and
Noise Figure vs. Frequency
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
GAIN (d B)
–40°C
+25°C
+85°C
2.11 2.12 2.13 2.14 2.15 2.16 2.17
FREQUENCY (GHz)
09431-016
Figure 16. AMP2–2140 MHz: Gain vs. Frequency and Temperature
–30
–25
–20
–15
–10
–5
0
S-PARAMETERS (dB)
FRE QUENCY ( GHz)
2.00 2.05 2.10 2.15 2.20 2.25 2.30
S12
S11
S22
09431-017
Figure 17. AMP2–2140 MHz: Input Return Loss (S11), Output Return Loss
(S22), and Reverse Isolation (S12) vs. Frequency
31
33
35
37
39
41
43
25.0
25.5
26.0
26.5
27.0
27.5
28.0
OIP3 (dBm)
P1d B ( dBm)
–40°C
+25°C
+85°C
2.11 2.12 2.13 2.14 2.15 2.16 2.17
FREQUENCY (GHz)
09431-018
Figure 18. AMP2–2140 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs.
Frequency and Temperature
34
35
36
37
38
39
40
41
42
–6 –4 –2 0246810 12 14 16 18 20 22
OIP3 (dBm)
P
OUT
PER TONE (dBm)
2.11GHz
2.14GHz
2.17GHz
09431-019
Figure 19. AMP2–2140 MHz: OIP3 vs. POUT and Frequency
2.0
2.5
3.0
3.5
4.0
4.5
5.5
5.0
2.00 2.302.272.242.212.182.152.122.092.062.03
NOISE FIGURE (dB)
FRE QUENCY ( GHz)
–40°C
+25°C
+85°C
09431-020
Figure 20. AMP2–2140 MHz: Noise Figure vs. Frequency and Temperature
Data Sheet ADL5243
Rev. B | Page 15 of 40
0
5
10
15
20
25
30
35
40
45
2.57 2.59 2.61 2.63 2.65 2.67 2.69
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (GHz)
P1dB
OIP3
GAIN
NF
09431-021
Figure 21. AMP2–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and
Noise Figure vs. Frequency
12.0
12.5
11.0
11.5
13.0
13.5
14.0
14.5
15.0
GAIN (d B)
–40°C
+25°C
+85°C
2.57 2.59 2.61 2.63 2.65 2.67 2.69
FREQUENCY (GHz)
09431-022
Figure 22. AMP2–2630 MHz: Gain vs. Frequency and Temperature
–30
–25
–20
–15
–10
–5
0
S-PARAMETERS (dB)
FRE QUENCY ( GHz)
2.50 2.55 2.60 2.65 2.70 2.75 2.80
S12
S11
S22
09431-023
Figure 23. AMP2–2630 MHz: Input Return Loss (S11), Output Return Loss
(S22), and Reverse Isolation (S12) vs. Frequency
23.0
23.5
24.5
25.5
26.5
27.5
24.0
25.0
26.0
27.0
28.0
37.0
37.5
38.5
39.5
40.5
41.5
38.0
39.0
40.0
41.0
42.0
OIP3 (dBm)
P1d B ( dBm)
–40°C
+25°C
+85°C
2.57 2.59 2.61 2.63 2.65 2.67 2.69
FREQUENCY (GHz)
09431-024
Figure 24. AMP2–2630 MHz: OIP3 at POUT = 5 dBm/Tone and P1dB vs.
Frequency and Temperature
30
32
34
36
31
33
35
37
38
39
40
41
42
–6 –4 –2 0246810 12 14 16 18 20 22
OIP3 (dBm)
P
OUT
PER TONE (dBm)
2.57GHz
2.63GHz
2.69GHz
09431-025
Figure 25. AMP2–2630 MHz: OIP3 vs. POUT and Frequency
2.0
2.5
3.0
3.5
4.0
4.5
6.0
5.5
5.0
2.50 2.802.772.742.712.682.652.622.592.562.53
NOISE FIGURE (dB)
FRE QUENCY ( GHz)
–40°C
+25°C
+85°C
09431-026
Figure 26. AMP2–2630 MHz: Noise Figure vs. Frequency and Temperature
ADL5243 Data Sheet
Rev. B | Page 16 of 40
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1 4.13.73.32.92.52.11.71.30.90.5
ATTENUAT ION ( dB)
FRE QUENCY ( GHz)
31.5dB
09431-027
0dB
Figure 27. DSA: Attenuation vs. Frequency
–36
–31
–26
–21
–16
–11
–6
–1
0.1 4.13.73.32.92.52.11.71.30.90.5
ATTENUAT ION ( dB)
FRE QUENCY ( GHz)
0dB
4dB
8dB
16dB
31.5dB
–40°C
+25°C
+85°C
09431-028
Figure 28. DSA: Attenuation vs. Frequency and Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
032282420161284
STEP ERROR (dB)
ATTENUAT ION ( dB)
450MHz
748MHz
943MHz
1960MHz
2140MHz
2630MHz
3600MHz
09431-029
Figure 29. DSA: Step Error vs. Attenuation
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
03228242016128
4
ABSO LUTE E RROR (d B)
ATTENUAT ION ( dB)
450MHz
748MHz
943MHz
1960MHz
2140MHz
2630MHz
3600MHz
09431-030
Figure 30. DSA: Absolute Error vs. Attenuation
–30
–25
–20
–15
–10
–5
0
0.1 4.13.73.32.92.52.11.71.30.90.5
INP UT RET URN LOS S ( dB)
FRE QUENCY ( GHz)
31.5dB
09431-031
0dB
Figure 31. DSA: Input Return Loss vs. Frequency, All States
–30
–25
–20
–15
–10
–5
0
0.1 4.13.73.32.92.52.11.71.30.90.5
OUTPUT RE TURN LOSS ( dB)
FRE QUENCY ( GHz)
09431-032
31.5dB
0dB
Figure 32. DSA: Output Return Loss vs. Frequency, All States
Data Sheet ADL5243
Rev. B | Page 17 of 40
25
30
35
40
45
55
50
30
31
32
33
34
35
36
0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
IIP3 (dBm)
IP 1dB (d Bm)
FREQUENCY (GHz)
IIP3
IP1dB
09431-033
Figure 33. DSA: Input P1dB and Input IP3 vs. Frequency, Minimum
Attenuation State
CH3 2.00VCH3 2.00V CH4 200mV M10n s 10GS/ s
IT 1.0ps/pt A CH3 1.24V
3
4
09431-034
Figure 34. DSA: Gain Settling Time, 0 dB to 31.5 dB
CH3 2.00VCH3 2.00V CH4 200mV M10n s 10GS/ s
IT 1.0ps/pt A CH3 1.24V
3
4
09431-035
Figure 35. DSA: Gain Settling Time, 31.5 dB to 0 dB
–150
–100
–50
0
50
100
150
04812 16 20 24 28 32
PHASE ( Degrees)
ATTENUATION (dB)
943MHz
1960MHz
2140MHz
2630MHz
09431-036
Figure 36. DSA: Phase vs. Attenuation
0
5
10
15
20
25
30
35
40
45
50
925 930 935 940 945 950 955 960 965
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (MHz)
P1dB
OIP3
GAIN
NF
09431-037
Figure 37. Loop–943 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise
Figure vs. Frequency, Minimum Attenuation State
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10
S-PARAM E TERS ( dB)
FREQUENCY (GHz)
S11
S12
S22
09431-038
Figure 38. Loop–943 MHz: Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
ADL5243 Data Sheet
Rev. B | Page 18 of 40
32
34
36
38
40
42
44
46
46810 12 14 16 18 20 22
OIP3 (dBm)
P
OUT
PER TONE (dBm)
925MHz
943MHz
961MHz
09431-039
Figure 39. Loop–943 MHz: OIP3 vs. POUT and Frequency, Minimum
Attenuation State
0
5
10
15
20
25
30
35
40
45
2.11 2.12 2.13 2.14 2.15 2.16 2.17
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (GHz)
P1
dB
OIP3
GAIN
NF
09431-040
Figure 40. Loop–2140 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise
Figure vs. Frequency, Minimum Attenuation State
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
2.00 2.05 2.10 2.15 2.20 2.25 2.30
S-PARAM E TERS ( dB)
FREQUENCY (GHz)
S11
S12
S22
09431-041
Figure 41. Loop–2140 MHz: Input Return Loss (S11), Output Return Loss
(S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
34
35
36
37
38
39
40
42
41
1 3 5 7 9 11 13 15 17 19 21
OIP3 (dBm)
P
OUT
PER TONE (dBm)
2.11GHz
2.14GHz
2.17GHz
09431-042
Figure 42. Loop–2140 MHz: OIP3 vs. POUT and Frequency, Minimum
Attenuation State
0
5
10
15
20
25
30
35
40
45
2.57 2.59 2.61 2.63 2.65 2.67 2.69
NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm)
FREQUENCY (GHz)
P1
dB
OIP3
GAIN
NF
09431-043
Figure 43. Loop–2630 MHz: Gain, P1dB, OIP3 at POUT = 5 dBm/Tone and Noise
Figure vs. Frequency, Minimum Attenuation State
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
S-PARAM E TERS ( dB)
FREQUENCY (GHz)
S12
S22
S11
09431-044
Figure 44. Loop–2630 MHz: Input Return Loss (S11), Output Return Loss
(S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
Data Sheet ADL5243
Rev. B | Page 19 of 40
33
34
35
36
37
38
39
40
42
41
0 2 4 6 8 10 12 14 16 18
OIP3 (dBm)
P
OUT
PER TONE (dBm)
2.57GHz
2.63GHz
2.69GHz
09431-045
Figure 45. Loop–2630 MHz: OIP3 vs. POUT and Frequency, Minimum
Attenuation State
70
75
80
85
90
95
100
105
110
–40 –30 –20 –10 010 20 30 40 50 60 70 80 90
SUPPLY CURRENT ( mA)
TEMPERATURE (°C)
4.75V
5.00V
5.25V
09431-046
Figure 46. AMP1: Supply Current vs. Voltage and Temperature
70
75
80
85
90
95
100
105
–6 –4 –2 0246810 12 14 16 18 20
22
SUPPLY CURRENT ( mA)
P
OUT
PER TONE (dBm)
+25°C
–40°C
+85°C
09431-147
Figure 47. AMP1: Supply Current vs. POUT and Temperature
60
110
105
100
95
90
80
70
65
75
85
–40 –30 –20 –10 010 20 30 40 50 60 70 80 90
SUPP LY CURRENT (mA)
TEMPERATURE (°C)
5.25V
5.00V
5.00V
4.75V
09431-047
Figure 48. AMP2: Supply Current vs. Voltage and Temperature
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
–6 –4 –2 0246810 12 14 16 18 20 22 24 26
SUPPLY CURRENT ( mA)
POUT PER TONE (dBm)
+25°C
–40°C
+85°C
09431-149
Figure 49. AMP2: Supply Current vs. POUT and Temperature
ADL5243 Data Sheet
Rev. B | Page 20 of 40
0
5
10
15
20
25
30
35
40
45
18.3
18.4
18.5
18.6
18.7
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
PERCENTAGE (%)
GAIN (d B)
09431-048
Figure 50. AMP1: Gain Distribution at 2140 MHz
0
5
10
15
20
25
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
20.5
PERCENTAGE (%)
P1d B ( dBm)
09431-049
Figure 51. AMP1: P1dB Distribution at 2140 MHz
0
5
10
15
20
25
30
35
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PERCENTAGE (%)
OIP3 (dBm)
09431-050
Figure 52. AMP1: OIP3 Distribution at 2140 MHz
0
10
20
30
40
50
60
70
80
90
100
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
PERCENTAGE (%)
NOISE FIGURE (dB)
09431-051
Figure 53. AMP1: Noise Figure Distribution at 2140 MHz
0
5
10
15
20
25
30
35
40
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
PERCENTAGE (%)
GAIN (d B)
09431-052
Figure 54. AMP2: Gain Distribution at 2140 MHz
0
5
10
15
20
25
30
35
40
45
50
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
26.0
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
PERCENTAGE (%)
P1d B ( dBm)
09431-053
Figure 55. AMP2: P1dB Distribution at 2140 MHz
Data Sheet ADL5243
Rev. B | Page 21 of 40
0
10
20
30
40
50
60
70
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PERCENTAGE (%)
OIP3 (dBm)
09431-054
Figure 56. AMP2: OIP3 Distribution at 2140 MHz
0
10
20
30
40
50
60
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
PERCENTAGE (%)
NOISE FIGURE (dB)
09431-055
Figure 57. AMP2: Noise Figure Distribution at 2140 MHz
ADL5243 Data Sheet
Rev. B | Page 22 of 40
APPLICATIONS INFORMATION
BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5243 are shown in Figure 58. The schematic of AMP2 is configured for 2140 MHz operation.
NC
VDD
NC
VBIAS
NC
NC
NC
NC D1/DATA
NC
D2/LE
D3
D5
D4
DSAOUT
NC
NC
D6
NC
AMP2IN
D0/CLK
SEL
AMP2OUT/VCC2
NC
NC
VDD
DSAIN
ADL5243
NC
NC
AMP1OUT/VCC
NC
SERIAL P ARALLE L INTERFACE
AMP1IN
VDD
100pF
VDD
0.01µF
AMP1IN
DSAIN DSAOUT
0.1µF
C21
C1
100pF
AMP1OUT
C4
0.1µF
C5
2.2pF
AMP2IN
C27 10pF
C8
C17
1.8pF
C28
1
2
3
4
5
6
7
8
910 161514131211
24
23
22
21
20
19
18
17
32 31 252627282930
C15
VCC
L1
470nH
68pF
C14
1.2nF
C13
1µF C3
AMP2OUT
C23
C22
L2
C25 C20
1pF
10µF
10pF
9.5nH
10nF
10pF
VCC2
09431-056
Figure 58. Basic Connections
Data Sheet ADL5243
Rev. B | Page 23 of 40
Amplifier 1 Power Supply
AMP1 in the ADL5243 is a broadband gain block. The dc bias is
supplied through Inductor L1 and is connected to the
AMP1OUT pin. Three decoupling capacitors (C13, C14, and
C25) are used to prevent RF signals from propagating on the dc
lines. The dc supply ranges from 4.75 V to 5.25 V and should be
connected to the VCC test pin.
Amplifier 1 RF Input Interface
Pin 10 is the RF input for AMP1 of the ADL5243. The amplifier
is internally matched to 50 Ω at the input; therefore, no external
components are required. Only a dc blocking capacitor (C21) is
required.
Amplifier 1 RF Output Interface
Pin 6 is the RF output for AMP1 of the ADL5243. The amplifier
is internally matched to 50 Ω at the output as well; therefore, no
external components are required. Only a dc blocking capacitor
(C4) is required. The bias is provided through this pin via a
choke inductor, L1.
Amplifier 2 Power Supply
The collector bias for AMP2 is supplied through Inductor L2
and is connected to the AMP2OUT pin, whereas the base bias is
provided through Pin 16. The base bias is connected to the
same supply pin as the collector bias. Three decoupling
capacitors (C3, C20, and C25) are used to prevent RF signals
from propagating on the dc lines. The dc supply ranges from
4.75 V to 5.25 V and should be connected to the VCC2 test pin.
Amplifier 2 RF Input Interface
Pin 19 is the RF input for AMP2 of the ADL5243. The input of
the amplifier is easily matched to 50 Ω with a combination of
series and shunt capacitors and a microstrip line serving as an
inductor. Figure 58 shows the input matching components and
is configured for 2140 MHz.
Amplifier 2 RF Output Interface
Pin 15 is the RF input for AMP2 of the ADL5243. The output of
the amplifier is easily matched to 50 Ω with a combination of series
and shunt capacitors and a microstrip line serving as an inductor.
Additionally, bias is provided through this pin. Figure 58 shows
the output matching components and is configured for 2140 MHz.
DSA RF Input Interface
Pin 4 is the RF input for the DSA of the ADL5243. The input
impedance of the DSA is close to 50 Ω over the entire frequency
range; therefore, no external components are required. Only a
dc blocking capacitor (C1) is required.
DSA RF Output Interface
Pin 21 is the RF output for the DSA of the ADL5243. The
output impedance of the DSA is close to 50 Ω over the entire
frequency range; therefore, no external components are
required. Only a dc blocking capacitor (C5) is required.
DSA SPI Interface
The DSA of the ADL5243 can operate in either serial or parallel
mode. Pin 32 (SEL) controls the mode of operation. For serial
mode operation, connect SEL to ground, and for parallel mode
operation, connect SEL to VDD. In parallel mode, Pin 25 to Pin
30 (D6 to D1) are the data bits, with D6 being the LSB. Connect
Pin 31 (D0) to ground during parallel mode of operation. In
serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data
(DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28
are not used in the serial mode and should be connected to
ground. Pin 25 (D6) should be connected to VDD during the
serial mode of operation. To prevent noise from coupling onto
the digital signals, an RC filter can be used on each data line.
SPI TIMING
SPI Timing Sequence
Figure 60 shows the timing sequence for the SPI function using
a 6-bit operation. The clock can be as fast as 20 MHz. In serial
mode operation, Register B5 (MSB) is first, and Register B0
(LSB) is last.
Table 4. Mode Selection Table
Pin 32 (SEL) Functionality
Connect to Ground Serial mode
Connect to Supply Parallel mode
Table 5. SPI Timing Specifications
Parameter Limit Unit Test Conditions/Comments
FCLK 10 MHz Data clock frequency
t1 30 ns min Clock high time
t2 30 ns min Clock low time
t3 10 ns min Data to clock setup time
t4 10 ns min Clock to data hold time
t5 10 ns min Clock low to LE setup time
t6 30 ns min LE pulse width
ADL5243 Data Sheet
Rev. B | Page 24 of 40
CLK
DATA
LE
B4 B3 B1
MSB
B5 LSB
B0
B2
t
6
t
5
t
1
t
2
t
4
t
3
09431-057
Figure 59. SPI Timing Diagram (Data Loaded MSB First)
B4 B3 B1
MSB
B5 LSB
B0
B2
D0/CLK
D1/DATA
D2/LE
D6
09431-058
Figure 60. SPI Timing Sequence
Table 6. DSA Attenuation Truth Table—Serial Mode
Attenuation State B5 (MSB) B4 B3 B2 B1 B0 (LSB)
0 dB (Reference) 1 1 1 1 1 1
0.5 dB 1 1 1 1 1 0
1.0 dB
1
1
1
1
0
1
2.0 dB 1 1 1 0 1 1
4.0 dB 1 1 0 1 1 1
8.0 dB 1 0 1 1 1 1
16.0 dB 0 1 1 1 1 1
31.5 dB
0
0
0
0
0
0
Table 7. DSA Attenuation Truth Table—Parallel Mode
Attenuation State D1 (MSB) D2 D3 D4 D5 D6 (LSB)
0 dB (Reference) 1 1 1 1 1 1
0.5 dB 1 1 1 1 1 0
1.0 dB 1 1 1 1 0 1
2.0 dB 1 1 1 0 1 1
4.0 dB 1 1 0 1 1 1
8.0 dB
1
0
1
1
1
1
16.0 dB 0 1 1 1 1 1
31.5 dB 0 0 0 0 0 0
Data Sheet ADL5243
Rev. B | Page 25 of 40
ADL5243 AMPLIFIER 2 MATCHING
The AMP2 input and output of the ADL5243 can be matched to
50 Ω with two or three external components and the microstrip
line used as an inductor. Table 8 lists the required matching
components values. All capacitors are Murata GRM155 series
(0402 size), and Inductor L2 is a Coilcraft® 0603CS series (0603
size). For all frequency bands, the placement of Capacitors C22,
C26, and C28 is critical.
Tabl e 9 lists the recommended component spacing of C22, C26,
and C28 for the various frequencies. The placement of R12 and
C27 is fixed for the matching network on evaluation board and
the spacing is 153 mils and 25 mils respectively. The component
spacing is referenced from the center of the component to the
edge of the package. Figure 61 to Figure 69 show the graphical
representation of the matching network. It is recommended to
configure a RC feedback network and bias the AMP2 input
through external R for optimal performance at frequency bands
less than 500 MHz as shown at Figure 61 and Figure 62. In this
case, VBIAS pin must be left open.
Table 8. Component Values on Evaluation Board
Frequency C27 C26 C28 C8 C22 C23 L2 R10 R201 R12 R16 R15 C10 R31 R30
150 MHz 2.7n H 1.5 pF N/A 1500 pF 0.5 pF 4700 pF 390 nH 21 Ω N/A 22 nH 3.16 kΩ 750 Ω 1 nF 0 Ω N/A
450 MHz 0 Ω N/A 5.1pF 1000 pF 0.5 pF 1000 pF 110 nH 21 Ω 5.6 Ω 3.9 nH 3.16 kΩ 750 Ω 1 nF 0 Ω N/A
748 MHz 0 Ω N/A 5.1 pF 12 pF 1.3 pF 18 pF 56 nH 18 Ω 5.6 Ω 3.9 nH N/A N/A N/A N/A 0 Ω
943 MHz 0 Ω 3.9 pF N/A 6 pF 1.3 pF 100 pF 56 nH 18 Ω N/A 3.3 nH N/A N/A N/A N/A 0 Ω
1960 MHz 2.7 pF N/A 1.0 pF 10 pF 1.0 pF 20 pF 9.5 nH 0 Ω N/A 0 Ω N/A N/A N/A N/A 0 Ω
2140 MHz 2.2 pF N/A 1.8 pF 10 pF 1.0 pF 10 pF 9.5 nH 0 Ω N/A 0 Ω N/A N/A N/A N/A 0 Ω
2350 MHz 3.3 pF 1.6 pF 1.5 KΩ 10 pF 1.0 pF 20 pF 9.5 nH 0 Ω N/A 0 Ω N/A N/A N/A N/A 0 Ω
2630 MHz 2.7 pF 1.1 pF 1.5 KΩ 10 pF 1.3 pF 20 pF 9.5 nH 0 Ω N/A 0 Ω N/A N/A N/A N/A 0 Ω
3600 MHz 1.0 pF 1.5 KΩ 1.2 pF 10 pF 1.2 pF 20 pF 9.5 nH 0 Ω N/A 1.0 nH N/A N/A N/A N/A 0 Ω
1 R20 is not reserved on the evaluation board.
Table 9. Component Spacing on Evaluation Board
Frequency
C26 : λ1(mils)
C28 : λ2(mils)
C22 : λ3(mils)
150 MHz 213 N/A 408
450 MHz N/A 230 485
748 MHz N/A 315 201
943 MHz
236
N/A
394
1960 MHz N/A 366 244
2140 MHz N/A 366 244
2350 MHz 153 195 244
2630 MHz 126 161 240
3600 MHz 342 366 106
ADL5243 Data Sheet
Rev. B | Page 26 of 40
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27
L2
390nH
NC
ADL5243
2.7nH
λ1
λ3
NC
NC
C8
1500pF
C26
1.5pF
R10
21Ω
R12
22nH
C22
0.5pF
C23
4700pF
750Ω
1nF
VCC
3.16kΩ
C10
R16
R15
R31
0Ω
09431-161
Figure 61. AMP2: Matching Circuit at 150 MHz
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27
C28
L2
110nH
NC
ADL5243
0Ω
λ2
λ3
NC
NC
C8
1000pF
5.1pF
R10
21Ω
R12
3.9nH
C22
0.5pF
C23
1000pF
1nF
VCC
3.16kΩ
5.6Ω
R31
0Ω
R15
750Ω
R20
C10
R16
09431-162
Figure 62. AMP2: Matching Circuit at 450 MHz
Data Sheet ADL5243
Rev. B | Page 27 of 40
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT/VCC2
VBIAS
AMP2IN
C27
0Ω
C28
L2
56nH
NC
ADL5243
λ2
λ3
NC
NC
5.1pF C8
12pF
R10
18Ω
R20
5.6Ω
R12
3.9nH
C22
1.3pF
C23
18pF
09431-061
Figure 63. AMP2: Matching Circuit at 748 MHz
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27
L2
56nH
NC
ADL5243
0Ω
λ1
λ3
NC
NC
C8
6pF
C26
3.9pF
R10
18Ω
R12
3.3nH
C22
1.3pF
C23
100pF
09431-062
Figure 64. AMP2: Matching Circuit at 943 MHz
ADL5243 Data Sheet
Rev. B | Page 28 of 40
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27 C28
L2
9.5nH
NC
ADL5243
2.7pF
λ2
λ3
NC
NC
1.0pF C8
10pF
R10
0Ω
R12
0Ω
C22
1.0pF
C23
20pF
09431-165
Figure 65. AMP2: Matching Circuit at 1960 MHz
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT/VCC2
VBIAS
AMP2IN
C27 C28
L2
9.5nH
NC
ADL5243
2.2pF
λ2
λ3
NC
NC
1.8pF C8
10pF
R10
0Ω
R12
0Ω
C22
1pF
C23
10pF
09431-064
Figure 66. AMP2: Matching Circuit at 2140 MHz
Data Sheet ADL5243
Rev. B | Page 29 of 40
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27 C28
L2
9.5nH
NC
ADL5243
3.3pF
λ2
λ1
λ3
NC
NC
1.5kΩ C8
10pF
C26
1.6pF
R10
0Ω
R12
0Ω
C22
1.0pF
C23
20pF
09431-167
Figure 67. AMP2: Matching Circuit at 2350 MHz
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27 C28
L2
9.5nH
NC
ADL5243
2.7pF
λ2
λ1
λ3
NC
NC
1.5kΩ
C8
10pF
C26
1.1pF
R10
0Ω
R12
0Ω
C22
1.3pF
C23
20pF
09431-065
Figure 68. AMP2: Matching Circuit at 2630 MHz
ADL5243 Data Sheet
Rev. B | Page 30 of 40
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT//VCC2
VBIAS
AMP2IN
C27 C28
L2
R12
1nH
9.5nH
NC
ADL5243
1.0pF
λ2
λ1
λ3
NC
NC
1.2pF C8
10pF
C26
1.5kΩ
R10
0Ω
R12
0Ω
C22
1.2pF
C23
20pF
09431-169
Figure 69. AMP2: Matching Circuit at 3600 MHz
Data Sheet ADL5243
Rev. B | Page 31 of 40
ADL5243 LOOP PERFORMANCE
The typical configuration of the ADL5243 is to connect in
AMP1-DSA-AMP2 mode, as shown in Figure 70. Because AMP1
and DSA are broadband in nature and internally matched, only an
ac coupling capacitor is required between them. The AMP2 is
externally matched for each frequency band of operation, and these
matching elements should be placed between the DSA and AMP2
and at the output of AMP2. Matching circuits for AMP2 are shown
in Figure 61 through Figure 69. This works well in a loop in each
case but matching circuits between the DSA and AMP2 requires
slight retuning, such as adding a shunt capacitor at the DSA
output or changing the location of a shunt capacitor for optimum
performance in a loop at certain frequency bands. Figure 71
and Figure 72 show the retuned matching circuits from Figure
66 and Figure 69 at 2140 MHz and 3600 MHz, respectively.
Figure 37 to Figure 45 show the performance of the ADL5243
when connected in a loop for the three primary frequency bands of
operation, namely 943 MHz, 2140 MHz, and 2630 MHz.
Table 10. Component Spacing in a Loop on Evaluation Board
Frequency C26: λ1
(mils)
C28: λ2
(mils)
C22: λ3
(mils)
C11: λ4
(mils)
2140 MHz N/A 366 244 122
3600 MHz 126 342 106 N/A
AMP1
RFIN
ADL5243
AMP2
DSA IMN OMN RFOUT
VCC2
VCC VDD/SPI
09431-067
Figure 70. ADL5243 Loop Block Diagram
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT/VCC2
VBIAS
C27 C28
L2
9.5nH
NC
ADL5243
2.2pF
λ2
λ3
NC
NC
1.8pF C6
10pF
R33
0Ω
R12
0Ω
C22
1pF
C23
10pF
21
DSAOUT
λ4
C11
1.3pF
09431-171
Figure 71. ADL5243 Matching Circuit at 2140 MHz in a Loop
AMP2OUT
20
19
18
17
13 14 15 16
AMP2IN
NC
NC
AMP2OUT/VCC2
VBIAS
C27 C28
L2
9.5nH
NC
ADL5243
1.0pF
λ2
λ1
λ3
NC
NC
1.5kΩ C6
10pF
C26
1.2pF
R33
0Ω
R12
1.2nH
C22
1pF
C23
10pF
21
DSAOUT
09431-172
Figure 72. ADL5243 Matching Circuit at 3600 MHz in a Loop
ADL5243 Data Sheet
Rev. B | Page 32 of 40
PROPER DRIVING LEVEL FOR THE OPTIMUM ACLR
It is usually required to drive the amplifier as high as possible in
order to maximize output power. However, properly driving AMP1
and AMP2 at the ADL5243 is required to achieve optimum ACLR
performance. Once output power approaches P1dB and OIP3,
there is ACLR degradation. The driving level of amplifier with a
modulated signal should be backed off properly from P1dB by
at least the amount of a signal crest factor for optimum ACLR.
So assuming a gain and P1dB of AMP1 at 2140 MHz are 19 dB
and 19 dBm respectively, the output power, which is backed off by
11 dB crest factor at the modulated signal case, is 8 dBm. Therefore,
the proper input driving level should be under −11 dBm.
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–40 –36 –32 –28 –24 –20 –16 –12 –8 –4 048
ACLR ( dBc)
PIN (dBm)
AMP1, ADJ AMP2, ADJ
AMP1, ALT AMP2, ALT
09431-173
Figure 73. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input
Power at AMP1 and AMP2, 2140 MHz
THERMAL CONSIDERATIONS
The ADL5243 is packaged in a thermally efficient, 5 mm × 5 mm,
32-lead LFCSP. The thermal resistance from junction to air (θJA)
is 34.8°C/W. The thermal resistance for the product was extracted
assuming a standard 4-layer JEDEC board with 25 copper platter
thermal vias. The thermal vias are filled with conductive copper
paste, AE3030, with a thermal conductivity of 7.8 W/mk and
thermal expansion as follows: α1 of 4 × 10−5/°C and α2 of 8.6 ×
10−5/°C. The thermal resistance from junction to case (θJC) is
6.2°C/W, where case is the exposed pad of the lead frame package.
For the best thermal performance, it is recommended to add as
many thermal vias as possible under the exposed pad of the
LFCSP. The above thermal resistance numbers assume a
minimum of 25 thermal vias arranged in a 5 × 5 array with a via
diameter of 13 mils, via pad of 25 mils, and pitch of 25 mils. The
vias are plated with copper, and the drill hole is filled with a
conductive copper paste. For optimal performance, it is
recommended to fill the thermal vias with a conductive paste of
equivalent thermal conductivity, as mentioned above, or use an
external heat sink to dissipate the heat quickly without affecting
the die junction temperature. It is also recommended to extend
the ground pattern as shown in Figure 74 to improve thermal
efficiency.
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 74 shows the recommended land pattern for the ADL5243.
To minimize thermal impedance, the exposed paddle on the
5 mm × 5 mm LFCSP package is soldered down to a ground
plane. To improve thermal dissipation, 25 thermal vias are
arranged in a 5 × 5 array under the exposed paddle. If multiple
ground layers exist, they should be tied together using vias. For
more information on land pattern design and layout, see the
AN-772 Application Note, A Design and Manufacturing Guide for
the Lead Frame Chip Scale Package (LFCSP).
1
DSAIN DSAOUT
25 MI L VI A P AD
WITH 13 MIL VIA 8
24
17
09431-068
Figure 74. Recommended Land Pattern
Data Sheet ADL5243
Rev. B | Page 33 of 40
EVALUATION BOARD
The schematic of the ADL5243 evaluation board is shown in
Figure 75. All RF traces on the evaluation board have a charac-
teristic impedance of 50 Ω and are fabricated from Rogers3003
material. The traces are CPWG with a width of 25 mils, spacing
of 20 mils, and dielectric thickness of 10 mils. The input and output
to the DSA and amplifier should be ac-coupled with capacitors
of an appropriate value to ensure broadband performance. The
bias to AMP1 is provided through a choke connected to the
AMP1OUT pin and, similarly, bias to AMP2 is provided through
a choke connected to the AMP2OUT pin. Bypassing capacitors
are recommended on all supply lines to minimize RF coupling.
The DSA and the amplifiers can be individually biased or
connected to the VDD plane through Resistors R1, R2, and R11.
The schematic of AMP2 on evaluation board is configured for
2140 MHz operation.
When configuring the ADL5243 evaluation board in the
AMP1-DSA-AMP2 loop, remove Capacitors C1, C4, C5, and
C8 and remove Resistor R10. Place 10 pF in place of C24 and
C6, and 0 Ω in place of R32 and R33. If needed, placing a shunt
capacitor (1.3 pF) at the output of the DSA improves the output
return loss of this loop as described at the ADL5243 Loop
Performance section.
On the digital signal traces, provisions for an RC filter are made
to clean any potential coupled noise. In normal operation, series
resistors are 0 Ω and shunt resistors and capacitors are open.
The evaluation board is designed to control DSA in either parallel
or serial mode by connecting the SEL pin to the supply or ground
by a switch.
For adjusting attenuation at DSA, the ADL5243 can be programmed
in two ways: through the on-board USB interface from a PC USB
port, or through an SDP board, which will become the Analog
Devices common control board in the future. The on-board USB
interface circuitry of the evaluation board is powered directly by
the PC. USB based programming software is available to download
from the ADL5243 product page at www.analog.com. Figure 71
shows the window of the programming software where the user
selects serial or parallel mode for the attenuation adjustment at
DSA. The selection of the mode in the window should match
the mode of the evaluation board switch.
It is highly recommended to refer the evaluation board layout
for the optimal and stable performance of each block as well as
for the improvement of thermal efficiency.
Table 11. Evaluation Board Configurations Options
Component Function Default Value
C1, C5 AC coupling caps for DSA. C1, C5 = 10 pF
C4, C21 AC coupling capacitors for AMP1. C4, C21 = 10 pF
C13, C14, C15
Power supply bypassing capacitors for AMP1. Capacitor C15 should be closest to the device.
C13 = 10 μF
C14 = 10 nF
C15 = 10 pF
L1
The bias for AMP1 comes through L1 when connected to a 5 V supply. L1 should be high
impedance for the frequency of operation, while providing low resistance for the dc current.
L1 = 33 nH
C8 AMP2 input ac coupling capacitor. C8 = 10 pF
C23 AMP2 output ac coupling capacitor. C23 = 10 pF
C22 AMP2 shunt output tuning capacitor. C22 = 1.0 pF at 244 mils
from edge of package
C26
ANP2 shunt input tuning capacitor.
DNP
C27 AMP2 series input tuning capacitor. C27 = 2.2 pF
C28 AMP2 shunt input tuning capacitor. C28 = 1.8 pF at 366 mils
from edge of package
C3, C25, C20 Power supply bypassing capacitors for AMP2. Capacitor C3 should be closest to the device. C3 = 10 pF
C25 = 10 nF
C20 = 10 μF
L2 The bias for AMP2 comes through L2 when connected to a 5 V supply. L2 should be high
impedance for the frequency of operation, while providing low resistance for the dc current.
L2 = 9.5 nH
C17 Power supply bypassing capacitor for DSA. C17 = 0.1 μF
R10, R12 Placeholder for the series component for the other frequency band. R10, R12 = 0 Ω
C6, C24, R32, R33 Replace with capacitors and resistors to connect the device in a loop. C6, C24, R32, R33 = open
R1, R2, R11 Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. R1, R2 = open
S1 Switch to change between serial and parallel mode operation; connect to a supply for
parallel mode and to ground for serial mode operation.
3-pin rocker
ADL5243 Data Sheet
Rev. B | Page 34 of 40
09431-069
DNI
0Ω
R31
L2
9.5nH
0Ω
R30
0.001µF
DNI
C10 2.2pF
C27
R15
DNI
750Ω R16
DNI
3.16kΩ
10pF
C23
1pF
C22
0
R12
10pF
C5 DSAOUT
1
2345
DNI
1.3pF
C11
D6
C15
L1
C14
1VCC
C24
R32
C4
C1
C13
R1
5432
1AMP1OUT
5432
1DSAIN
C17
R2 1VDD
2
31
S1
24
1
16
32
13
12
11
9
8
7
5
323
22
20
18
17
14
2
PAD
21
4
25
26
27
28
29
30
31
15
19
6
10
U1
R33
R10
C28
C3
5432
1
AMP1IN C21
5 4 3 2
1
AMP2OUT
C25 C20
R11
1VCC2
C26
C8
5432
1AMP2IN
C6
VDD
10pF 10000pF
1.1pF
DNI
10µF
RED DNI
0Ω
1.8pF
DNI
0Ω
0Ω
10pF
DNI
10pF
VDD
VDD
CLK_D0
LE_D2
DATA_D1
D5
D4
D3
DNI
0Ω
10µF
RED
10pF
0.01µF
10pF
10pF
10pF
DNI
DNI
0Ω
10pF
33nH
ADL5243ACPZ
0.1µF
0
DNI RED
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
EPAD
SEL
D0/CLK
D1/DATA
D2/LE
D3
D4
D5
D6
VDD
NC
NC
DSAOUT
NC
AMP2IN
NC
NC
VBIAS
AMP2OUT/VCC2
NC
NC
NC
NC
AMP1IN
NC
NC
NC
AMP1OUT/VCC
NC
DSAIN
NC
NC
VDD
AGND
AGND
R20
0Ω
Figure 75. ADL5243 Evaluation Board
Data Sheet ADL5243
Rev. B | Page 35 of 40
DECOUP LI NG FOR U1
PLACEHOLDER
R29 C19
R28 C18
R27 C16
C12
R26
R25
R23
R20
R19
R46
A C
CR2
R8 R55
R24
R54
R53
C53 R13 C55 R14 C56
9
8
7
6
5
4
3
2
10
1P3
4
5
44
55
43
32
27
17
11
16
15
42
14
2
1
52
51
50
49
48
47
46
45
25
24
23
22
21
20
19
18
PAD
40
39
38
37
36
35
34
33
13
56
53
41
28
26
12
8
9
31
30
29
54
7
3
10
6
U4
C35 C36 C38 C39 C45 C46 C48
R45
A C
D1
R4 C37 6
PAD
2
1
8
7
5
3
U3
R3
C44 R9 C47
7
8
56
4
3
2
1U2 R5
C49 C34
R47 R7
C31
C50
5
4
3
2
1
G4
G3
G2
G1
P1
C51
31
42
Y1
C52
C33
C9
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
330pF
DNI
DNI
1.00kΩ
0Ω
JEDEC_TYPE=QFN56_8X8_PAD5_2X4_5
DNI
DNIDNI
330pF
DNI
330pF
DNI
330pF
DNI
330pF
1.00kΩ
SML-210MTT86 330pF
330pF
100kΩ
DNI
100kΩ
CY7C68013A-56LTXC
PA5
PA6
PA4
PB0
PA1
PA3
PA2
LE_D2
DATA_D1
CLK_D0
PA7
PB3
CTL2_FLAGC
24LC64-I-SN
LE_D2
CLK_D0
TSW-105-08-G-D
897-43-005-00-100001
DATA_D1
CTL1_FLAGB
CTL0_FLAGA
DM 5V_USB
PD5
D4
D3
D6
D6
D5
D5
D4
D3
DNI
1.00kΩ
DNI
1.00kΩ
DNI
1.00kΩ
0Ω
DNI
PA0
0Ω
0Ω
0Ω
0Ω
0Ω
DP
2kΩ
PD1
PD2
CLKOUT
RESETN
PD7
PD4
PD6
PD3
PD0
PB7
PB5
PB6
PB2
PB4
PB1
IFCLK
2kΩ
ADP3334ACPZ
3V3_USB
XTALIN
22pF
1.00kΩ
DNI 1.00kΩ
DNI
0.1µF
10pF
0.1µF
2kΩ
DNI
0.1µF0.1µF0.1µF0.1µF0.1µF 0.1µF
SML-210MTT86
2kΩ
78.7kΩ
1000pF 140kΩ
FB
E013815
10pF
0.1µF 22pF
XTALOUT
0.1µF
SDA
WAKEUP
SCL
1µF
1µF
24.000000MHZ
3V3_USB
0Ω
5V_USB
0.1µF
OUT
PINS
GND
DGND
DGND
CASE
DGND
AGND DGND
PAD
CLKOUT
PD7_FD15
PD6_FD14
PD5_FD13
PD4_FD12
PD3_FD11
PD2_FD10
PD1_FD9
PD0_FD8
WAKEUP
RESET_N
PA7_FLAGD_SLCS_N
PA6_PKTEND
PA5_FIFOADR1
PA4_FIFOADR0
PA3_WU2
PA2_SLOE
PA1_INT1_N
PA0_INT0_N
VCC
CTL2_FLAGC
CTL1_FLAGB
CTL0_FLAGA
GND
PB7_FD7
PB6_FD6
PB5_FD5
PB4_FD4
PB3_FD3
PB2_FD2
PB1_FD1
PB0_FD0
SDA
SCL
RESERVED
IFCLK
DMINUS
DPLUS
AGND
XTALIN
XTALOUT
AVCC
RDY1_SLWR
RDY0_SLRD
DGND
DGND
IN
IO
IN1
IN2 OUT2
OUT1
PAD FB
GND
SD_N
DGND
GND
SCL SDA
WC_N
A2
A1
A0 VCC
IN
IN
IN
DGND
DGND
DGND
DGND
DGND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
(FROM M AIN BOARD; 200mA M INI M UM )
1DGND1
1
5V_SDP
R21
R22
R17
R42
R6
R18 R43
R44 7
4
8
5
6
3
2
1U5
112
113
114
61
115
62
63
64
65
66
67
68
69
70
71
116
72
73
74
75
76
77
78
79
80
81
117
82
83
84
85
86
87
88
89
90
91
118
92
93
94
95
96
97
98
99
100
101
119
102
103
104
105
106
107
108
109
110
111
120 P2
9
8
7
60
6
59
58
57
56
55
54
53
52
51
50
5
49
48
47
46
45
44
43
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1P2
DGND DGND
LE_D2
CLK_D0
TBD0603
DNI
100kΩ
100kΩ
DNI
24LC32A-I/MS
JEDEC_TYPE=MSOP8
E014160
0Ω DNI
FX8-120S-SV(21)
DNI
0Ω
DATA_D1
0Ω
0Ω
0Ω
DNI D5
D4
D3
RED
5V_SDP
FX8-120S-SV(21)
D6
BLK
DGND
DGND
VSS
VCC
WP
A2
A1
A0
SCL SDA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
09431-176
Figure 76. USB/SDP Interface Circuitry on the Customer Evaluation Board
ADL5243 Data Sheet
Rev. B | Page 36 of 40
09431-070
Figure 77. Evaluation Board Layout—Top
09431-071
Figure 78. Evaluation Board Layout—Bottom
Data Sheet ADL5243
Rev. B | Page 37 of 40
09431-179
Figure 79. Evaluation Board Control Software
ADL5243 Data Sheet
Rev. B | Page 38 of 40
OUTLINE DIMENSIONS
3.45
3.30 S Q
3.15
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATIO N AND
FUNCTION DESCRIPT IO NS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDE C S TANDARDS MO-220-V HHD- 2
1
32
8
9
25
24
1716
COPLANARITY
0.08
3.50 REF
0.50
BSC
PI N 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18 0.20 REF
12° M AX 0.80 M AX
0.65 TYP
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
0.50
0.40
0.30
5.00
BSC SQ
4.75
BSC SQ
0.60 M AX
0.60 M AX
0.25 M IN
05-23-2012-A
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
Figure 80. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADL5243ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package LFCSP_VQ CP-32-3
ADL5243-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADL5243
Rev. B | Page 39 of 40
NOTES
ADL5243 Data Sheet
Rev. B | Page 40 of 40
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09431-0-8/12(B)
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Authorized Distributor
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ADL5243ACPZ-R7 ADL5243-EVALZ