FA3686V Dimensions, mm TSSOP-16 9 8 1 * Wide range of supply voltage: VCC=2.5 to 20V * MOSFET direct driving * Low operating current consumption by CMOS process: 3.0mA (typ.) * 2ch PWM control IC * High frequency operation: 300kHz to 1.5MHz * Simple setting of operation frequency by timing resistor * Built-in error amplifier for series regulator * Soft start function on each channel (1ch, 2ch only) * Maximum output duty cycle: 85% (typ.), at 500kHz * Built-in under voltage lockout * High accuracy reference voltage: VREF: 1.00V1%, VREG: 2.20V1% * Timer latch for short-circuit protection with counter * PGS pin for a power supply fault signal * Thin and small package: TSSOP-16 0.220.02 0~8 5 0.50.08 1.1max Features 0.105 to 0.145 4.4 6.40.2 16 0.100.05 Description FA3686V is a PWM type DC-to-DC converter control IC with 2ch outputs that can directly drive power MOSFETs. CMOS devices with high breakdown voltage are used in this IC and low power consumption is achieved. This IC is suitable for very small DC-to-DC converters because of their small and thin package (1.1mm max.), and high frequency operation (to 1.5MHz). This IC contains built-in an error amplifier for series regulators, therefore, this IC is suitable for the 3ch power supply with a 2ch DC-to-DC converter and a 1ch series regulator. CMOS IC For Switching Power Supply Control FA3686V 0.65 Block diagram Pin No. Pin symbol Description 1 FB3 Ch.3 output of error amplifier 2 IN3- Ch.3 inverting input to error amplifier 3 FB2 Ch.2 output of error amplifier 4 IN2- Ch.2 inverting input to error amplifier 5 PGS PGS signal output 6 VCC Power supply 7 CS2 Soft start for Ch.2 8 OUT2 Ch.2 output 9 OUT1 Ch.1 output 10 CS1 Soft start for Ch.1 11 GND Ground 12 RT Oscillator timing resistor 13 VREG Regulated voltage output 14 IN1- Ch.1 inverting input to error amplifier 15 FB1 Ch.1 output of error amplifier 16 TL Timer latched short circuit protection 1 FA3686V Absolute maximum ratings Item Power supply voltage PGS pin voltage FB1, IN1-, FB2, IN2-, FB3, IN3- pin voltage CS1, CS2, RT, TL, VREG pin voltage OUT1/2 OUT pin source current OUT pin sink current OUT1/2 OUT pin source current OUT pin sink current Power dissipation * Operating junction temperature Operating ambient temperature Storage temperature Symbol VCC VPGS VEA_IN VCTR_IN IOUT- IOUT+ IOUT- IOUT+ Pd TJ TOPR TSTG Rating 20 20 -0.3 to 5.0 -0.3 to 5.0 -400 (peak) 150 (peak) -50 (continuous) 50 (continuous) 300 (Ta25C) +125 -30 to +85 -40 to +125 Unit V V V V mA mA mA mA mW C C C * Derating factor Ta25C: 3mW/C Maximun power dissipation [mW] Maximum power dissipation curve 350 300 250 200 150 100 50 0 -30 0 30 60 90 120 150 Ambient temperature [C] Recommended operating conditions Item Symbol Max. Unit Supply voltage VCC 2.5 18 V CS1, CS2, TL pin voltage VCTR_IN 0.0 2.5 V IN1-, IN2-, IN3- pin voltage VEA_IN 0.0 2.5 V Oscillation frequency fOSC 300 1500 kHz VREG pin capacitance CREG VREG pin current IREG VCC pin capacitance CVCC CS1 pin capacitance CCS1 CS2 pin capacitance CCS2 Test condition Min. Typ. 500 Vcc<10V 0.1 1.0 4.7 F 10VVcc<18V 0.47 1.0 4.7 F 1.0 mA 1.0 F Between CS1 and GND 0.01 F Between CS2 and VREG 0.01 F Electrical characteristics (VCC=3.3V, CREG=1.0F, RT=12k, Ta=+25C) Regulated voltage for internal control blocks (VREG pin) Item Symbol Regulated voltage VREG Line regulation VREG_LINE VCC=2.5 to 18V Load regulation VREG_LOAD IREG=0 to 1mA Variation with temperature VREG_TC Ta=-30 to +85C 2 Test condition Min. Typ. Max. Unit 2.178 2.200 2.222 V 5 15 mV -5 -1 mV 0.5 % FA3686V Oscillator section (RT pin) Item Symbol Test condition Min. Oscillation frequency fOSC 500 565 kHz Line regulation fOSC_LINE VCC=2.5 to 18V 1 5 % Variation with temperature fOSC_TC1 Ta=-30 to +85C 3 435 Typ. Max. Unit % Error amplifier section (IN1-, FB1, IN2-, FB2, IN3-, FB3 pin) Item Symbol Test condition Min. Typ. Max. Unit Reference voltage (CH.1) VREF1 *1 0.99 1.00 1.01 V Reference voltage (CH.2) VREF2 *2 0.98 1.00 1.02 V Reference voltage (CH.3) VREF3 *3 0.98 1.00 1.02 V VREF Line regulation VREF_LINE VCC=2.5 to 18V 2 5 mV VREF Variation with temperature VREF_TC1 Ta=-30 to +85C 0.5 % Input bias current IIN- VINx-=0.0 to 2.5V *4 0.0 mA Open loop gain AVO 70 dB Unity gain bandwidth fT 1.5 Output current (sink) ISIFB VFBx=0.5V, VINx-=VREG *4 2.3 3.5 4.7 mA Output current (source) ISOFB VFBx=VREG-0.5V, VINx-=0V *4 -360 -270 -180 A *1 *2 *3 *4 MHz The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included. The FB2 voltage is measured under the condition that IN2- pin and FB2 pin are shorted. The input offset voltage of the error amplifier is included. The FB3 voltage is measured under the condition that IN3- pin and FB3 pin are shorted. The input offset voltage of the error amplifier is included. The "x" of INx- and FBx refers to 1 to 3. Soft start section (CS1, CS2 pin) Item Symbol Test condition Threshold voltage (CS1) VCS1D0 Duty cycle=0%, VFB1=1.4V VCS1D20 Duty cycle=20%, VFB1=1.4V 0.89 1.25 Threshold voltage (CS2) Min. Typ. Max. 0.82 Unit V 0.925 0.96 1.285 1.32 VCS1D80 Duty cycle=80%, VFB1=1.4V VCS2D0 Duty cycle=0%, VFB2=0.7V VCS2D20 Duty cycle=20%, VFB2=0.7V 1.20 1.235 1.27 1.33 V V V V VCS2D80 Duty cycle=80%, VFB2=0.7V 0.84 0.875 0.91 V Charge current of CS2 (source) ICS1 VCS1=0.5V -2. -2.0 -1.5 A Charge current of CS2 (sink) ICS2 VCS2=VREG-0.5V 1.5 2.0 2.4 A Typ. Max. Pulse width modulation (PWM) section (FB1, FB2 pin) Item Symbol Test condition Max. duty cycle of OUT1 DMAX1 fOSC=300kHz RT=12k (fOSC500kHz) Min. 87 80 fOSC=1.5MHz Max. duty cycle of OUT2 DMAX2 OSC500kHz) fOSC=1.5MHz Threshold voltage of FB1 Threshold voltage of FB2 90 78 fOSC=300kHz RT=12k (f 85 85 73 % % 88 80 Unit % % 90 % % VFB1D0 Duty cycle=0% 0.82 V VFB1D20 Duty cycle=20% 0.925 V V VFB1D80 Duty cycle=80% 1.285 VFB2D0 Duty cycle=0% 1.33 V VFB2D20 Duty cycle=20% 1.235 V VFB2D80 Duty cycle=80% 0.875 V 3 FA3686V Timer latch protection section (TL pin) Item Symbol Test condition Min. Threshold voltage of FB1 VTHFB1TL *1 Threshold voltage of FB2 VTHFB2TL *2 Threshold voltage of FB3 VTHFB3TL Threshold voltage of CS1 Threshold voltage of CS2 Typ. Max. Unit 1.5 2.0 V 0.2 0.6 V *1 1.5 2.0 V VVTHCS1TL *3 0.2 0.6 V VVTHCS2TL *4 1.5 2.0 V TL pin voltage for counting 16th stage VTL16 0 0.2 V TL pin voltage counting 17th stage VTL17 VREG-0.2 VREG V *1 *2 *3 *4 The latched mode operates when the voltage of FB1 or FB3 exceeds the threshold voltage as shown in the table. The latched mode operates when the FB2 voltage falls below the threshold voltage as shown in the table. The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table. The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table. Under voltage lockout circuit section (VCC pin) Item Symbol ON threshold voltage of VCC VUVLO Hysteresis voltage VUVLO Test condition Min. Typ. Max. Unit 2.0 2.2 2.35 V 0.1 V PGS section (VCC, PGS pin) Item Symbol Test condition Min. Typ. Max. Unit Threshold voltage of VCC VPGS VCC decreasing 2.15 2.25 2.35 V Hysteresis voltage VPGS VCC increasing 0.10 V VPGS variation with temperature VPGS_TC1 Ta=-30 to +85C 1 % On resistance RPGS VCC=2.2V, IPGS=10mA 50 100 Output section (OUT1, OUT2 pin) Item Symbol Test condition Typ. Max. Unit High side on resistance of OUT1/2 RONHI IOUTx=-50mA * 10 20 IOUTx=-50mA, VCC=5V * 9 IOUTx=-50mA, VCC=15V * 8 Low side on resistance of OUT1/2 RONLO Min. 10 IOUTx=50mA * 5 IOUTx=50mA, VCC=5V * 5 IOUTx=50mA, VCC=15V * 5 Rise time of OUT1/2 tRISE CL=1000pF 25 ns Fall time of OUT1/2 tFALL CL=1000pF 40 ns Item Symbol Test condition Typ. Max. Unit Supply current ICCA Ch.1, Ch.2 operating mode 3.0 4.0 mA ICCA1 Ch.1, Ch.2 off mode 2.5 mA ICCA2 Ch.1, Ch.2 operating mode, VCC=18V 3.5 mA ICCA3 Latch mode 2.5 mA * The "x" of OUTx refers to 1, 2. Overall section 4 Min. FA3686V Characteristic curves Oscillation frequency vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 1800 510 1600 508 Oscillation frequency [kHz] Oscillation frequency [kHz] Oscillation frequency vs. timing resistor VCC=3.3V, Ta=25C 1400 1200 1000 800 600 400 506 504 502 500 498 496 494 492 200 490 0 1 10 0 5 10 100 15 20 Vcc [V] Timing resistor RT [k] Oscillation frequency vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Regulated voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 2.23 550 Regulated voltage VREG [V] Oscillation frequency [kHz] 570 530 510 490 470 450 Load current IREG=0A 2.22 2.21 2.20 2.19 2.18 430 -50 -25 0 25 50 75 100 125 150 2.17 0 Ambient temperature Ta [C] 5 10 15 20 Vcc [V] Regulated voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Regulated voltage vs. load current VCC=3.3V, RT=12k (fOSC=500kHz) 2.23 Regulated voltage VREG [V] Regulated voltage VREG [V] 2.23 2.22 2.21 2.20 2.19 2.18 2.17 2.22 Ta=85C 2.21 2.20 Ta=25C 2.19 Ta=-30C 2.18 2.17 -50 -25 0 25 50 75 100 Ambient temperature Ta [C] 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Load current IREG [mA] 5 FA3686V Reference voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) 1.020 1.020 1.015 1.015 Reference voltage VREF [V] Reference voltage VREF [V] Reference voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 1.010 1.005 1.000 0.995 0.990 1.010 1.005 1.000 0.995 0.990 0.985 0.985 0.980 0 5 10 15 20 0.980 25 -50 Vcc [V] 50 75 100 125 150 -150 Output current (source) ISOFB [uA] 4.5 4.0 3.5 3.0 2.5 2.0 -50 -25 0 25 50 75 100 125 -200 -250 -300 -350 -50 150 -25 Ambient temperature Ta [C] -1.5 -2.0 -2.5 -25 0 25 50 75 100 Ambient temperature Ta [C] 25 50 75 100 125 150 Charge current of CS2 (sink) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Charge current of CS2 (sink) ICS2 [uA] -1.0 -3.0 -50 0 Ambient temperature Ta [C] Charge current of CS1 (source) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Charge current of CS1 (source) ICS1 [uA] 25 Error amp. output current (source) vs. ambient temperarure VCC=3.3V, RT=12k (fOSC=500kHz) 5.0 6 0 Ambient temperature Ta [C] Error amp. output current (sink) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Output current (sink) ISIFB [mA] -25 125 150 3.0 2.5 2.0 1.5 1.0 -50 -25 0 25 50 75 100 Ambient temperature Ta [C] 125 150 FA3686V Output duty cycle vs. CS voltage (ch. 1) VCC=3.3V, Ta=25C 100 Output duty cycle vs. oscillation frequency (ch. 1) VCC=3.3V, Ta=25C 100 fosc=300kHz fosc=500kHz 90 90 VCS1=1.30V 80 VCS1=1.25V 70 VCS1=1.20V 80 70 fosc=1.5MHz 60 50 40 30 Output duty cycle (ch.1) [%] Output duty cycle (ch.1) [%] fosc=760kHz VCS1=1.15V 60 VCS1=1.10V 50 VCS1=1.05V 40 VCS1=1.00V 30 VCS1=0.95V 20 20 10 10 VCS1=0.90V VCS1=0.85V 0 0 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 300 500 VCS1 [V] Output duty cycle vs. CS voltage (ch. 2) VCC=3.3V, Ta=25C 100 900 1100 1300 1500 Output duty cycle vs. oscillation frequency (ch. 2) VCC=3.3V, Ta=25C 100 fosc=300kHz 90 90 fosc=500kHz 80 VCS2=0.85V 80 VCS2=0.90V 70 VCS2=0.95V 60 VCS2=1.00V 70 60 fosc=760kHz Duty 2 [%] Output duty cycle (ch.2) [%] 700 Oscillation frequency [kHz] 50 40 fosc=1.5MHz 30 VCS2=1.05V 50 VCS2=1.10V 40 VCS2=1.15V 20 30 VCS2=1.20V 10 20 VCS2=1.25V 10 VCS2=1.30V 0 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 0 VCS2 [V] 300 500 700 900 1100 1300 1500 Oscillation frequency [kHz] Maximum duty cycle vs. oscillation frequency (ch. 2) VCC=3.3V, Ta=25C 95 95 90 90 85 85 DMAX2 [%] DMAX1 [%] Maximum duty cycle vs. oscillation frequency (ch. 1) VCC=3.3V, Ta=25C 80 80 75 75 70 70 65 300 500 700 900 1100 Oscillation frequency [kHz] 1300 1500 65 300 500 700 900 1100 1300 1500 Oscillation frequency [kHz] 7 FA3686V Maximum duty cycle vs. ambient temperature (ch. 2) VCC=3.3V, RT=12k (fOSC=500kHz) 90 90 89 89 88 88 87 87 DMAX2 [%] DMAX1 [%] Maximum duty cycle vs. ambient temperature (ch. 1) VCC=3.3V, RT=12k (fOSC=500kHz) 86 85 84 86 85 84 83 83 82 82 81 81 80 80 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Ambient temperature Ta [C] OUT1 terminal source current vs. H level output voltage Ta=25C 0 75 100 125 150 0 -50 -100 -100 Vcc=2.5V -150 Vcc=2.5V -200 IOUT2 [mA] -150 Vcc= 3V -250 -300 Vcc= 5V -350 -200 Vcc= 3V -250 -300 Vcc= 5V -350 -400 -400 Vcc=12V -450 Vcc=12V -450 -500 -500 0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 Vcc-VOUT1 [V] 3.0 4.0 5.0 Vcc-VOUT2 [V] OUT1 terminal source current vs. H level output voltage VCC=3.3V OUT2 terminal source current vs. H level output voltage VCC=3.3V 0 0 -50 -50 -100 -100 IOUT2 [mA] IOUT1 [mA] 50 OUT2 terminal source current vs. H level output voltage Ta=25C -50 IOUT1 [mA] 25 Ambient temperature Ta[C] Ta=85C -150 Ta=25C Ta=-30C -200 Ta=85C -150 -200 Ta=25C Ta=-30C -250 -250 -300 -300 0.0 0.5 1.0 1.5 2.0 Vcc-VOUT1 [V] 8 2.5 3.0 0.0 0.5 1.0 1.5 2.0 Vcc-VOUT2 [V] 2.5 3.0 FA3686V OUT1 terminal source current vs. H level output voltage VCC=12V OUT2 terminal source current vs. H level output voltage VCC=12V 0 0 -100 IOUT2 [mA] IOUT1 [mA] -100 -200 -300 Ta=85C -200 -300 Ta=85C Ta=-30C -400 Ta=-30C -400 Ta=25C -500 0.0 1.0 2.0 3.0 4.0 Ta=25C -500 5.0 0.0 1.0 2.0 Vcc-VOUT1 [V] OUT1 terminal sink current vs. L level voltage 5.0 200 Ta=25C Ta=-30C Ta=-30C Ta=25C 150 150 IOUT2 [mA] IOUT1 [mA] 4.0 OUT2 terminal sink current vs. L level voltage 200 Ta=85C 100 Ta=85C 100 50 50 0 0.0 0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 1.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VOUT2 [V] VOUT1 [V] OUT1 terminal rise time vs. supply voltage VCC CL=1000pF OUT2 terminal rise time vs. supply voltage VCC CL=1000pF 60 60 OUT2 terminal rise time t RISE [ns] OUT1 terminal rise time t RISE [ns] 3.0 Vcc-VOUT2 [V] 50 Ta=85C 40 Ta=25C 30 Ta=-30C 20 10 50 Ta=25C 30 20 0 5 10 Vcc [V] 15 20 Ta=-30C 10 0 0 Ta=85C 40 0 5 10 15 20 Vcc [V] 9 FA3686V OUT1 terminal fall time vs. supply voltage VCC CL=1000pF OUT2 terminal fall time vs. supply voltage VCC CL=1000pF 200 OUT2 terminal fall time t FALL [ns] OUT1 terminal fall time t FALL [ns] 200 Ta=85C 150 Ta=25C 100 Ta=-30C 50 Ta=85C 150 Ta=25C 100 Ta=-30C 50 0 0 0 5 10 15 0 20 5 10 6.0 Vcc=18V Vcc=12V 5.0 Vcc=5V 4.0 Vcc=3.3V Vcc=2.5V 500 700 900 1100 1300 Operating mode supply current vs. ambient temperature Operating mode supply current ICCA [mA] Operating mode supply current ICCA [mA] Operating mode supply current vs. oscillation frequency Ta=25C 2.0 300 4.5 Vcc=12V 4.0 3.5 Vcc=3.3V Vcc=2.5V 2.5 2.0 -50 -25 25 50 75 100 125 150 Ambient temperature Ta [C] PGS terminal on resistance vs. ambient temperature 2.5 80 2.4 70 Vcc= 5V 60 2.3 RPGS [] UVLO ON threshold VUVLO [V] 0 1500 UVLO ON threshold vs. ambient temperature 2.2 2.1 2.0 Vcc=3.3V 50 Vcc=2.5V 40 30 20 1.9 10 -25 0 25 50 75 100 Ambient temperature Ta [C] 10 Vcc=5V 3.0 Oscillation frequency [kHz] 1.8 -50 20 Vcc [V] Vcc [V] 3.0 15 125 150 0 -50 -25 0 25 50 75 100 Ambient temperature Ta [C] 125 150 FA3686V PGS terminal current vs. voltage Ta=25C PGS terminal threshold voltage of VCC vs. ambient temperature 2.35 45 Vcc=7.0V 40 Vcc=5V Vcc=3.3V IPGS [mA] 30 25 20 Vcc=2.2V 2.30 VPGS [V] 35 15 2.20 10 vcc=1.8V 5 2.15 -50 vcc=1.5V 0 0.0 2.25 0.5 1.0 1.5 2.0 2.5 -25 0 25 50 75 100 125 150 Ambient temperature Ta [C] VPGS [V] CS1 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz) CS2 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz) 400 0 Ta=-30C 350 -50 Ta=25C ICS2 off [uA] ICS1 off [uA] 300 250 Ta=85C 200 150 100 -100 Ta=85C -150 0 0.00 Ta=25C Ta=-30C 50 0.50 1.00 1.50 2.00 VCS1 [V] 2.50 -200 0.00 0.50 1.00 1.50 2.00 VREG-VCS2 [V] Error amplifier gain and phase vs. frequency 11 FA3686V Description of each circuit OSC 1. Reference voltage circuit (VREF) This circuit generates the reference voltage of 1.00V (ch1: 1%; ch2, 3: 2%) compensated in temperature from VCC voltage, and is connected to the non-inverting input of the error amplifier. This voltage cannot be observed directly because an external pin for this purpose is not provided. 2. Regulated voltage circuit (VREG) This circuit generates 2.20V1% based on the reference voltage VREF, and is used as the power supply of the internal IC circuits. This voltage is generated when the supply voltage, VCC, is input. The VREG voltage also is used as a regulated power supply for soft start and others. The output current for external circuit should be within 1mA. A capacitor connected between VREG pin and GND pin is necessary to stable the VREF voltage (To determine capacitance, refer to recommended operating conditions). The VREG voltage is regulated in VCC voltage of 2.4V or above. 3. Oscillator The oscillator generates a triangular waveform by charging and discharging the built-in capacitor. A desired oscillation frequency can be set by the value of the resistor connected to the RT pin (Fig. 1). The built-in capacitor voltage oscillates between approximately 0.82V and 1.38V at fosc=500kHz (that of ch1 and ch2 are slightly different) with almost the same charging and discharging gradients (Fig. 2). You can set the desired oscillation frequency by changing the gradients using the resistor connected to the RT pin. (Large RT: low frequency, small RT: high frequency) The oscillator waveform cannot be observed from the outside because a pin for this purpose is not provided. The RT pin voltage is approximately 1V DC in normal operation. The oscillator output is connected to the PWM comparator. 4. Error amplifier circuit The error amplifiers 1, 2, 3 have inverting input pins of IN1- pin (Pin 14), IN2- pin (Pin 4) and IN3- pin (Pin 2). The non-inverting input is internally connected to the reference voltage VREF of the error amplifier 1 (1.00V1%; 25C) and the error amplifiers 2, 3 (1.00V2%; 25C). The FB pins (Pin1, Pin15) are the output of the error amplifiers. An external RC network is connected between FB pin and IN- pin for gain and phase compensation setting. The error amplifier 3 can be used for a series regulator. 12 RT RT Fig. 1 RT value: small RT value: large 1.38V 0.82V Fig. 2 Vout1 RNF1 R1 Er.Amp.1 FB1 14 IN1- R2 15 + VREG 13 R3 VREF (1.0V) Er.Amp.2 IN2Vout3 FB2 4 3 R4 Vout2 R5 Er.Amp.3 IN3- FB3 2 1 R6 RNF3 RNF2 Fig. 3 12 Comp FA3686V 5. PWM comparator The PWM output generates from the oscillator output, the error amplifier output (FB1, FB2) and CS voltage (CS1, CS2) (Fig. 4). The oscillator output is compared with the preferred lower voltage between FB1 and CS1 for ch1. While the preferred voltage is lower than oscillator output, the PWM output is low. While the preferred voltage is higher than oscillator output, the PWM output is high. Since the phase of Ch2 is the opposite phase of Ch1, higher voltage between FB2 and CS2 is preferred and while the preferred voltage is lower than the oscillator output, the PWM output 2 is high. (Cannot be observed externally) The output polarity of OUT1, OUT2 changes according to the condition of SEL pin. (See Fig. 6) The maximum duty cycle (DMAX1, DMAX2) is internally set approximately 85%. Note that the maximum duty cycle depends on operation frequencies. (See the characteristics curve: Output duty cycle vs. oscillation frequency) 6. Soft start function This IC has a soft start function to protect DC-to-DC converter circuits from damage when starting operation. CS1 pin (Pin10) and CS2 pin (Pin7) are used for soft start function of ch1 and ch2 respectively. (Fig. 5) When the supply voltage is applied to the VCC pin and UVLO is cancelled, the capacitor CCS1 and CCS2 is charged by the internal constant current sources (2A, typ.). Then, the CS1 voltage gradually increases, and the CS2 voltage gradually decreases. Since the CS1, and CS2 are connected to the PWM comparator, the pulses gradually widen and then the soft start function operates. (Fig. 6) PWM Comp.1 FB1 PWM output1 OUT1 Nch. drive 9 CS1 Oscillator output DMAX1 UVLO DMAX2 CS2 PWM output2 OUT2 Pch. drive FB2 8 PWM Comp.2 Fig. 4 VREG VREG 13 13 CCS2 7 10 CS2 CS1 CCS1 Fig. 5 Er. amp.1 output CS1 pin voltage Oscillator output PWM output 1 OUT1 Nch.drive CS2 pin voltage Oscillator output Er. amp.2 output PWM output2 OUT2 Pch. drive Fig. 6 13 FA3686V 7. Timer latch short-circuit protection circuit This IC has the timer latch short-circuit protection circuit. The circuit cuts off the output of all channels when the output voltage of DC-to-DC converter drops due to short circuit or overload. Delay time of the timer latch mode is set by a counter system in the internal circuit, therefore, no external parts are necessary. When one of the output voltage of the DC-to-DC converter drops due to a short circuit or overload, the FB1 and FB3 pin voltage increases up to around the VREG voltage for ch1 and ch3, or the FB2 pin voltage drops down to around 0V for ch2. The counter system operates when the FB1 or FB3 pin voltage exceeds the timer latch threshold voltage of 2.0V(max.) or FB2 pin voltage falls below timer latch threshold voltage of 0.2V(min.). The counter system counts oscillator waveform. If this system counts the oscillation cycles of 216 times (TL pin: GND, 16th stage counter) or 217 times (TL pin: VREG, 17th stage counter), this circuit detects short circuit. Then the IC is set to off latch mode and the output of all channels is shut off and the current consumption becomes 2.5mA (typ.). (Fig. 7) If the DC-to-DC converters return to normal before counter system counts 216 or 217, counter is reset. The period (tp) between the occurrences of short-circuit in the converter output and setting to off latch mode can be calculated by the following equations: tp [s] = 216 1 fosc Ch1 Momentary short circuit Short circuit FB1 or 3 Oscillator output tp Timer latch count Short circuit protection Timer latch count Time t Off latch mode OUT1 Time t Ch2 Timer latch Timer latch count count 1 fosc Oscillation output TL pin: VREG Example. When fosc=500kHz and TL pin to GND, the period tp is: tp=216 1/500kHz=0.131sec. You can reset off latched mode of the short-circuit protection by either of the following ways to 1) CS pins, or 2) VCC pin: 1) Set the CS pin of the cause of off latch mode as follows. CS1 pin voltage = 0V, CS2 pin voltage = VREG 2) VCC voltage is below UVLO off threshold voltage (2.1V typ.). Connect the TL pin to either VREG or GND. If TL pin is opened, the counter operation is unstable. 8. Output circuit The IC contains a push-pull output stage and can directly drive MOSFETs. The maximum peak current of the output stage is sink current of +150mA, and source current of -400mA. The IC can also drive NPN and PNP transistors. The maximum current in such cases is 50mA. You must design the output current considering the rating of power dissipation. (See "Design advice".) 9. Undervoltage lockout circuit The IC contains an undervoltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. When the supply voltage rises from 0V, the IC starts to operate at VCC of 2.2V (typ.) and outputs generate pulses. If a drop of the supply voltage occurs, it stops output at VCC of 2.1V (typ.). When it occurs, the CS1 pin is turned to low level and the CS2 pin to high level, and then these pins are reset. 14 tp TL pin: GND Short circuit FB2 tp [s] = 217 Short circuit protection Momentary short circuit Time t OUT2 Off latch mode Time t Fig. 7 FA3686V PGS 5 + UVLO V VPGS Timer latch 11 Vcc voltage stable state Hysteresis voltage Vcc VPGS voltage 2.25V Off latch mode reset VCC increasing VCC decreasing Off latch mode 1V PGS pin voltage 10. PGS circuit The PGS pin is an open drain output of Nch MOSFET for transmitting fault signals of the power supply. The PGS circuit is enabled when Vcc voltage is over the operating threshold voltage (approximately 1V). The Nch MOSFET turns ON and the PGS pin is connected to GND if any of the following three conditions occurs: 1) the VCC voltage is below the threshold voltage (VCC increasing: 2.35V typ.; VCC decreasing: 2.25V typ.), 2) UVLO turns on (VCC=2.1V or below), 3) IC is off latch mode. The operation sequence is shown in Fig. 8. As shown in Fig. 8, in the case of increasing the Vcc voltage with the voltage V applied to the PGS pin, when the Vcc voltage reaches 1V, PGS circuit is enabled and detects that the Vcc voltage is not enough high. Then PGS circuit turns the Nch MOSFET on and output fault signal. The fault signal is cancelled when the VCC voltage exceeds 2.35V (typ.). In the case that the VCC voltage exceeds 2.53V (typ.) and the IC is off latch mode, the PSG circuit detects it as abnormal and the Nch MOSFET is turned on. In the case of decreasing the VCC voltage, the circuit sends out fault signals when the VCC voltage is below 2.25V (typ.) and continues to output until the VCC voltage reaches below the PGS circuit operation threshold voltage of approximately 1V. (Under the VCC voltage of 1V, the circuit does not operate normally.) V PGS operation PGS operation PGS operation Fig. 8 15 FA3686V Design advice VCC pin voltage 1. Setting the oscillation frequency As described in item 1, "Description of each circuit," a desired oscillation frequency can be determined by the value of the resistor connected to the RT pin. When designing an oscillation frequency, you can set any frequency between 300kHz and 1.5MHz. You can obtain the oscillation frequency from the characteristic curve "Oscillation frequency (fosc) vs. timing resistor resistance (RT)" or the value can be approximately calculated by the following expression. CS1 pin voltage Threshold voltage VCS1n fOSC = 4050 RT -0.86 RT = ( ) 4050 fOSC 1.16 fOSC: Oscillation frequency [kHz] RT: Timing resistor [k] t0 t Fig. 9 This expression, however, can be used for rough calculation, the obtain value is not guaranteed. The operation frequency varies due to the conditions such as tolerance of the characteristics of the ICs, influence of noises, or external discrete components. When determining the values, examine the effectiveness of the values in an actual circuit. The timing resistor RT should be wired to the GND pin as shortly as possible because the RT pin is a high impedance pin and is easy affected by noises. 2. Determining soft start period The period from the start of charging the capacitor CCS to widening n% of output duty cycle can be roughly calculated by the following expression: (see Fig. 5 for symbols) t [s] = VCS2n CCS1 ICS1 t [s] = (VREG - VCS2n) CCS1 ICS2 For CS1 pin For CS2 pin CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [F] ICS1, ICS2: CS charge current [A] (2A typ.) VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in n% of output duty cycle, and vary in accordance with operating frequency. The value can be obtained from the characteristic curve "Output duty cycle vs. CS voltage" The charging of the CCS1 and CCS2 starts after the UVLO is unlocked. Therefore, the period from power-on of VCC to widening n% of output duty cycle is the sum of t0 and t. To reset the soft start function, the supply voltage VCC is lowered below the UVLO voltage (2.1V typ.) and then the internal switch discharges the CS capacitor. The characteristics of the internal switch for discharge are shown in following the characteristics curves of "Characteristics of CS1 internal discharge switch current vs. voltage" and "Characteristics of CS2 internal discharge switch current vs. voltage". Therefore, when determining the period of soft start at restarting the power supply, consider the characteristics carefully. 16 FA3686V 3. Determining the output voltage of DC-DC converters The ways to determine the output voltage of the DC-DC converter of each channel is shown in Fig. 10 and the following equations. OUT1 Vout1 9 Vout1 R1 IN114 For ch1: The output voltage of a boost circuit is determined by: Vout1 = 15 FB1 + R2 VREF (1.0V) R1 + R2 VREF R2 8 VREG OUT2 Vout2 13 For ch2: The output voltage of an inverting circuit is determined by: R3 IN24 3 FB2 + Vout2 = R3 + R4 R4 VREF - VREG R3 R3 R4 VREF (1.0V) Vout2 Vout3 The ratio of resistances is determined by: R3 VREG - VREF = R3 Vout2 + VREF Vout3 R5 IN3- FB3 2 1 (Use the absolute value of the Vout2 voltage.) + R6 VREF (1.0V) For ch3: The output voltage of a series regulator is determined by: Vout3 = R5 + R6 VREF R6 Fig. 10 4. Restriction of external discrete components and recommended operating conditions To achieve a stable operation of the IC, the value of external discrete components connected to VCC, VREG, CS pins should be within the recommended operating conditions. And the voltage and current applied to each pin should be also within the recommended operating conditions. If the pin voltage of OUT1, OUT2, or VREG becomes higher than the VCC pin voltage, the current flows from the pins to the VCC pin because parasitic three diode exist between the VCC pin and these pins. Be careful not to allow this current to flow. 5. Loss calculation of IC Since it is difficult to measure IC loss directly, the calculation to obtain the approximate loss of the IC connected directly to a MOSFET is described below. When the supply voltage is VCC, the current consumption of the IC is ICCA, the total input gate charge of the driven MOSFET is Qg and the switching frequency is fsw, the total loss Pd of the IC can be calculated by: Pd VCC (ICCA + Qg fsw). The value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperature, or the tolerance of parameter. Therefore, evaluate the appropriateness of IC loss sufficiently considering the range of values of above parameters under all conditions. Example: ICCA=3.0mA for VCC=3.3V in the case of a typical IC from the characteristics curve. Qg=6nC, fsw=500kHz, the IC loss "Pd" is as follows. Pd 3.3 (3.0mA + 6nC 500kHz) 19.8mW If two MOSFETs are driven under the same condition for 2 channels, Pd is as follows: Pd 3.3 {3.0mA + 2 (6nC 500kHz)} = 29.7mW 17 FA3686V Application circuit 10V/5mA 0.1uF 4700pF 0.1uF 180k 10k 13k 0.1uF 4.7uF 0.1uF 5.0V/200mA 2.9 to 3.6V 4k 1000pF 15uF 10uF 470 GND 1k -5.0V/100mA 7 0.47uF 10k 3 4 5 PGS 33k 2 2200pF 4700pF 4.7k sample shown above. When designing an actual circuit for a product, you must determine parts tolerances and characteristics for safe and 18 2.2k 6 0.047uF Parts tolerances characteristics are not defined in the circuit design economical operation. 11k 470 8 10uF 1 47k FB3 IN3- FB2 IN2- PGS VCC CS2 OUT2 4700pF 16 15 10k FA3686V 9 10 11 14 1uF 13 12 12k TL 0.022uF FB1 IN1- VREG RT GND CS1 OUT1 1000pF