FA3686V
1
■ Block diagram
FA3686V
■ Dimensions, mm
TSSOP-16
■ Description
FA3686V is a PWM type DC-to-DC converter control IC with
2ch outputs that can directly drive po w er MOSFETs . CMOS
de vices with high breakdo wn voltage are used in this IC and
low po w er consumption is achieved. This IC is suitable f or very
small DC-to-DC converters because of their small and thin
package (1.1mm max.), and high frequency operation (to
1.5MHz). This IC contains built-in an error amplifier f or series
regulators, therefore, this IC is suitable for the 3ch power supply
with a 2ch DC-to-DC converter and a 1ch series regulator .
■ Features
• Wide range of supply voltage: VCC=2.5 to 20V
• MOSFET direct driving
• Low operating current consumption by CMOS process:
3.0mA (typ .)
• 2ch PWM control IC
• High frequency operation: 300kHz to 1.5MHz
• Simple setting of operation frequency by timing resistor
• Built-in error amplifier for series regulator
• Soft start function on each channel (1ch, 2ch only)
• Maximum output duty cycle: 85% (typ .), at 500kHz
• Built-in under v oltage lockout
• High accuracy reference voltage: VREF: 1.00V±1%,
VREG: 2.20V±1%
• Timer latch f or short-circuit protection with counter
• PGS pin f or a power supply fault signal
• Thin and small pac kage: TSSOP-16
CMOS IC
For Switching Power Supply Control
Pin No. Pi n symb ol Description
1 FB3 Ch.3 output of error amplifier
2 IN3- Ch.3 inverting input to error amplifier
3 FB2 Ch.2 output of error amplifier
4 IN2- Ch.2 inverting input to error amplifier
5 PGS PGS signal output
6 VCC Power supply
7 CS2 Soft star t for Ch.2
8 OUT2 Ch.2 output
9 OUT1 Ch.1 output
10 CS1 Soft star t for Ch.1
11 GND Ground
12 RT Oscillator timing resistor
13 VREG Regulated voltage output
14 IN1- Ch.1 inverting input to error amplifier
15 FB1 Ch.1 output of error amplifier
16 TL Timer latched shor t circuit protection
18
9
16
0~8˚
0.65
6.4
±0.2
0.105 to
0.145
4.4
5
0.22
±0.02
0.5
±0.08
1.1max
0.10
±0.05
FA3686V
2
■ Recommended operating conditions
Item Symbol Test condition Min. Typ. Max. Unit
Supply voltage VCC 2.5 18 V
CS1, CS2, TL pin voltage VCTR_IN 0.0 2.5 V
IN1–, IN2–, IN3– pin voltage VEA_IN 0.0 2.5 V
Oscillation frequency fOSC 300 500 1500 kHz
VREG pin capacitance CREG Vcc<10V 0.1 1.0 4.7 µF
10V⬉Vcc<18V 0.47 1.0 4.7 µF
VREG pin current IREG 1.0 mA
VCC pin capacitance CVCC 1.0 µF
CS1 pin capacitance CCS1 Between CS1 and GND 0.01 µF
CS2 pin capacitance CCS2 Between CS2 and VREG 0.01 µF
■ Electrical characteristics (VCC=3.3V, CREG=1.0µF, RT=12kΩ, Ta=+25˚C)
Regulated voltage for internal control blocks (VREG pin)
■ Absolute maximum ratings
Maximum power dissipation curve
Item Symbol Rating Unit
Power supply voltage VCC 20 V
PGS pin voltage VPGS 20 V
FB1, IN1–, FB2, IN2–, FB3, IN3– pin voltage VEA_IN –0.3 to 5.0 V
CS1, CS2, R T, TL, VREG pin voltage VCTR_IN –0.3 to 5.0 V
OUT1/2 OUT pin source current IOUT––400 (peak) mA
OUT pin sink current IOUT+ 150 (peak) mA
OUT1/2 OUT pin source current IOUT––50 (continuous) mA
OUT pin sink current IOUT+ 50 (continuous) mA
Power dissipation * Pd300 (Ta⬉25˚C) mW
Operating junction temperature TJ+125 ˚C
Operating ambient temperature TOPR –30 to +85 ˚C
Storage temperature TSTG –40 to +125 ˚C
* Derating factor Ta⭌25˚C: 3mW/˚C
Item Symbol Test condition Min. Typ. Max. Unit
Regulated voltage VREG 2.178 2.200 2.222 V
Line regulation VREG_LINE VCC=2.5 to 18V ±5 ±15 mV
Load regulation VREG_LOAD IREG=0 to 1mA –5–1mV
Variation with temperature VREG_TC Ta=–30 to +85˚C ±0.5 %
0
50
100
150
200
250
300
350
-30 0 30 60 90 120 150
Ambient temperature [˚C]
Maximun power dissipation
[mW]
FA3686V
3
Error amplifier section (IN1–, FB1, IN2–, FB2, IN3–, FB3 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Reference voltage (CH.1) VREF1 *10.99 1.00 1.01 V
Reference voltage (CH.2) VREF2 *20.98 1.00 1.02 V
Reference voltage (CH.3) VREF3 *30.98 1.00 1.02 V
VREF Line regulation VREF_LINE VCC=2.5 to 18V ±2 ±5 mV
VREF Variation with temperature VREF_TC1 Ta=–30 to +85˚C ±0.5 %
Input bias current IIN–VINx–=0.0 to 2.5V *40.0 mA
Open loop gain AVO 70 dB
Unity gain bandwidth fT1.5 MHz
Output current (sink) ISIFB VFBx=0.5V, VINx–=VREG *42.3 3.5 4.7 mA
Output current (source) ISOFB VFBx=VREG–0.5V, VINx–=0V *4–360 –270 –180 µA
*1 The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset v oltage of the error amplifier is included.
*2 The FB2 voltage is measured under the condition that IN2- pin and FB2 pin are shorted. The input offset v oltage of the error amplifier is included.
*3 The FB3 voltage is measured under the condition that IN3- pin and FB3 pin are shorted. The input offset v oltage of the error amplifier is included.
*4 The “x” of INx- and FBx refers to 1 to 3.
Soft start section (CS1, CS2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage (CS1) VCS1D0 Duty cycle=0%, VFB1=1.4V 0.82 V
VCS1D20 Duty cycle=20%, VFB1=1.4V 0.89 0.925 0.96 V
VCS1D80 Duty cycle=80%, VFB1=1.4V 1.25 1.285 1.32 V
Threshold voltage (CS2) VCS2D0 Duty cycle=0%, VFB2=0.7V 1.33 V
VCS2D20 Duty cycle=20%, VFB2=0.7V 1.20 1.235 1.27 V
VCS2D80 Duty cycle=80%, VFB2=0.7V 0.84 0.875 0.91 V
Charge current of CS2 (source) ICS1 VCS1=0.5V –2. –2.0 –1.5 µA
Charge current of CS2 (sink) ICS2 VCS2=VREG–0.5V 1.5 2.0 2.4 µA
Pulse width modulation (PWM) section (FB1, FB2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
Max. duty cycle of OUT1 DMAX1 fOSC=300kHz 87 %
RT=12kΩ (fOSCⱌ500kHz) 80 85 90 %
fOSC=1.5MHz 78 %
Max. duty cycle of OUT2 DMAX2 fOSC=300kHz 88 %
RT=12k (f OSCⱌ500kHz) 80 85 90 %
fOSC=1.5MHz 73 %
Threshold voltage of FB1 VFB1D0 Duty cycle=0% 0.82 V
VFB1D20 Duty cycle=20% 0.925 V
VFB1D80 Duty cycle=80% 1.285 V
Threshold voltage of FB2 VFB2D0 Duty cycle=0% 1.33 V
VFB2D20 Duty cycle=20% 1.235 V
VFB2D80 Duty cycle=80% 0.875 V
Oscillator section (RT pin)
Item Symbol Test condition Min. Typ. Max. Unit
Oscillation frequency fOSC 435 500 565 kHz
Line regulation fOSC_LINE VCC=2.5 to 18V ±1 ±5 %
Variation with temperature fOSC_TC1 Ta=–30 to +85˚C±3%
FA3686V
4
PGS section (VCC, PGS pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage of VCC VPGS VCC decreasing 2.15 2.25 2.35 V
Hysteresis voltage 䉭VPGS VCC increasing 0.10 V
VPGS variation with temperature VPGS_TC1 Ta=–30 to +85˚C±1%
On resistance RPGS VCC=2.2V, IPGS=10mA 50 100 Ω
*1 The latched mode operates when the voltage of FB1 or FB3 exceeds the threshold voltage as shown in the table.
*2 The latched mode operates when the FB2 voltage falls below the threshold voltage as sho wn in the table.
*3 The timer latch of FB1 is disabled when the CS1 v oltage is below the threshold voltage as shown in the table.
*4 The timer latch of FB2 is disabled when the CS2 v oltage is above the threshold voltage as shown in the table.
Under voltage lockout circuit section (VCC pin)
Item Symbol Test condition Min. Typ. Max. Unit
ON threshold voltage of VCC VUVLO 2.0 2.2 2.35 V
Hysteresis voltage 䉭VUVLO 0.1 V
Timer latch protection section (TL pin)
Item Symbol Test condition Min. Typ. Max. Unit
Threshold voltage of FB1 VTHFB1TL *11.5 2.0 V
Threshold voltage of FB2 VTHFB2TL *20.2 0.6 V
Threshold voltage of FB3 VTHFB3TL *11.5 2.0 V
Threshold voltage of CS1 VVTHCS1TL *30.2 0.6 V
Threshold voltage of CS2 VVTHCS2TL *41.5 2.0 V
TL pin voltage for counting 16th stage VTL16 00.2V
TL pin voltage counting 17th stage VTL17
VREG–0.2
VREG V
* The “x” of OUTx refers to 1, 2.
Output section (OUT1, OUT2 pin)
Item Symbol Test condition Min. Typ. Max. Unit
High side on resistance of OUT1/2 RONHI IOUTx=-50mA * 10 20 Ω
IOUTx=-50mA, VCC=5V * 9 Ω
IOUTx=-50mA, VCC=15V * 8 Ω
Low side on resistance of OUT1/2 RONLO IOUTx=50mA * 5 10 Ω
IOUTx=50mA, VCC=5V * 5 Ω
IOUTx=50mA, VCC=15V * 5 Ω
Rise time of OUT1/2 tRISE CL=1000pF 25 ns
Fall time of OUT1/2 tFALL CL=1000pF 40 ns
Overall section
Item Symbol Test condition Min. Typ. Max. Unit
Supply current ICCA Ch.1, Ch.2 operating mode 3.0 4.0 mA
ICCA1 Ch.1, Ch.2 off mode 2.5 mA
ICCA2 Ch.1, Ch.2 operating mode, VCC=18V 3.5 mA
ICCA3 Latch mode 2.5 mA
FA3686V
5
■ Characteristic curves
Oscillation frequency vs. timing resistor Oscillation frequency vs. supply v olta ge VCC
VCC=3.3V, Ta=25˚C Ta=25˚C, RT=12kΩ (fOSC=500kHz)
Oscillation frequency vs. ambient temperature Regulated voltage vs. supply voltage VCC
VCC=3.3V, RT=12kΩ (fOSC=500kHz) Ta=25˚C, RT=12kΩ (fOSC=500kHz)
Regulated voltage vs. ambient temperature Regulated voltage vs. load current
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
0
200
400
600
800
1000
1200
1400
1600
1800
1 10 100
Timing resistor R
T
[kΩ]
Oscillation frequency [kHz]
490
492
494
496
498
500
502
504
506
508
510
0 5 10 15 20
Vcc [V]
Oscillation frequency [kHz]
430
450
470
490
510
530
550
570
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Oscillation frequency [kHz]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0 5 10 15 20
Vcc [V]
Regulated voltage V
REG
[V]
Load current
I
REG
=0A
2.17
2.18
2.19
2.20
2.21
2.22
2.23
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Regulated voltage V
REG
[V]
2.17
2.18
2.19
2.20
2.21
2.22
2.23
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Load current IREG [mA]
Regulated voltage V
REG
[V]
Ta=-30˚C
Ta=25˚C
Ta=85˚C
FA3686V
6
Reference voltage vs. supply voltage VCC Reference v olta ge vs. ambient temperature
Ta=25˚C, RT=12kΩ (f OSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Error amp. output current (sink) vs. ambient temperature Error amp. output current (source) vs. ambient temperarure
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Charge current of CS1 (source) vs. ambient temperature Charge current of CS2 (sink) vs. ambient temperature
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0 5 10 15 20 25
Vcc [V]
Reference voltage V
REF
[V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Reference voltage V
REF
[V]
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Output current (sink) I
SIFB
[mA]
-350
-300
-250
-200
-150
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Output current (source) I
SOFB
[uA]
-3.0
-2.5
-2.0
-1.5
-1.0
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Charge current of CS1 (source) I
CS1
[uA]
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Charge current of CS2 (sink) I
CS2
[uA]
FA3686V
7
Output duty cyc le vs. CS voltage (ch. 1) Output duty cyc le vs. oscillation frequency (ch. 1)
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
Output duty cyc le vs. CS voltage (ch. 2) Output duty cyc le vs. oscillation frequency (ch. 2)
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
0
10
20
30
40
50
60
70
80
90
100
0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50
VCS1 [V]
Output duty cycle (ch.1) [%]
fosc=300kHz fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Output duty cycle (ch.1) [%]
VCS1=0.85V
VCS1=0.90V
VCS1=0.95V
VCS1=1.00V
VCS1=1.05V
VCS1=1.10V
VCS1=1.15V
VCS1=1.20V
VCS1=1.25V
VCS1=1.30V
0
10
20
30
40
50
60
70
80
90
100
0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40
VCS2 [V]
Output duty cycle (ch.2) [%]
fosc=300kHz
fosc=500kHz
fosc=760kHz
fosc=1.5MHz
0
10
20
30
40
50
60
70
80
90
100
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Duty 2 [%]
VCS2=0.85V
VCS2=1.30V
VCS2=1.25V
VCS2=1.20V
VCS2=1.15V
VCS2=1.10V
VCS2=1.05V
VCS2=1.00V
VCS2=0.95V
VCS2=0.90V
Maximum duty c ycle vs. oscillation frequency (ch. 1) Maxim um duty cycle vs. oscillation frequency (c h. 2)
VCC=3.3V, Ta=25˚CVCC=3.3V, Ta=25˚C
65
70
75
80
85
90
95
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
D
MAX1
[%]
65
70
75
80
85
90
95
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
D
MAX2
[%]
FA3686V
8
Maximum duty c ycle vs. ambient temperature (ch. 1) Maximum duty c yc le vs. ambient temperature (ch. 2)
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
OUT1 terminal sour ce current vs. H level output v olta ge OUT2 terminal source current vs. H le vel output voltage
Ta=25˚C Ta=25˚C
80
81
82
83
84
85
86
87
88
89
90
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
DMAX1 [%]
80
81
82
83
84
85
86
87
88
89
90
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta[˚C]
D
MAX2
[%]
OUT1 terminal sour ce current vs. H level output v olta ge OUT2 terminal source current vs. H le vel output voltage
VCC=3.3V VCC=3.3V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0
Vcc-VOUT1 [V]
IOUT1 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-500
-450
-400
-350
-300
-250
-200
-150
-100
-50
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT2 [V]
IOUT2 [mA]
Vcc=2.5V
Vcc= 3V
Vcc= 5V
Vcc=12V
-300
-250
-200
-150
-100
-50
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc-VOUT1 [V]
IOUT1 [mA]
Ta=-30˚CTa=25˚C
Ta=85˚C
-300
-250
-200
-150
-100
-50
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc-VOUT2 [V]
IOUT2 [mA]
Ta=-30˚C
Ta=85˚C
Ta=25˚C
FA3686V
9
OUT1 terminal sour ce current vs. H level output v olta ge OUT2 terminal source current vs. H le vel output voltage
VCC=12V VCC=12V
-500
-400
-300
-200
-100
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT1 [V]
IOUT1 [mA]
Ta=85˚C
Ta=-30˚C
Ta=25˚C
-500
-400
-300
-200
-100
0
0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT2 [V]
IOUT2 [mA]
Ta=-30˚C
Ta=25˚C
Ta=85˚C
OUT1 terminal sink current vs. L level v oltage OUT2 terminal sink current vs. L level volta ge
OUT1 terminal rise time vs. supply volta ge VCC OUT2 terminal rise time vs. suppl y voltage VCC
CL=1000pF CL=1000pF
0
50
100
150
200
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT1 [V]
IOUT1 [mA]
Ta=-30˚CTa=25˚C
Ta=85˚C
0
50
100
150
200
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT2 [V]
IOUT2 [mA]
Ta=-30˚C
Ta=85˚C
Ta=25˚C
0
10
20
30
40
50
60
0 5 10 15 20
Vcc [V]
OUT1 terminal rise time t RISE [ns]
Ta=-30˚C
Ta=25˚C
Ta=85˚C
0
10
20
30
40
50
60
0 5 10 15 20
Vcc [V]
OUT2 terminal rise time t RISE [ns]
Ta=25˚C
Ta=85˚C
Ta=-30˚C
FA3686V
10
OUT1 terminal fall time vs. supply volta ge VCC OUT2 terminal fall time vs. suppl y voltage VCC
CL=1000pF CL=1000pF
Operating mode supply current vs. oscillation frequency Operating mode supply current vs. ambient temperature
Ta=25˚C
UVLO ON threshold vs. ambient temperature PGS terminal on resistance vs. ambient temperature
0
50
100
150
200
0 5 10 15 20
Vcc [V]
OUT1 terminal fall time t FALL [ns]
Ta=-30˚C
Ta=25˚C
Ta=85˚C
0
50
100
150
200
0 5 10 15 20
Vcc [V]
OUT2 terminal fall time t
FALL
[ns]
Ta=25˚C
Ta=-30˚C
Ta=85˚C
2.0
3.0
4.0
5.0
6.0
300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]
Operating mode supply current ICCA [mA]
Vcc=12V
Vcc=18V
Vcc=2.5V
Vcc=5V
Vcc=3.3V
2.0
2.5
3.0
3.5
4.0
4.5
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
Operating mode supply current I
CCA
[mA]
Vcc=5V
Vcc=12V
Vcc=2.5V
Vcc=3.3V
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
UVLO ON threshold V
UVLO
[V]
0
10
20
30
40
50
60
70
80
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
R
PGS
[Ω]
Vcc=3.3V
Vcc= 5V
Vcc=2.5V
FA3686V
11
PGS terminal current vs. voltage PGS terminal threshold volta ge of VCC vs.
Ta=25˚Cambient temperature
CS1 internal dischar ge switc h current vs. volta ge CS2 internal discharge s witc h current vs. volta ge
VCC=3.3V, RT=12kΩ (fOSC=500kHz) VCC=3.3V, RT=12kΩ (fOSC=500kHz)
Error amplifier gain and phase vs. frequency
0
5
10
15
20
25
30
35
40
45
0.0 0.5 1.0 1.5 2.0 2.5
VPGS [V]
IPGS [mA]
Vcc=7.0V
Vcc=3.3V
Vcc=2.2V
vcc=1.8V
vcc=1.5V
Vcc=5V
2.15
2.20
2.25
2.30
2.35
-50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [˚C]
V
PGS
[V]
0
50
100
150
200
250
300
350
400
0.00 0.50 1.00 1.50 2.00 2.50
V
CS1
[V]
ICS1 off [uA]
Ta=-30˚C
Ta=25˚C
Ta=85˚C
-200
-150
-100
-50
0
0.00 0.50 1.00 1.50 2.00
V
REG
-V
CS2
[V]
ICS2 off [uA]
Ta=-30˚CTa=25˚C
Ta=85˚C
FA3686V
12
■ Description of each circuit
1. Reference voltage circuit (VREF)
This circuit generates the reference voltage of 1.00V (ch1: ±1%;
ch2, 3: ±2%) compensated in temperature from VCC voltage ,
and is connected to the non-in v erting input of the error amplifier .
This v oltage cannot be observed directly because an external
pin f or this purpose is not provided.
2. Regulated voltage circuit (VREG)
This circuit generates 2.20V±1% based on the reference
voltage VREF, and is used as the power supply of the internal IC
circuits. This voltage is generated when the supply voltage ,
VCC, is input. The VREG voltage also is used as a regulated
power supply for soft start and others. The output current f or
e xternal circuit should be within 1mA. A capacitor connected
between VREG pin and GND pin is necessary to stab le the
VREF voltage (To determine capacitance , refer to recommended
operating conditions). The VREG voltage is regulated in VCC
voltage of 2.4V or above.
3. Oscillator
The oscillator generates a triangular wavef orm by charging and
discharging the built-in capacitor. A desired oscillation
frequency can be set by the value of the resistor connected to
the R T pin (Fig. 1). The built-in capacitor voltage oscillates
between approximately 0.82V and 1.38V at fosc=500kHz (that
of ch1 and ch2 are slightly diff erent) with almost the same
charging and discharging gradients (Fig. 2). You can set the
desired oscillation frequency b y changing the gr adients using
the resistor connected to the R T pin. (Large RT: lo w frequency,
small RT: high frequency) The oscillator wav eform cannot be
observed from the outside because a pin for this purpose is not
provided. The RT pin voltage is approximately 1V DC in normal
operation. The oscillator output is connected to the PWM
comparator.
4. Error amplifier circuit
The error amplifiers 1, 2, 3 hav e in v erting input pins of IN1– pin
(Pin 14), IN2– pin (Pin 4) and IN3– pin (Pin 2). The non-inverting
input is internally connected to the reference v oltage VREF of the
error amplifier 1 (1.00V±1%; 25˚C) and the error amplifiers 2, 3
(1.00V±2%; 25˚C). The FB pins (Pin1, Pin15) are the output of
the error amplifiers. An e xternal RC network is connected
between FB pin and IN– pin for gain and phase compensation
setting. The error amplifier 3 can be used for a series regulator.
Fig. 1
Fig. 2
12
OSC
R
T
RT
R
T
value: small R
T
value: large
0.82V
1.38V
+
14 15
3
13
IN1-
VREG
IN2- FB2
FB1
Comp
Vout1
Vout2
R
NF
1
R
NF2
VREF
(1.0V)
R1
R2
R3
R4
4
21
R5
R6
R
NF3
FB3
Er.Amp.1
Er.Amp.2
Er.Amp.3
IN3-
Vout3
Fig. 3
FA3686V
13
5. PWM comparator
The PWM output generates from the oscillator output, the error
amplifier output (FB1, FB2) and CS v oltage (CS1, CS2) (Fig. 4).
The oscillator output is compared with the pref erred lo wer
voltage betw een FB1 and CS1 for ch1. While the preferred
voltage is lower than oscillator output, the PWM output is low.
While the pref erred voltage is higher than oscillator output, the
PWM output is high. Since the phase of Ch2 is the opposite
phase of Ch1, higher v oltage betw een FB2 and CS2 is
pref erred and while the preferred voltage is lo w er than the
oscillator output, the PWM output 2 is high. (Cannot be
observed externally) The output polarity of OUT1, OUT2
changes according to the condition of SEL pin. (See Fig. 6)
The maximum duty cycle (DMAX1, DMAX2) is internally set
appro ximately 85%. Note that the maximum duty cycle depends
on operation frequencies . (See the characteristics curve: Output
duty cycle vs. oscillation frequency)
6. Soft start function
This IC has a soft start function to protect DC-to-DC converter
circuits from damage when starting operation. CS1 pin (Pin10)
and CS2 pin (Pin7) are used f or soft start function of ch1 and
ch2 respectiv ely. (Fig. 5) When the supply voltage is applied to
the VCC pin and UVLO is cancelled, the capacitor CCS1 and
CCS2 is charged b y the internal constant current sources (2µA,
typ .). Then, the CS1 voltage gradually increases, and the CS2
voltage g r adually decreases . Since the CS1, and CS2 are
connected to the PWM comparator, the pulses gradually widen
and then the soft start function operates. (Fig. 6)
Fig. 4
Fig. 5
Nch.
drive
Pch.
drive
UVLO
Oscillator
output
CS1
CS2
FB2
FB1 OUT1
OUT2
PWM
Comp.1
PWM
Comp.2
PWM
output1
9
8
PWM output2
D
MAX1
D
MAX2
13
10
CS1
VREG
CCS1
13
7
VREG
CS2
CCS2
Oscillator output CS1 pin voltage
Er. amp.1 output
PWM output 1
OUT1
Nch.drive
Oscillator output
CS2 pin voltage Er. amp.2 output
PWM output2
OUT2
Pch. drive
Fig. 6
FA3686V
14
7. Timer latch short-circuit protection circuit
This IC has the timer latch short-circuit protection circuit. The
circuit cuts off the output of all channels when the output
voltage of DC-to-DC converter drops due to short circuit or
overload. Dela y time of the timer latch mode is set by a counter
system in the internal circuit, therefore, no external parts are
necessary. When one of the output voltage of the DC-to-DC
converter drops due to a short circuit or overload, the FB1 and
FB3 pin v oltage increases up to around the VREG v oltage for
ch1 and ch3, or the FB2 pin v oltage drops do wn to around 0V
f or ch2.
The counter system operates when the FB1 or FB3 pin voltage
e xceeds the timer latch threshold voltage of 2.0V(max.) or FB2
pin voltage falls below timer latch threshold voltage of
0.2V(min.). The counter system counts oscillator waveform. If
this system counts the oscillation cycles of 216 times (TL pin:
GND, 16th stage counter) or 217 times (TL pin: VREG, 17th
stage counter), this circuit detects short circuit. Then the IC is
set to off latch mode and the output of all channels is shut off
and the current consumption becomes 2.5mA (typ.). (Fig. 7)
If the DC-to-DC converters return to normal before counter
system counts 216 or 217, counter is reset.
The period (tp) between the occurrences of short-circuit in the
converter output and setting to off latch mode can be calculated
by the following equations:
Example. When f osc=500kHz and TL pin to GND, the period tp is:
tp=216 ⫻1/500kHz=0.131sec.
You can reset off latched mode of the short-circuit protection b y
either of the f ollo wing w ays to 1) CS pins, or 2) VCC pin:
1) Set the CS pin of the cause of off latch mode as follows.
CS1 pin voltage = 0V, CS2 pin v oltage = VREG
2) VCC voltage is below UVLO off threshold voltage (2.1V typ.).
Connect the TL pin to either VREG or GND. If TL pin is
opened, the counter operation is unstab le .
8. Output circuit
The IC contains a push-pull output stage and can directly drive
MOSFETs. The maximum peak current of the output stage is
sink current of +150mA, and source current of –400mA. The IC
can also drive NPN and PNP transistors. The maximum current
in such cases is ±50mA. You must design the output current
considering the rating of pow er dissipation. (See “Design
advice”.)
9. Underv olta ge loc kout circuit
The IC contains an undervoltage lockout circuit to protect the
circuit from the damage caused by malfunctions when the
supply voltage drops. When the supply voltage rises from 0V,
the IC starts to operate at VCC of 2.2V (typ.) and outputs
generate pulses . If a drop of the supply v oltage occurs, it stops
output at VCC of 2.1V (typ.). When it occurs , the CS1 pin is
turned to low le v el and the CS2 pin to high level, and then these
pins are reset.
Timer latch count Timer latch count
Momentary
short circuit Short circuit
Short circuit
protection
tp
FB1 or 3
Time t
Time t
Off latch mode
Oscillator output
OUT1
Timer latch
count
Timer latch
count
Momentary
short circuit
Short circuit
Short circuit
protection
tp
FB2
Time t
Time t
Off latch mode
OUT2
Oscillation output
Fig. 7
Ch1
Ch2
tp [s] = 216 ⫻1
fosc TL pin: GND
tp [s] = 217 ⫻1
fosc TL pin: VREG
FA3686V
15
10. PGS circuit
The PGS pin is an open drain output of Nch MOSFET for
transmitting fault signals of the power supply. The PGS circuit is
enabled when Vcc v oltage is over the operating threshold
voltage (approximately 1V). The Nch MOSFET turns ON and
the PGS pin is connected to GND if an y of the following three
conditions occurs:
1) the VCC voltage is belo w the threshold voltage (VCC
increasing: 2.35V typ.; VCC decreasing: 2.25V typ.), 2) UVLO
turns on (VCC=2.1V or below), 3) IC is off latch mode.
The operation sequence is sho wn in Fig. 8.
As shown in Fig. 8, in the case of increasing the Vcc voltage
with the v oltage V applied to the PGS pin, when the Vcc voltage
reaches 1V, PGS circuit is enabled and detects that the Vcc
voltage is not enough high. Then PGS circuit turns the Nch
MOSFET on and output f ault signal. The fault signal is
cancelled when the VCC voltage exceeds 2.35V (typ.).
In the case that the VCC voltage exceeds 2.53V (typ.) and the
IC is off latch mode, the PSG circuit detects it as abnormal and
the Nch MOSFET is turned on.
In the case of decreasing the VCC voltage , the circuit sends out
f ault signals when the VCC v oltage is belo w 2.25V (typ.) and
continues to output until the VCC voltage reaches below the
PGS circuit operation threshold voltage of approximately 1V.
(Under the VCC voltage of 1V, the circuit does not operate
normally.) Fig. 8
+
5
PGS
11
V
UVLO
VPGS
Timer latch
V
CC
decreasing
V
CC
increasing
1V
V
PGS
voltage 2.25V
Hysteresis voltage
PGS
pin voltage
Vcc voltage stable state
Off latch mode
Off latch mode reset
PGS operation PGS operation PGS operation
Vcc
V
FA3686V
16
■ Design advice
1. Setting the oscillation frequency
As described in item 1, “Description of each circuit,” a desired
oscillation frequency can be determined by the v alue of the
resistor connected to the R T pin. When designing an oscillation
frequency, you can set an y frequency betw een 300kHz and
1.5MHz. You can obtain the oscillation frequency from the
characteristic curve “Oscillation frequency (fosc) vs. timing
resistor resistance (RT)” or the value can be appro ximately
calculated by the following e xpression.
This e xpression, ho w ever, can be used for rough calculation,
the obtain v alue is not guaranteed. The oper ation frequency
varies due to the conditions such as toler ance of the
characteristics of the ICs, influence of noises , or external
discrete components. When determining the values , examine
the eff ectiveness of the values in an actual circuit. The timing
resistor RT should be wired to the GND pin as shortly as
possible because the RT pin is a high impedance pin and is
easy aff ected b y noises .
2. Determining soft start period
The period from the start of charging the capacitor CCS to
widening n% of output duty cycle can be roughly calculated b y
the f ollo wing expression: (see Fig. 5 for symbols)
VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in
n% of output duty cycle, and vary in accordance with operating
frequency. The value can be obtained from the characteristic
curv e “Output duty cycle vs. CS voltage”
The charging of the CCS1 and CCS2 starts after the UVLO is
unlock ed. Therefore, the period from power-on of VCC to
widening n% of output duty cycle is the sum of t0 and t.
To reset the soft start function, the supply voltage VCC is
low ered belo w the UVLO voltage (2.1V typ.) and then the
internal switch discharges the CS capacitor. The characteristics
of the internal switch for discharge are shown in following the
characteristics curves of “Char acteristics of CS1 internal
discharge s witch current vs . voltage” and “Characteristics of
CS2 internal discharge switch current vs . v oltage”. Therefore,
when determining the period of soft start at restarting the power
supply, consider the characteristics carefully.
t [s] = VCS2n ⫻ CCS1
ICS1 For CS1 pin
t [s] = (VREG
–
VCS2n)
⫻
CCS1
ICS2 For CS2 pin
CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [µF]
ICS1, ICS2: CS charge current [µA] (2µA typ .)
fOSC = 4050 ⫻
RT –0.86
fOSC: Oscillation frequency [kHz]
RT: Timing resistor [kΩ]
( )
RT = 4050
fOSC
1.16
VCC pin voltage
CS1 pin voltage
Threshold
voltage
VCS1n
t0 t
Fig. 9
FA3686V
17
3. Determining the output voltage of DC-DC converter s
The ways to determine the output v oltage of the DC-DC
converter of each channel is shown in Fig. 10 and the f ollo wing
equations.
F or ch1:
The output voltage of a boost circuit is determined b y:
F or ch2:
The output voltage of an inverting circuit is determined by:
The ratio of resistances is determined by:
(Use the absolute value of the Vout2 voltage .)
F or ch3:
The output voltage of a series regulator is determined by:
4. Restriction of external discrete components and
recommended operating conditions
To achiev e a stable oper ation of the IC , the v alue of external
discrete components connected to VCC, VREG, CS pins should
be within the recommended operating conditions . And the
v oltage and current applied to each pin should be also within the
recommended operating conditions . If the pin v oltage of OUT1,
OUT2, or VREG becomes higher than the VCC pin v oltage , the
current flows from the pins to the VCC pin because parasitic
three diode e xist between the VCC pin and these pins. Be careful
not to allow this current to flo w.
5. Loss calculation of IC
Since it is difficult to measure IC loss directly, the calculation to
obtain the appro ximate loss of the IC connected directly to a
MOSFET is described below.
When the supply voltage is VCC, the current consumption of the
IC is ICCA, the total input gate charge of the driven MOSFET is
Qg and the s witching frequency is fs w, the total loss Pd of the IC
can be calculated by:
Pd ⱌ VCC ⫻ (ICCA + Qg ⫻ fs w).
The value in this expression is influenced by the eff ects of the
dependency of supply v oltage, the char acteristics of temperature ,
or the tolerance of parameter. Therefore, e v aluate the
appropriateness of IC loss sufficiently considering the range of
v alues of abov e parameters under all conditions .
Example:
ICCA=3.0mA for VCC=3.3V in the case of a typical IC from the
characteristics curv e . Qg=6nC , fs w=500kHz, the IC loss “Pd” is
as f ollows .
Pd ⱌ 3.3 ⫻ (3.0mA + 6nC ⫻ 500kHz) ⱌ 19.8mW
If two MOSFETs are driven under the same condition for 2
channels, Pd is as f ollo ws:
Pd ⱌ 3.3 ⫻ {3.0mA + 2 ⫻ (6nC ⫻ 500kHz)} = 29.7mW
IN1-
FB1
Vout1
R2
R1
OUT1
Vout1
9
15
14
+
VREF
(1.0V)
IN2-
FB2
Vout2
R4
R3
OUT2 Vout2
8
3
4
+
VREF
(1.0V)
VREG
13
IN3- FB3
Vout3
R6
R5
Vout3
1
2
+
VREF
(1.0V)
Vout1 = R1 + R2 ⫻ VREF
R2
Vout2 = R3 + R4 ⫻
VREF –R4 ⫻ VREG
R3 R3
Vout3 = R5 + R6 ⫻ VREF
R6
R3 =VREG – VREF
R3 Vout2 + V REF
Fig. 10
FA3686V
18
■ Application circuit
4700pF
0.47uF
2200pF
0.047uF
1uF
0.022uF
4700pF
10kΩ
4.7kΩ
10kΩ
12kΩ
0.1uF 0.1uF
180kΩ
13kΩ
10kΩ
4700pF
4kΩ
1kΩ
470Ω
1000pF
11kΩ
2.2kΩ
470Ω
1000pF
10uF
2.9 to 3.6V
10V/5mA
5.0V/200mA
-5.0V/100mA
PGS
GND
4.7uF
15uF
10uF
0.1uF
0.1uF
FB1 IN1-
IN2-
GND
PGS
FB2
IN3-
FB3
CS1
CS2
RT
VREG OUT1
VCC OUT2
TL
FA3686V
15 14 11 10
12
13 916
45
3
2
17
68
47kΩ
33kΩ
Parts tolerances characteristics are not defined in the circuit design
sample shown above. When designing an actual circuit for a product,
you must determine parts tolerances and characteristics for safe and
economical operation.
