Mobile LPDDR2 SDRAM
MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,
MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,
MT42L256M64D4, MT42L384M32D3
Features
• Ultra low-voltage core and I/O power supplies
–V
DD2 = 1.14–1.30V
–V
DDCA/VDDQ = 1.14–1.30V
–V
DD1 = 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed
Grade
Clock Rate
(MHz)
Data Rate
(Mb/s/pin) RL WL tRCD/tRP1
-18 533 1066 8 4 Typical
-25 400 800 6 3 Typical
-3 333 667 5 2 Typical
Options Marking
•V
DD2: 1.2V L
• Configuration
– 32 Meg x 16 x 8 banks x 1 die 256M16
– 16 Meg x 32 x 8 banks x 1 die 128M32
– 16 Meg x 32 x 8 banks x 2 die 256M32
– 1 (16 Meg x 32 x 8 banks) + 2 (32
Meg x 16 x 8 banks)
384M32
– 32 Meg x 16 x 8 banks x 4 die 512M32
– 16 Meg x 32 x 8 banks x 2 die 128M64
– 16 Meg x 32 x 8 banks x 3 die 192M64
– 16 Meg x 32 x 8 banks x 4 die 256M64
• Device type
– LPDDR2-S4, 1 die in package D1
– LPDDR2-S4, 2 die in package D2
– LPDDR2-S4, 3 die in package D3
– LPDDR2-S4, 4 die in package D4
• FBGA “green” package
– 134-ball FBGA (10mm x
11.5mm)
GU, GV
– 168-ball FBGA (12mm x 12mm) LF, LG
– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,
LP
– 220-ball FBGA (14mm x 14mm) LD, MP
– 240-ball FBGA (14mm x 14mm) MC
– 253-ball FBGA (11mm x 11mm) EU, EV
• Timing – cycle time
– 1.875ns @ RL = 8 -18
– 2.5ns @ RL = 6 -25
– 3.0ns @ RL = 5 -3
• Operating temperature range
– From –30°C to +85°C WT
– From –40°C to +105°C AT
• Revision :A
Note: 1. For Fast tRCD/tRP, contact factory.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Single Channel S4 Configuration Addressing
Architecture 256 Meg x 16 128 Meg x 32 256 Meg x 32 384 Meg x 32 512 Meg x 32
Die
configuration
CS0# 32 Meg x 16 x 8
banks
16 Meg x 32 x 8
banks
16 Meg x 32 x 8
banks
16 Meg x 32 x 8
banks
32 Meg x 16 x 8
banks
CS1# n/a n/a 16 Meg x 32 x 8
banks
32 Meg x 32 x 8
banks
32 Meg x 16 x 8
banks
Row addressing 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0])
Column
addressing
CS0# 2K (A[10:0]) 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 2K (A[10:0])
CS1# n/a n/a 1K (A[9:0]) 2K (A[10:0]) 2K (A[10:0])
Number of die 1 1 2 3 4
Die per rank CS0# 1 1 1 1 2
CS1# 0 0 1 2 2
Ranks per channel 111222
Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.
Table 3: Dual Channel S4 Configuration Addressing
Architecture 128 Meg x 64 192 Meg x 64 256 Meg x 64
Die configuration 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks
Row addressing 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0])
Column addressing CS0# 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])
CS1# n/a 1K (A[9:0]) 1K (A[9:0])
Number of die 2 3 4
Die per rank CS0# 1 1 1
CS1# 0 1 = Channel A
0 = Channel B
1
Ranks per channel 1Channel A 1 2 2
Channel B 1 1 2
Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Figure 1: 4Gb LPDDR2 Part Numbering
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
Operating Voltage
L = 1.2V
Configuration
256M16 = 256 Meg x 16
128M32 = 128 Meg x 32
256M32 = 256 Meg x 32
384M32 = 384 Meg x 32
512M32 = 512 Meg x 32
128M64 = 128 Meg x 64
192M64 = 192 Meg x 64
256M64 = 256 Meg x 64
Addressing
D1 = LPDDR2, 1 die
D2 = LPDDR2, 2 die
D3 = LPDDR2, 3 die
D4 = LPDDR2, 4 die
Design Revision
:A = First generation
Operating Temperature
WT = –30°C to +85°C
AT = –40°C to +105°C
Cycle Time
-18 = 1.875ns, tCK RL = 8
-25 = 2.5ns, tCK RL = 6
-3 = 3.0ns, tCK RL = 5
Package Codes
GU, GV = 134-ball FBGA, 10mm x 11.5mm
LF, LG = 168-ball FBGA, 12mm x 12mm
LH, LK, LL, LM, LP = 216-ball FBGA, 12mm x 12mm
LD, MP = 220-ball FBGA, 14mm x 14mm
MC = 240-ball FBGA, 14mm x 14mm
EU, EV = 253-ball FBGA, 11mm x 11mm
MT 42 L 128M32 D1 GU -25 WT :A
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Table 4: Package Codes and Descriptions
Package
Code Ball Count # Ranks # Channels Size (mm)
Die per
Package
Solder Ball
Composition
GU 134 1 1 10 x 11.5 x 0.7, 0.65 pitch SDP LF35 (w/OSP)
GV 134 2 1 10 x 11.5 x 0.85, 0.65 pitch DDP LF35 (w/OSP)
LF 168 1 1 12 x 12 x 0.75, 0.5 pitch SDP SAC305
LG 168 2 1 12 x 12 x 0.8, 0.5 pitch DDP SAC305
LH 216 1 1 (Chan B only) 12 x 12 x 0.65, 0.4 pitch SDP SAC305
LL 216 1 2 12 x 12 x 0.8, 0.4 pitch DDP SAC305
LM 216 2 2 12 x 12 x 1.0, 0.4 pitch QDP SAC305
LK 216 2 1 (Chan B only) 12 x 12 x 0.8, 0.4 pitch DDP SAC305
LP 216 2 1 (Chan B only) 12 x 12 x 0.82, 0.4 pitch 3DP SAC305
MP 220 1 2 14 x 14 x 0.8, 0.5 pitch DDP SAC305
LD 220 2 2 14 x 14 x 1.0, 0.5 pitch QDP SAC305
MC 240 1 2 14 x 14 x 0.8, 0.5 pitch DDP SAC305
EU 253 1 2 11 x 11 x 0.9, 0.5 pitch DDP LF35 (w/OSP)
EV 253 2 2 11 x 11 x 1.2, 0.5 pitch QDP LF35 (w/OSP)
Notes: 1. SDP = single-die package, DDP = dual-die package, 3DP = triple-die package, QDP = quad-die package
2. Solder ball material: LF35 with Cu OSP ball pads (98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni),
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Contents
General Description ....................................................................................................................................... 12
General Notes ............................................................................................................................................ 12
IDD Specifications ........................................................................................................................................... 13
Package Block Diagrams ................................................................................................................................. 18
Package Dimensions ....................................................................................................................................... 24
Ball Assignments and Descriptions ................................................................................................................. 37
Functional Description ................................................................................................................................... 46
Power-Up ....................................................................................................................................................... 47
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 49
Power-Off ....................................................................................................................................................... 49
Uncontrolled Power-Off .............................................................................................................................. 50
Mode Register Definition ................................................................................................................................ 50
Mode Register Assignments and Definitions ................................................................................................ 50
ACTIVATE Command ..................................................................................................................................... 61
8-Bank Device Operation ............................................................................................................................ 61
Read and Write Access Modes ......................................................................................................................... 62
Burst READ Command ................................................................................................................................... 62
READs Interrupted by a READ ..................................................................................................................... 69
Burst WRITE Command .................................................................................................................................. 69
WRITEs Interrupted by a WRITE ................................................................................................................. 72
BURST TERMINATE Command ...................................................................................................................... 72
Write Data Mask ............................................................................................................................................. 74
PRECHARGE Command ................................................................................................................................. 75
READ Burst Followed by PRECHARGE ......................................................................................................... 76
WRITE Burst Followed by PRECHARGE ....................................................................................................... 77
Auto Precharge ........................................................................................................................................... 78
READ Burst with Auto Precharge ................................................................................................................. 78
WRITE Burst with Auto Precharge ............................................................................................................... 79
REFRESH Command ...................................................................................................................................... 81
REFRESH Requirements ............................................................................................................................. 87
SELF REFRESH Operation ............................................................................................................................... 89
Partial-Array Self Refresh – Bank Masking .................................................................................................... 90
Partial-Array Self Refresh – Segment Masking .............................................................................................. 91
MODE REGISTER READ ................................................................................................................................. 92
Temperature Sensor ................................................................................................................................... 94
DQ Calibration ........................................................................................................................................... 96
MODE REGISTER WRITE Command ............................................................................................................... 98
MRW RESET Command .............................................................................................................................. 98
MRW ZQ Calibration Commands ................................................................................................................ 99
ZQ External Resistor Value, Tolerance, and Capacitive Loading .................................................................... 101
Power-Down ................................................................................................................................................. 101
Deep Power-Down ........................................................................................................................................ 108
Input Clock Frequency Changes and Stop Events ............................................................................................ 109
Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 109
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 110
NO OPERATION Command ........................................................................................................................... 110
Simplified Bus Interface State Diagram ....................................................................................................... 110
Truth Tables .................................................................................................................................................. 112
Electrical Specifications ................................................................................................................................. 120
Absolute Maximum Ratings ....................................................................................................................... 120
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Input/Output Capacitance ......................................................................................................................... 120
Electrical Specifications – IDD Specifications and Conditions ........................................................................... 121
AC and DC Operating Conditions ................................................................................................................... 124
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 127
VREF Tolerances ......................................................................................................................................... 128
Input Signal .............................................................................................................................................. 128
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 131
Single-Ended Requirements for Differential Signals .................................................................................... 132
Differential Input Crosspoint Voltage ......................................................................................................... 134
Input Slew Rate ......................................................................................................................................... 134
Output Characteristics and Operating Conditions ........................................................................................... 135
Single-Ended Output Slew Rate .................................................................................................................. 136
Differential Output Slew Rate ..................................................................................................................... 137
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 140
Output Driver Impedance .............................................................................................................................. 140
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 141
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 142
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 142
Clock Specification ........................................................................................................................................ 146
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 147
Clock Period Jitter .......................................................................................................................................... 147
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 147
Cycle Time Derating for Core Timing Parameters ........................................................................................ 148
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 148
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 148
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 148
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 149
Refresh Requirements .................................................................................................................................... 150
AC Timing ..................................................................................................................................................... 151
CA and CS# Setup, Hold, and Derating ........................................................................................................... 157
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 164
Revision History ............................................................................................................................................ 171
Rev. O – 08/13 ............................................................................................................................................ 171
Rev. N – 05/13 ............................................................................................................................................ 171
Rev. M – 10/12 ........................................................................................................................................... 171
Rev. L – 08/12 ............................................................................................................................................ 171
Rev. K – 07/12 ............................................................................................................................................ 171
Rev. J – 07/12 ............................................................................................................................................. 171
Rev. I – 05/12 ............................................................................................................................................. 171
Rev. H – 04/12 ............................................................................................................................................ 171
Rev. G – 04/12 ............................................................................................................................................ 172
Rev. F – 03/12 ............................................................................................................................................ 172
Rev. E – 02/12 ............................................................................................................................................ 172
Rev. D – 12/11 ............................................................................................................................................ 172
Rev. C – 12/11 ............................................................................................................................................ 172
Rev. B – 05/11 ............................................................................................................................................ 172
Rev. A – 02/11 ............................................................................................................................................ 172
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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List of Figures
Figure 1: 4Gb LPDDR2 Part Numbering ............................................................................................................ 3
Figure 2: VDD1Typical Self Refresh Current vs. Temperature ............................................................................. 17
Figure 3: VDD2 Typical Self Refresh Current vs. Temperature ............................................................................ 17
Figure 4: Single Rank, Single Channel Package Block Diagram ......................................................................... 18
Figure 5: Dual Rank, Single Channel Package Block Diagram ........................................................................... 18
Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram ................................................................ 19
Figure 7: Single Rank, Dual Channel Package Block Diagram ........................................................................... 20
Figure 8: Dual Rank, Dual Channel Package Block Diagram ............................................................................ 21
Figure 9: Dual Rank, Dual Channel (3 Die) Package Block Diagram .................................................................. 22
Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram .............................................................. 23
Figure 11: 134-Ball FBGA – 10mm x 11.5mm Single-Die (Package Code GU) ..................................................... 24
Figure 12: 134-Ball FBGA – 10mm x 11.5mm Dual-Die (Package Code GV) ....................................................... 25
Figure 13: 168-Ball FBGA – 12mm x 12mm Single-Die (Package Code LF) ........................................................ 26
Figure 14: 168-Ball FBGA – 12mm x 12mm Dual-Die (Package Code LG) .......................................................... 27
Figure 15: 216-Ball FBGA – 12mm x 12mm (Package Codes LK, LL) .................................................................. 28
Figure 16: 216-Ball FBGA – 12mm x 12mm (Package Code LM) ........................................................................ 29
Figure 17: 216-Ball FBGA – 12mm x 12mm (Package Code LH) ........................................................................ 30
Figure 18: 216-Ball FBGA – 12mm x 12mm (Package Code LP) ......................................................................... 31
Figure 19: 220-Ball FBGA – 14mm x 14mm Dual-Die (Package Code MP) ......................................................... 32
Figure 20: 220-Ball FBGA – 14mm x 14mm Quad-Die (Package Code LD) ......................................................... 33
Figure 21: 240-Ball FBGA – 14mm x 14mm Dual-Die (Package Code MC) ......................................................... 34
Figure 22: 253-Ball FBGA – 11mm x 11mm Dual-Die (Package Code EU) ......................................................... 35
Figure 23: 253-Ball FBGA – 11mm x 11mm Quad-Die (Package Code EV) ......................................................... 36
Figure 24: 134-Ball FBGA (x16) ....................................................................................................................... 37
Figure 25: 134-Ball FBGA (x32) ....................................................................................................................... 38
Figure 26: 168-Ball FBGA – 12mm x 12mm ..................................................................................................... 39
Figure 27: 216-Ball 2-Channel FBGA – 12mm x 12mm ..................................................................................... 40
Figure 28: 216-Ball 1-Channel (B) FBGA – 12mm x 12mm ................................................................................ 41
Figure 29: 220-Ball 2-Channel FBGA – 14mm x 14mm ..................................................................................... 42
Figure 30: 240-Ball 2-Channel FBGA – 14mm x 14mm ..................................................................................... 43
Figure 31: 253-Ball 2-Channel FBGA – 11mm x 11mm ..................................................................................... 44
Figure 32: Functional Block Diagram ............................................................................................................. 46
Figure 33: Voltage Ramp and Initialization Sequence ...................................................................................... 49
Figure 34: ACTIVATE Command .................................................................................................................... 61
Figure 35: tFAW Timing (8-Bank Devices) ....................................................................................................... 62
Figure 36: READ Output Timing – tDQSCK (MAX) ........................................................................................... 63
Figure 37: READ Output Timing – tDQSCK (MIN) ........................................................................................... 63
Figure 38: Burst READ – RL = 5, BL = 4, tDQSCK > tCK ..................................................................................... 64
Figure 39: Burst READ – RL = 3, BL = 8, tDQSCK < tCK ..................................................................................... 64
Figure 40: tDQSCKDL Timing ........................................................................................................................ 65
Figure 41: tDQSCKDM Timing ....................................................................................................................... 66
Figure 42: tDQSCKDS Timing ......................................................................................................................... 67
Figure 43: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 68
Figure 44: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2 .............................................................................. 68
Figure 45: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2 ................................................................. 69
Figure 46: Data Input (WRITE) Timing ........................................................................................................... 70
Figure 47: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 70
Figure 48: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 71
Figure 49: Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2 ............................................................................ 71
Figure 50: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2 ................................................................ 72
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Figure 51: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 73
Figure 52: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 74
Figure 53: Data Mask Timing ......................................................................................................................... 74
Figure 54: Write Data Mask – Second Data Bit Masked .................................................................................... 75
Figure 55: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 ................................ 76
Figure 56: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 ................................ 77
Figure 57: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 78
Figure 58: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 ........................................ 79
Figure 59: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 80
Figure 60: Regular Distributed Refresh Pattern ............................................................................................... 84
Figure 61: Supported Transition from Repetitive REFRESH Burst .................................................................... 85
Figure 62: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 86
Figure 63: Recommended Self Refresh Entry and Exit ..................................................................................... 87
Figure 64: tSRF Definition .............................................................................................................................. 88
Figure 65: All-Bank REFRESH Operation ........................................................................................................ 88
Figure 66: Per-Bank REFRESH Operation ....................................................................................................... 89
Figure 67: SELF REFRESH Operation .............................................................................................................. 90
Figure 68: MRR Timing – RL = 3, tMRR = 2 ...................................................................................................... 92
Figure 69: READ to MRR Timing – RL = 3, tMRR = 2 ......................................................................................... 93
Figure 70: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 94
Figure 71: Temperature Sensor Timing ........................................................................................................... 96
Figure 72: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2 ............................................................. 97
Figure 73: MODE REGISTER WRITE Timing – RL = 3, tMRW = 5 ....................................................................... 98
Figure 74: ZQ Timings .................................................................................................................................. 100
Figure 75: Power-Down Entry and Exit Timing ............................................................................................... 102
Figure 76: CKE Intensive Environment .......................................................................................................... 102
Figure 77: REFRESH-to-REFRESH Timing in CKE Intensive Environments ..................................................... 102
Figure 78: READ to Power-Down Entry .......................................................................................................... 103
Figure 79: READ with Auto Precharge to Power-Down Entry ........................................................................... 104
Figure 80: WRITE to Power-Down Entry ........................................................................................................ 105
Figure 81: WRITE with Auto Precharge to Power-Down Entry ......................................................................... 106
Figure 82: REFRESH Command to Power-Down Entry ................................................................................... 107
Figure 83: ACTIVATE Command to Power-Down Entry .................................................................................. 107
Figure 84: PRECHARGE Command to Power-Down Entry .............................................................................. 107
Figure 85: MRR Command to Power-Down Entry .......................................................................................... 108
Figure 86: MRW Command to Power-Down Entry ......................................................................................... 108
Figure 87: Deep Power-Down Entry and Exit Timing ...................................................................................... 109
Figure 88: Simplified Bus Interface State Diagram .......................................................................................... 111
Figure 89: VREF DC Tolerance and VREF AC Noise Limits ................................................................................. 128
Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal ................................................................................... 129
Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal ..................................................................................... 130
Figure 92: Differential AC Swing Time and tDVAC .......................................................................................... 131
Figure 93: Single-Ended Requirements for Differential Signals ....................................................................... 133
Figure 94: VIX Definition ............................................................................................................................... 134
Figure 95: Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS# ............................................... 135
Figure 96: Single-Ended Output Slew Rate Definition ..................................................................................... 136
Figure 97: Differential Output Slew Rate Definition ........................................................................................ 138
Figure 98: Overshoot and Undershoot Definition ........................................................................................... 139
Figure 99: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 140
Figure 100: Output Driver ............................................................................................................................. 141
Figure 101: Output Impedance = 240 Ohms, I-V Curves After ZQRESET .......................................................... 144
Figure 102: Output Impedance = 240 Ohms, I-V Curves After Calibration ........................................................ 145
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Figure 103: Command Input Setup and Hold Timing ..................................................................................... 157
Figure 104: Typical Slew Rate and tVAC – tIS for CA and CS# Relative to Clock .................................................. 160
Figure 105: Typical Slew Rate – tIH for CA and CS# Relative to Clock ............................................................... 161
Figure 106: Tangent Line – tIS for CA and CS# Relative to Clock ...................................................................... 162
Figure 107: Tangent Line – tIH for CA and CS# Relative to Clock ..................................................................... 163
Figure 108: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe ........................................................... 167
Figure 109: Typical Slew Rate – tDH for DQ Relative to Strobe ......................................................................... 168
Figure 110: Tangent Line – tDS for DQ with Respect to Strobe ......................................................................... 169
Figure 111: Tangent Line – tDH for DQ with Respect to Strobe ........................................................................ 170
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Single Channel S4 Configuration Addressing ........................................................................................ 2
Table 3: Dual Channel S4 Configuration Addressing .......................................................................................... 2
Table 4: Package Codes and Descriptions ......................................................................................................... 3
Table 5: 256 Meg x 16 IDD Specifications ......................................................................................................... 13
Table 6: 128 Meg x 32 IDD Specifications ......................................................................................................... 14
Table 7: IDD6 Partial-Array Self Refresh Current ............................................................................................... 16
Table 8: Ball/Pad Descriptions ....................................................................................................................... 45
Table 9: Initialization Timing Parameters ....................................................................................................... 49
Table 10: Power-Off Timing ............................................................................................................................ 50
Table 11: Mode Register Assignments ............................................................................................................. 51
Table 12: MR0 Device Information (MA[7:0] = 00h) ......................................................................................... 52
Table 13: MR0 Op-Code Bit Definitions .......................................................................................................... 52
Table 14: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 52
Table 15: MR1 Op-Code Bit Definitions .......................................................................................................... 53
Table 16: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) ................................. 53
Table 17: No-Wrap Restrictions ...................................................................................................................... 54
Table 18: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 54
Table 19: MR2 Op-Code Bit Definitions .......................................................................................................... 55
Table 20: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 55
Table 21: MR3 Op-Code Bit Definitions .......................................................................................................... 55
Table 22: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 55
Table 23: MR4 Op-Code Bit Definitions .......................................................................................................... 56
Table 24: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 56
Table 25: MR5 Op-Code Bit Definitions .......................................................................................................... 56
Table 26: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 57
Table 27: MR6 Op-Code Bit Definitions .......................................................................................................... 57
Table 28: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 57
Table 29: MR7 Op-Code Bit Definitions .......................................................................................................... 57
Table 30: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 57
Table 31: MR8 Op-Code Bit Definitions .......................................................................................................... 57
Table 32: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 58
Table 33: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 58
Table 34: MR10 Op-Code Bit Definitions ........................................................................................................ 58
Table 35: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh) ......................................................................................... 59
Table 36: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 59
Table 37: MR16 Op-Code Bit Definitions ........................................................................................................ 59
Table 38: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 59
Table 39: MR17 PASR Segment Mask Definitions ............................................................................................ 59
Table 40: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 59
Table 41: Reserved Mode Registers ................................................................................................................. 60
Table 42: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 60
Table 43: Bank Selection for PRECHARGE by Address Bits ............................................................................... 76
Table 44: PRECHARGE and Auto Precharge Clarification ................................................................................. 80
Table 45: REFRESH Command Scheduling Separation Requirements .............................................................. 82
Table 46: Bank and Segment Masking Example ............................................................................................... 91
Table 47: Temperature Sensor Definitions and Operating Conditions .............................................................. 95
Table 48: Data Calibration Pattern Description ............................................................................................... 97
Table 49: Truth Table for MRR and MRW ........................................................................................................ 98
Table 50: Command Truth Table ................................................................................................................... 112
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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Table 51: CKE Truth Table ............................................................................................................................. 113
Table 52: Current State Bank n to Command to Bank n Truth Table ................................................................ 114
Table 53: Current State Bank n to Command to Bank m Truth Table ............................................................... 116
Table 54: DM Truth Table .............................................................................................................................. 119
Table 55: Absolute Maximum DC Ratings ...................................................................................................... 120
Table 56: Input/Output Capacitance ............................................................................................................. 120
Table 57: Switching for CA Input Signals ........................................................................................................ 121
Table 58: Switching for IDD4R ......................................................................................................................... 122
Table 59: Switching for IDD4W ........................................................................................................................ 122
Table 60: IDD Specification Parameters and Operating Conditions .................................................................. 123
Table 61: Recommended DC Operating Conditions ....................................................................................... 125
Table 62: Input Leakage Current ................................................................................................................... 126
Table 63: Operating Temperature Range ........................................................................................................ 126
Table 64: Single-Ended AC and DC Input Levels for CA and CS# Inputs ........................................................... 127
Table 65: Single-Ended AC and DC Input Levels for CKE ................................................................................ 127
Table 66: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 127
Table 67: Differential AC and DC Input Levels ................................................................................................ 131
Table 68: CK/CK# and DQS/DQS# Time Requirements Before Ringback (tDVAC) ............................................ 132
Table 69: Single-Ended Levels for CK, CK#, DQS, DQS# .................................................................................. 133
Table 70: Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#) ........................................... 134
Table 71: Differential Input Slew Rate Definition ............................................................................................ 135
Table 72: Single-Ended AC and DC Output Levels .......................................................................................... 135
Table 73: Differential AC and DC Output Levels ............................................................................................. 136
Table 74: Single-Ended Output Slew Rate Definition ...................................................................................... 136
Table 75: Single-Ended Output Slew Rate ...................................................................................................... 136
Table 76: Differential Output Slew Rate Definition ......................................................................................... 137
Table 77: Differential Output Slew Rate ......................................................................................................... 138
Table 78: AC Overshoot/Undershoot Specification ......................................................................................... 138
Table 79: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 141
Table 80: Output Driver Sensitivity Definition ................................................................................................ 142
Table 81: Output Driver Temperature and Voltage Sensitivity ......................................................................... 142
Table 82: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 142
Table 83: I-V Curves ..................................................................................................................................... 143
Table 84: Definitions and Calculations .......................................................................................................... 146
Table 85: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 147
Table 86: Refresh Requirement Parameters (Per Density) ............................................................................... 150
Table 87: AC Timing ..................................................................................................................................... 151
Table 88: CA and CS# Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ............................................ 158
Table 89: CA and CS# Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ............................................ 158
Table 90: Derating Values for AC/DC-Based tIS/tIH (AC220) ........................................................................... 159
Table 91: Derating Values for AC/DC-Based tIS/tIH (AC300) ........................................................................... 159
Table 92: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC) ....................................................... 159
Table 93: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ....................................................... 164
Table 94: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ....................................................... 165
Table 95: Derating Values for AC/DC-Based tDS/tDH (AC220) ........................................................................ 165
Table 96: Derating Values for AC/DC-Based tDS/tDH (AC300) ........................................................................ 166
Table 97: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC) ......................................................... 166
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
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General Description
The 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic
random-access memory containing 4,294,967,296-bits. The LPDDR2-S4 device is inter-
nally configured as an eight-bank DRAM. Each of the x16’s 536,870,912-bit banks is or-
ganized as 16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit
banks is organized as 16,384 rows by 1024 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter-
preted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS, DQS# and CK, CK# respectively, unless
specifically stated otherwise. “BA” includes all BA pins used for a given density.
In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[9:0].
VREF indicates VREFCA and VREFDQ.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
General Description
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IDD Specifications
Table 5: 256 Meg x 16 IDD Specifications
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Parameter Supply
Speed Grade
Unit-18 -25 -3
IDD01 VDD1 15 15 15 mA
IDD02 VDD2 70 70 70
IDD0,in VDDCA + VDDQ 766
IDD2P1 VDD1 600 600 600 μA
IDD2P2 VDD2 800 800 800
IDD2P,in VDDCA + VDDQ 50 50 50
IDD2PS1 VDD1 600 600 600 μA
IDD2PS2 VDD2 800 800 800
IDD2PS,in VDDCA + VDDQ 50 50 50
IDD2N1 VDD1 222mA
IDD2N2 VDD2 30 30 30
IDD2N,in VDDCA + VDDQ 766
IDD2NS1 VDD1 1.7 1.7 1.7 mA
IDD2NS2 VDD2 27 27 27
IDD2NS,in VDDCA + VDDQ 666
IDD3P1 VDD1 1200 1200 1200 μA
IDD3P2 VDD2 888mA
IDD3P,in VDDCA + VDDQ 150 150 150 μA
IDD3PS1 VDD1 1200 1200 1200 μA
IDD3PS2 VDD2 888mA
IDD3PS,in VDDCA + VDDQ 150 150 150 μA
IDD3N1 VDD1 2.5 2.5 2.5 mA
IDD3N2 VDD2 30 30 30
IDD3N,in VDDCA + VDDQ 766
IDD3NS1 VDD1 222mA
IDD3NS2 VDD2 27 27 27
IDD3NS,in VDDCA + VDDQ 666
IDD4R1 VDD1 333mA
IDD4R2 VDD2 220 194 178
IDD4R,in VDDCA 666
IDD4W1 VDD1 10 10 10 mA
IDD4W2 VDD2 190 185 170
IDD4W,in VDDCA + VDDQ 25 25 25
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
IDD Specifications
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Table 5: 256 Meg x 16 IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Parameter Supply
Speed Grade
Unit-18 -25 -3
IDD51 VDD1 40 40 40 mA
IDD52 VDD2 150 150 150
IDD5,in VDDCA + VDDQ 866
IDD5PB1 VDD1 555mA
IDD5PB2 VDD2 50 50 50
IDD5PB,in VDDCA + VDDQ 888
IDD5PBET1 VDD1 10.5 10.5 10.5 mA
IDD5PBET2 VDD2 80 80 80
IDD5PB,ETin VDDCA + VDDQ 888
IDD5AB1 VDD1 555mA
IDD5AB2 VDD2 50 50 50
IDD5AB,in VDDCA + VDDQ 888
IDD5ABET1 VDD1 10.5 10.5 10.5 mA
IDD5ABET2 VDD2 80 80 80
IDD5AB,ETin VDDCA + VDDQ 888
IDD61 VDD1 1000 1000 1000 μA
IDD62 VDD2 3200 3200 3200
IDD6,in VDDCA + VDDQ 50 50 50
IDD6ET1 VDD1 3100 3100 3100 μA
IDD6ET2 VDD2 13.7 13.7 13.7 mA
IDD6,ETin VDDCA + VDDQ 90 90 90 μA
IDD81 VDD1 25 25 25 μA
IDD82 VDD2 100 100 100
IDD8,in VDDCA + VDDQ 100 100 100
Table 6: 128 Meg x 32 IDD Specifications
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Parameter Supply
Speed Grade
Unit-18 -25 -3
IDD01 VDD1 15 15 15
mAIDD02 VDD2 70 70 70
IDD0,in VDDCA + VDDQ 766
IDD2P1 VDD1 600 600 600
μAIDD2P2 VDD2 800 800 800
IDD2P,in VDDCA + VDDQ 50 50 50
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
IDD Specifications
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Table 6: 128 Meg x 32 IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Parameter Supply
Speed Grade
Unit-18 -25 -3
IDD2PS1 VDD1 600 600 600
μAIDD2PS2 VDD2 800 800 800
IDD2PS,in VDDCA + VDDQ 50 50 50
IDD2N1 VDD1 222mA
IDD2N2 VDD2 30 30 30 mA
IDD2N,in VDDCA + VDDQ 766
IDD2NS1 VDD1 1.7 1.7 1.7
mAIDD2NS2 VDD2 27 27 27
IDD2NS,in VDDCA + VDDQ 666
IDD3P1 VDD1 1200 1200 1200 μA
IDD3P2 VDD2 888mA
IDD3P,in VDDCA + VDDQ 150 150 150 μA
IDD3PS1 VDD1 1200 1200 1200 μA
IDD3PS2 VDD2 888mA
IDD3PS,in VDDCA + VDDQ 150 150 150 μA
IDD3N1 VDD1 2.5 2.5 2.5 mA
IDD3N2 VDD2 30 30 30 mA
IDD3N,in VDDCA + VDDQ 766
IDD3NS1 VDD1 222
mAIDD3NS2 VDD2 27 27 27
IDD3NS,in VDDCA + VDDQ 666
IDD4R1 VDD1 333
mAIDD4R2 VDD2 220 194 178
IDD4R,in VDDCA 666
IDD4W1 VDD1 10 10 10
mAIDD4W2 VDD2 190 185 170
IDD4W,in VDDCA + VDDQ 25 25 25
IDD51 VDD1 40 40 40
mAIDD52 VDD2 150 150 150
IDD5,in VDDCA + VDDQ 866
IDD5PB1 VDD1 555
mAIDD5PB2 VDD2 50 50 50
IDD5PB,in VDDCA + VDDQ 888
IDD5PBET1 VDD1 10.5 10.5 10.5
mAIDD5PBET2 VDD2 80 80 80
IDD5PB,ETin VDDCA + VDDQ 888
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
IDD Specifications
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Table 6: 128 Meg x 32 IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Parameter Supply
Speed Grade
Unit-18 -25 -3
IDDAB1 VDD1 555
mAIDD5AB2 VDD2 50 50 50
IDD5AB,in VDDCA + VDDQ 888
IDDABET1 VDD1 10.5 10.5 10.5
mAIDD5ABET2 VDD2 80 80 80
IDD5AB,ETin VDDCA + VDDQ 888
IDD61 VDD1 1000 1000 1000
μAIDD62 VDD2 3200 3200 3200
IDD6,in VDDCA + VDDQ 50 50 50
IDD6ET1 VDD1 3100 3100 3100 μA
IDD6ET2 VDD2 13.7 13.7 13.7 mA
IDD6,ETin VDDCA + VDDQ 90 90 90 μA
IDD81 VDD1 25 25 25
μAIDD82 VDD2 100 100 100
IDD8,in VDDCA + VDDQ 100 100 100
Table 7: IDD6 Partial-Array Self Refresh Current
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR Supply Value (–30˚C to +85˚C) Value (+85˚C to +105˚C) Unit
Full array VDD1 1000 3100 μA
VDD2 3.2 13.7 mA
VDDi 50 90 μA
1/2 array VDD1 950 2200
VDD2 2700 7300
VDDi 50 90
1/4 array VDD1 900 1600
VDD2 2400 4300
VDDi 50 90
1/8 array VDD1 850 1300
VDD2 2000 2800
VDDi 50 90
Note: 1. LPDDR2-S4 SDRAM devices support both bank masking and segment masking. IDD6 PASR
currents are measured using bank masking only.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
IDD Specifications
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Figure 2: VDD1Typical Self Refresh Current vs. Temperature
0
200
400
600
800
1000
1200
1400
1600
1800
2000
-40 -20 0 25 35 45 65 80 85 95 110
IDD6 1/8 VDD1 (μa)
IDD6 1/4 VDD1 (μa)
IDD6 1/2 VDD1 (μa)
IDD6 Full VDD1 (μa)
Figure 3: VDD2 Typical Self Refresh Current vs. Temperature
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
-40 -20 0 25 35 45 65 80 85 95 110
IDD6 1/8 VDD2 (μa)
IDD6 1/4 VDD2 (μa)
IDD6 1/2 VDD2 (μa)
IDD6 Full VDD2 (μa)
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
IDD Specifications
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Package Block Diagrams
Figure 4: Single Rank, Single Channel Package Block Diagram
LPDDR2
Die 0
CS0#
CKE0
CK
CK#
DM
CA[9:0]
DQ, DQS
ZQ
RZQ
VDD1
VDD2
VDDQ
VDDCA
VSS
VREFDQ
VREFCA
Figure 5: Dual Rank, Single Channel Package Block Diagram
LPDDR2
Die 0
LPDDR2
Die 1
CS1#
CKE1
CS0#
CKE0
CK
CK#
DM
CA[9:0]
DQ[31:0], DQS
ZQ0
RZQ
VDD1
VDD2
VDDQ
VDDCA
VSS
VREFDQ
VREFCA
Note: 1. For the 168-ball JEDEC PoP ballout employing only a single ZQ connection, the RZQ re-
sistor is connected to ZQ.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram
DQ[31:0],
DQS[3:0]/DQS[3:0]#
CKE1
CS1#
LPDDR2
Die 1
LPDDR2
Die 2
LPDDR2
Die 0
x32
VDD1 VDD2 VDDQVDDCA VSS
CS0#
CKE0
CK
CK#
DM
CA[9:0]
RZQ1
ZQ1
ZQ0
RZQ0
VREFDQ
VREFCA
x16 x16
DQ[15:0] DQ[31:16]
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Figure 7: Single Rank, Dual Channel Package Block Diagram
DQ[31:0], DQS
CKE0
CS0#
LPDDR2
Die 1
LPDDR2
Die 0
CS0#
CKE0
CK#
CK
DM
CA[9:0]
CA[9:0]
DM
CK
CK#
DQ[31:0], DQS
ZQ0
RZQ
ZQ0
RZQ
V
DD1
VDDQ
VDDCA
VSS
VREFDQ(b)
VREFCA(b)
Channel B
Channel A
VREFDQ(a)
VREFCA(a)
V
DD2
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Figure 8: Dual Rank, Dual Channel Package Block Diagram
DQ[31:0], DQS
CKE0
CS0#
LPDDR2
Die 2
LPDDR2
Die 3
LPDDR2
Die 0
LPDDR2
Die 1
CS1#
CKE1
CS0#
CKE0
CK
CK#
DM
CA[9:0]
CA[9:0]
DM
CK
CK#
DQ[31:0], DQS
ZQ0
RZQ
ZQ0
RZQ
VDD1
VDD2
VDDQ
VDDCA
VSS
VREFDQ(b)
VREFCA(b)
VREFDQ(a)
VREFCA(a)
Channel B
Channel A
CKE1
CS1#
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Figure 9: Dual Rank, Dual Channel (3 Die) Package Block Diagram
DQ[31:0], DQS
CKE0
CS0#
LPDDR2
Die 2
LPDDR2
Die 0
LPDDR2
Die 1
CS1#
CKE1
CS0#
CKE0
CK
CK#
DM
CA[9:0]
CA[9:0]
DM
CK
CK#
DQ[31:0], DQS
ZQ0
RZQ0
ZQ0
RZQ0
VDD1
VDD2
VDDQ
VDDCA
VSS
VREFDQ(a)
VREFCA(a)
VREFDQ(b)
VREFCA(b)
Channel B
Channel A
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram
DQ[15:0], DQS0/DQS0#, DQS1/DQS1#
CKE1
CS1#
LPDDR2
Die 2
LPDDR2
Die 3
LPDDR2
Die 0
LPDDR2
Die 1
VDD1
VDD2
VDDQ
VDDCA
VSS
CS0#
CKE0
CK
CK#
DM
CA[9:0]
DQ[31:16], DQS2/DQS2#, DQS3/DQS3#
RZQ1
ZQ1
ZQ0
RZQ0
VREFDQ
VREFCA
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Block Diagrams
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Package Dimensions
Figure 11: 134-Ball FBGA – 10mm x 11.5mm Single-Die (Package Code GU)
Seating plane
0.08 A
Ball A1 ID
(covered by SR)
11.5 ±0.1
10 ±0.1
10.4 CTR
5.85 CTR
Ball A1 ID
0.6 ±0.1
0.22 MIN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
12345678910
134X Ø0.36
Dimensions apply
to solder balls post-
reflow on Ø0.30 SMD
OSP ball pads.
0.65 TYP 0.65 TYP
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
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Figure 12: 134-Ball FBGA – 10mm x 11.5mm Dual-Die (Package Code GV)
Seating plane
0.08 A
Ball A1 ID
(covered by SR)
11.5 ±0.1
10 ±0.1
10.4 CTR
5.85 CTR
Ball A1 ID
0.75 ±0.1
0.22 MIN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
12345678910
134X Ø0.36
Dimensions apply
to solder balls post-
reflow on Ø0.30
SMD OSP ball pads.
0.65 TYP 0.65 TYP
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
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Figure 13: 168-Ball FBGA – 12mm x 12mm Single-Die (Package Code LF)
Seating plane
0.08 A
Ball A1 ID
0.237 MIN
0.65 ±0.1
11 CTR
12 ±0.1
0.5 TYP
11 CTR
12 ±0.1
0.5 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
23 21 19 17 15 13 11 9 7 5 3 1
22 20 18 16 14 12 10 8 6 4 2
Ball A1 ID
168X Ø0.355
Dimensions apply
to solder balls post-
reflow on Ø0.28 SMD
ball pads.
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 14: 168-Ball FBGA – 12mm x 12mm Dual-Die (Package Code LG)
Seating plane
0.08 A
Ball A1 ID
0.24 MIN
0.7 ±0.1
11 CTR
12 ±0.1
0.5 TYP
11 CTR
12 ±0.1
0.5 TYP
Ball A1 ID
168X Ø0.355
Dimensions
apply to solder
balls post-reflow
on Ø0.28 SMD
ball pads.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
23 21 19 17 15 13 11 9 7 5 3 1
22 20 18 16 14 12 10 8 6 4 2
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 15: 216-Ball FBGA – 12mm x 12mm (Package Codes LK, LL)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Seating plane
0.08 A
Ball A1 ID
0.13 MIN
0.7 ±0.1
11.2 CTR
12 ±0.1
0.4 TYP
11.2 CTR
12 ±0.1
0.4 TYP
Ball A1 ID
(covered by SR)
216X Ø0.27
Dimensions
apply to solder
balls post-reflow
on Ø0.24 SMD
ball pads. 1
246810121416182022242628 357911131517192123252729
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 16: 216-Ball FBGA – 12mm x 12mm (Package Code LM)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Seating plane
0.08 A
Ball A1 ID
0.13 MIN
0.9 ±0.1
11.2 CTR
12 ±0.1
0.4 TYP
11.2 CTR
12 ±0.1
0.4 TYP
Ball A1 ID
(covered by SR)
216X Ø0.27
Dimensions
apply to solder
balls post-reflow
on Ø0.24 SMD
ball pads. 1
246810121416182022242628 357911131517192123252729
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 17: 216-Ball FBGA – 12mm x 12mm (Package Code LH)
Seating plane
0.08 A
Ball A1 index
0.13 MIN
0.55 ±0.1
11.2 CTR
12 ±0.1
0.4 TYP
11.2 CTR
12 ±0.1
0.4 TYP
1
Ball A1 index
216X Ø0.27
Dimensions
apply to solder
balls post-reflow
on Ø0.24 SMD
ball pads.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
246810121416182022242628 357911131517192123252729
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 18: 216-Ball FBGA – 12mm x 12mm (Package Code LP)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Seating plane
0.08 A
A
Ball A1 ID
0.132 MIN
0.72 ±0.1
11.2 CTR
12 ±0.1
0.4 TYP
11.2 CTR
12 ±0.1
0.4 TYP
Ball A1 ID
216X Ø0.261
Dimensions
apply to solder
balls post-reflow
on Ø0.24 SMD
ball pads. 1
246810121416182022242628 357911131517192123252729
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 19: 220-Ball FBGA – 14mm x 14mm Dual-Die (Package Code MP)
Seating plane
0.08 A
Ball A1 ID
0.215 MIN
0.7 ±0.1
13.0 CTR
14 ±0.1
0.5 TYP
13.0 CTR
14 ±0.1
0.5 TYP
220X Ø0.34
Dimensions
apply to solder
balls post-reflow
on Ø0.27 SMD
ball pads.
Ball A1 ID
(covered by SR)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
13 11 9 7 5 3 1
14 12 10 8 6 4 2
15
16
17
18
19
20
21
22
23
24
25
26
27
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 20: 220-Ball FBGA – 14mm x 14mm Quad-Die (Package Code LD)
Seating plane
0.08 A
Ball A1 ID
0.215 MIN
0.9 ±0.1
13.0 CTR
14 ±0.1
0.5 TYP
13.0 CTR
14 ±0.1
0.5 TYP
220X Ø0.34
Dimensions
apply to solder
balls post-reflow
on Ø0.27 SMD
ball pads.
Ball A1 ID
(covered by SR)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
13 11 9 7 5 3 1
14 12 10 8 6 4 2
15
16
17
18
19
20
21
22
23
24
25
26
27
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 21: 240-Ball FBGA – 14mm x 14mm Dual-Die (Package Code MC)
Pin A1 index
Seating
plane
0.08 A
A
0.7 ±0.1
Pin A1 index
(covered by SR)
0.5 TYP
0.5 TYP
13.0 CTR
Dimensions apply
to solder balls
post-reflow on
Ø0.27 SMD OSP
ball pads.
240X Ø0.34
14 ±0.1
0.215 MIN
13.0
CTR
14 ±0.1
27 25 23 21 19 17 15 13 11
9 7 5 3 1
26 24 22 20 18 16 14 12 1
0 8 6 4 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 22: 253-Ball FBGA – 11mm x 11mm Dual-Die (Package Code EU)
Seating plane
0.08 A
Ball A1 ID
(covered by SR)
11 ±0.1
11 ±0.1
8 CTR
8 CTR
Ball A1 ID
0.8 ±0.1
0.18 MIN
1
253X Ø0.309
Dimensions apply
to solder balls post-
reflow on Ø0.27
SMD OSP ball pads.
0.5 TYP 0.5 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 23: 253-Ball FBGA – 11mm x 11mm Quad-Die (Package Code EV)
Seating plane
0.08 A
Ball A1 ID
(covered by SR)
11 ±0.1
11 ±0.1
8 CTR
8 CTR
Ball A1 ID
1.1 ±0.1
0.18 MIN
253X Ø0.31
Dimensions
apply to solder
balls post-reflow
on Ø0.27 SMD OSP
ball pads.
0.5 TYP 0.5 TYP
A
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note: 1. All dimensions are in millimeters.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Package Dimensions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Ball Assignments and Descriptions
Figure 24: 134-Ball FBGA (x16)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View (ball down)
1
DNU
DNU
VDD1
VSS
VSSCA
VDDCA
VDD2
VDDCA
VSSCA
CKE0
CS0#
CA4
VSSCA
VSS
VDD1
DNU
DNU
1
2
DNU
NC
VSS
VDD2
CA9
CA6
CA5
VSS
NC
CKE1
CS1#
CA3
VDDCA
VDD2
VSS
NC
DNU
2
4
4
3
NC
ZQ1
ZQ0
CA8
CA7
VREFCA
CK#
CK
RFU
RFU
CA2
CA1
CA0
NC
NC
3
5
VDD2
VSS
VDDQ
RFU
VSSQ
DQS1#
DM1
VSSQ
DM0
DQS0#
VSSQ
RFU
VDDQ
VSS
VDD2
5
6
VDD1
VSSQ
RFU
RFU
DQ11
DQS1
VDDQ
VDDQ
VDDQ
DQS0
DQ4
RFU
RFU
VSSQ
VDD1
6
7
RFU
VDDQ
RFU
RFU
DQ13
DQ10
VDD2
DQ5
DQ2
RFU
RFU
VDDQ
RFU
7
8
RFU
RFU
RFU
DQ15
DQ14
DQ9
VSS
DQ6
DQ1
DQ0
RFU
RFU
RFU
8
9
DNU
RFU
VSSQ
RFU
VDDQ
DQ12
DQ8
VREFDQ
DQ7
DQ3
VDDQ
RFU
VSSQ
RFU
DNU
9
10
DNU
DNU
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
DNU
DNU
10
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 25: 134-Ball FBGA (x32)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View (ball down)
1
DNU
DNU
VDD1
VSS
VSSCA
VDDCA
VDD2
VDDCA
VSSCA
CKE0
CS0#
CA4
VSSCA
VSS
VDD1
DNU
DNU
1
2
DNU
NC
VSS
VDD2
CA9
CA6
CA5
VSS
NC
CKE1
CS1#
CA3
VDDCA
VDD2
VSS
NC
DNU
2
4
4
3
NC
ZQ1
ZQ0
CA8
CA7
VREFCA
CK#
CK
RFU
RFU
CA2
CA1
CA0
NC
NC
3
5
VDD2
VSS
VDDQ
DQ28
VSSQ
DQS1#
DM1
VSSQ
DM0
DQS0#
VSSQ
DQ19
VDDQ
VSS
VDD2
5
6
VDD1
VSSQ
DQ30
DQ24
DQ11
DQS1
VDDQ
VDDQ
VDDQ
DQS0
DQ4
DQ23
DQ17
VSSQ
VDD1
6
7
DQ31
VDDQ
DQ27
DM3
DQ13
DQ10
VDD2
DQ5
DQ2
DM2
DQ20
VDDQ
DQ16
7
8
DQ29
DQ25
DQS3
DQ15
DQ14
DQ9
VSS
DQ6
DQ1
DQ0
DQS2
DQ22
DQ18
8
9
DNU
DQ26
VSSQ
DQS3#
VDDQ
DQ12
DQ8
VREFDQ
DQ7
DQ3
VDDQ
DQS2#
VSSQ
DQ21
DNU
9
10
DNU
DNU
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VSSQ
VDDQ
DNU
DNU
10
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 26: 168-Ball FBGA – 12mm x 12mm
Notes: 1. Ball AC9 may be VSS or left unconnected.
2. Balls labeled NC = no connect; however, they can be connected together internally.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 27: 216-Ball 2-Channel FBGA – 12mm x 12mm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Top View (ball down)
1
DNU
VSSQ
VDD1
DQ17
DQ18
VSSQ
DQ21
DQ22
VSSQ
DQS#2
DM2
DQ1
DQ2
VSS
VDD1
VDD2
VDDQ
DQ4
DQ6
VDDQ
DQS0
DM0
VDDQ
DQS# 1
DQ8
DQ9
DQ10
VSSQ
DNU
1
2
VSS
NC
DQ16
VDDQ
DQ19
DQ20
VDDQ
DQ23
VDDQ
DQS2
DQ0
VSSQ
VDD1
VSS
VREFDQ
VDD2
DQ3
VSSQ
DQ5
DQ7
DQS#0
VSSQ
DM1
DQS1
VSSQ
VDDQ
DQ11
VDD1
VSS
2
4
DQ30
VDDQ
DQ13
VDDQ
4
3
VDD2
DQ31
VDD2
DQ12
3
5
DQ29
DQ28
VSSQ
DQ14
5
6
VSSQ
DQ27
DQ15
VDDQ
6
7
DQ26
VDDQ
DM3
VSSQ
7
8
DQ25
DQ24
DQS3
DQS#3
8
9
VSSQ
VDDQ
VDDQ
DQ24
9
11
VSSQ
DM3
DQ27
VSSQ
11
13
DQ13
VDDQ
DQ30
DQ29
13
14
VSS
VSSQ
VSSQ
DQ31
14
15
VDD1
VREFDQ
VDD2
VDD1
15
16
VDD2
VDD2
VREFCA
VSS
16
29
DNU
VSSQ
VDD2
VDDQ
DQ0
VDDQ
DQS#2
DQ23
DQ22
DQ21
VSSQ
DQ18
DQ17
VDD1
CA0
CA1
CA2
CA3
CS1#
CKE1
CKE0
CK#
CA5
CA6
VDDCA
CA9
ZQ
VSSCA
DNU
29
10
DQS#3
DQS3
DQ26
DQ25
10
12
DQ14
DQ15
VDDQ
DQ28
12
18
DQ10
VDDQ
VSSCA
CA8
18
19
DQ9
DQ8
CA7
VDDCA
19
20
DQS1
DQS#1
CA6
CA5
20
21
DM1
VSSQ
CK#
CK
21
17
DQ11
DQ12
CA9
ZQ
17
22
VDDQ
DM0
VDDCA
VSSCA
22
23
DQS0
DQS#0
CKE0
CKE1
23
24
DQ7
VSSQ
CS0#
CS1#
24
25
DQ6
VDDQ
CA3
CA4
25
26
DQ4
DQ5
CA2
VDDCA
26
27
DQ3
DQ2
CA1
CA0
27
28
VSS
NC
VDD1
DQ1
VSSQ
DM2
DQS2
VSSQ
VDDQ
DQ20
DQ19
VDDQ
DQ16
VDD2
VSS
VDDCA
VREFCA
VSSCA
CA4
CS0#
VSSCA
CK
VDDCA
CA7
CA8
VSSCA
VDD2
VDD1
VSS
28
GroundSupplyChannel BChannel A
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 28: 216-Ball 1-Channel (B) FBGA – 12mm x 12mm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Top View (ball down)
1
DNU
VSSQ
VDD1
DQ17
DQ18
VSSQ
DQ21
DQ22
VSSQ
DQS#2
DM2
DQ1
DQ2
VSS
VDD1
VDD2
VDDQ
DQ4
DQ6
VDDQ
DQS0
DM0
VDDQ
DQS# 1
DQ8
DQ9
DQ10
VSSQ
DNU
1
2
VSS
NC
DQ16
VDDQ
DQ19
DQ20
VDDQ
DQ23
VDDQ
DQS2
DQ0
VSSQ
VDD1
VSS
V
REFDQ
VDD2
DQ3
VSSQ
DQ5
DQ7
DQS#0
VSSQ
DM1
DQS1
VSSQ
VDDQ
DQ11
VDD1
VSS
2
4
NC
NC
DQ13
VDDQ
4
3
VDD2
NC
VDD2
DQ12
3
5
NC
NC
VSSQ
DQ14
5
7
NC
NC
DM3
VSSQ
7
8
NC
NC
DQS3
DQS#3
8
9
NC
NC
VDDQ
DQ24
9
11
NC
NC
DQ27
VSSQ
11
13
NC
NC
DQ30
DQ29
13
14
NC
NC
VSSQ
DQ31
14
15
NC
NC
VDD2
VDD1
15
16
NC
NC
NC
VSS
16
29
DNU
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD1
CA0
CA1
CA2
CA3
CS1#
CKE1
CKE0
CK#
CA5
CA6
V
DDCA
CA9
ZQ0
V
SSCA
DNU
29
10
NC
NC
DQ26
DQ25
10
12
NC
NC
VDDQ
DQ28
12
18
NC
NC
NC
NC
18
19
NC
NC
NC
NC
19
20
NC
NC
NC
NC
20
21
NC
NC
NC
NC
21 22
17
NC
NC
NC
ZQ1/
NC2
17
22
NC
NC
NC
NC
23
NC
NC
NC
NC
23
24
NC
NC
NC
NC
24
25
NC
NC
NC
NC
25
26
NC
NC
NC
NC
26
27
NC
NC
NC
NC
27
28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD2
VSS
V
DDCA
V
REFCA
V
SSCA
CA4
CS0#
V
SSCA
CK
V
DDCA
CA7
CA8
VSSCA
VDD2
VDD1
VSS
28
GroundSupplyChannel B
6
NC
NC
DQ15
VDDQ
6
Notes: 1. Package codes LP, LH and LK = Channel B only; Channel A not connected.
2. ZQ1 for 3DP; NC for all other configurations.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 29: 220-Ball 2-Channel FBGA – 14mm x 14mm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
Top View (Ball Down)
1
DNU
V
DD1
A-
DQ16
A-
DQ18
V
SSQ
A-
DQ21
V
SSQ
A-
DQS2
V
SSQ
A-
DQ1
V
SSQ
A-
DQ4
V
SSQ
A-
DQ7
V
SSQ
A-
DM0
V
SS
V
DD2
V
SS
A-
DQS1#
V
SSQ
A-
DQ8
V
SSQ
A-
DQ13
V
SSQ
V
SS
DNU
1
4
V
SSQ
B-
DQ31
A-
DQS3
V
DDQ
4
2
V
SS
NC
A-
DQ17
V
DDQ
A-
DQ20
V
DDQ
A-
DQ22
A-
DQS2#
A-
DM2
V
DDQ
A-
DQ2
V
DDQ
A-
DQ5
V
DDQ
A-
DQS0#
V
DDQ
V
SSQ
V
DD1
V
DD2
A-
DQS1
A-
DQ9
V
DDQ
A-
DQ11
A-
DQ14
A-
DQ15
V
DDQ
V
DD2
2
3
V
DD2
V
DDQ
A-
DQ19
A-
DQ23
A-
DQ0
A-
DQ3
A-
DQ6
A-
DQS0
A-
V
REF(DQ)
A-
DM1
A-
DQ10
A-
DQ12
A-
DM3
V
SSQ
3
5
B-
DQ29
B-
DQ30
A-
DQS3#
A-
DQ24
5
6
B-
DQ28
V
DDQ
A-
DQ25
A-
DQ26
6
7
V
SSQ
B-
DQ27
A-
DQ27
V
SSQ
7
8
B-
DQ25
B-
DQ26
V
DDQ
A-
DQ28
8
9
B-
DQ24
V
DDQ
A-
DQ29
A-
DQ30
9
11
B-
DM3
V
SSQ
V
DD2
V
SS
11
13
V
SSQ
B-
DQ14
V
DDCA
V
SSCA
13
14
B-
DQ13
B-
DQ12
B-CA9
B-CA8
14
15
B-
DQ11
V
DDQ
B-CA7
B-CA6
15
16
V
SSQ
B-
DQ10
V
DD2
B-CA5
16
27
DNU
V
DD2
B-DQ4
B-DQ3
V
SSQ
B-DQ0
V
SSQ
B-
DQ23
V
SSQ
B-
DQ20
V
SSQ
B-
DQ17
V
SS
A-CA0
V
SSCA
A-CA4
V
SS
A-
CKE1
V
SSCA
A-CA5
V
DD2
V
SS
V
SSCA
V
DD2
A-ZQ
V
SS
DNU
27
10
B-
DQS3#
B-
DQS3
A-
DQ31
V
SSQ
10
12
B-
DQ15
V
DDQ
V
DD1
B-ZQ
12
18
B-
DQS1#
B-
DQS1
V
DDCA
V
SSCA
18
19
B-
DM1
V
DDQ
B-CK
B-CK#
19
20
V
SSQ
B-
V
REF(DQ)
B-
CKE1
B-
CKE0
20
21
V
SS
V
DD1
B-
CS0#
B-
CS1#
21
17
B-
DQ9
B-
DQ8
B-
V
REF(CA)
V
SS
17
22
V
DD2
B-
DM0
B-
CA4
V
SSCA
22
23
B-
DQS0#
B-
DQS0
V
DDCA
B-CA3
23
24
B-
DQ7
V
DDQ
B-CA2
B-CA1
24
25
V
SSQ
B-
DQ6
B-
DQ2
B-
DM2
B-
DQ21
B-
DQ19
B-
DQ16
A-CA1
A-
CS0#
A-CK#
A-
V
REF(CA)
A-CA8
B-CA0
V
SS
25
26
V
SS
NC
B-
DQ5
V
DDQ
B-DQ1
V
DDQ
B-
DQS2
B-
DQS2#
B-
DQ22
V
DDQ
B-
DQ18
V
DD2
V
DDQ
V
DDCA
A-CA2
A-CA3
A-
CS1#
A-
CKE0
A-CK
V
DDCA
A-CA6
A-CA7
A-CA9
V
DDCA
V
DD1
V
DD2
V
DD1
26
GroundSupplyChannel BChannel A DRAMZQ
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 30: 240-Ball 2-Channel FBGA – 14mm x 14mm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
Top View (ball down)
1
DNU
VSSQ
VDD1
DQ17
DQ18
DQ20
VDDQ
VSSQ
DQS2#
VSSQ
DQ1
DQ3
DQ4
DQ6
VDDQ
VSSQ
VREFDQ
VDD1
DM1
VDDQ
DQS1#
VDDQ
DQ10
DQ13
VDD1
VSSQ
DNU
1
4
DQ31
DQ30
VDDQ
DM3
4
2
VSS
NC
DQ16
VDDQ
DQ19
DQ21
DQ22
DQS2
VDDQ
DQ0
VDDQ
VSSQ
DQ5
DQ7
DQS0
VSS
VSS
VDD1
VDD2
VSSQ
DQS1
DQ9
DQ11
DQ12
DQ14
VDDQ
VSS
2
3
VDD2
VSSQ
VSSQ
DQ23
DM2
DQ2
VDDQ
DQS0#
DM0
VDD2
DQ8
VSSQ
DQ15
VDD2
3
5
VDDQ
DQ29
DQ28
VSSQ
DQS3
DQS3#
5
6
VSSQ
DQ27
DQ25
DQ24
6
7
DQ26
VDDQ
DQ25
DQ27
DQ26
VDDQ
7
8
DQ24
VSSQ
DQ28
VSSQ
8
9
DQS3
DQS3#
VDDQ
DQ30
VDDQ
DQ29
9
11
DQ15
DQ14
VDDQ
VDD2
VSS
VDD1
11
13
VSSQ
DQ11
DQ10
CA6
CA7
CA8
13
14
VDDQ
DQ9
VDDCA
VSSCA
14
15
DQ8
DQS1#
DQS1
CA5
VSS
VREFCA
15
16
VSSQ
VDDQ
VDDCA
VSSCA
16
27
DNU
VSS
VDD2
DQS2#
DQ23
VDDQ
VSSQ
DQ18
DQ16
VDD2
VSS
VSSCA
VDDCA
CS1#
CKE1
CK
VSSCA
VREFCA
VSSCA
CA6
CA8
ZQ
VDD1
NC
NC
NC
DNU
27
10
DM3
VSSQ
VSSQ
DQ31
10
12
DQ13
DQ12
CA9
ZQ
12
18
VDD1
VDD2
CKE0
CKE1
18
19
VDDQ
DQS0#
DQS0
CA4
CS0#
CS1#
19
20
VSSQ
DM0
CA2
CA3
20
21
DQ7
DQ6
VDDQ
VSS
VSSCA
VDDCA
21
17
VREFDQ
VSS
DM1
VDD2
CK
CK#
17
22
DQ5
DQ4
CA0
CA1
22
23
VSSQ
DQ3
DQ2
NC
VDD2
VDD1
23
24
VDDQ
DQ1
NC
NC
24
25
VDD1
DQ0
VSSQ
DQ21
VDDQ
CA0
CA3
CKE0
VDD2
CA5
VDD2
NC
NC
NC
25
26
VSSQ
NC
DM2
VDDQ
DQS2
DQ22
DQ20
DQ19
DQ17
VSSQ
VDD1
CA1
CA2
CA4
CS0#
CK#
VDDCA
VSS
VDDCA
CA7
CA9
VSS
NC
NC
NC
NC
NC
26
GroundSupplyChannel BChannel A
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Figure 31: 253-Ball 2-Channel FBGA – 11mm x 11mm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
NC
VSS
VSS
VSS
VDDCA
VSS
VSS
VDD2
CHB
VDDCA
VDD2
VSS
VDDQ
VSS
VDD1
VDD1
NC
1
4
VSS
VSS
VSS
VSS
RFU
CA9
CA6
RFU
CKE1
CS0#
CA2
VSS
DQ0
DM2
DQS2#
DQS2
VSS
4
2
VSS
VDD1
VSS
VSS
ZQ0
CA7
VDDCA
CK#
CS1#
CA3
CA0
VDDQ
DQ19
DQ18
DQ17
DQ16
VDD2
2
3
VSS
VSS
VDD2
VSS
ZQ1
CA8
CA5
CK
CKE0
CA4
CA1
VDDQ
DQ23
DQ22
DQ21
DQ20
VDD2
3
5
VSS
CA0
CA1
CA2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQ4
DQ3
DQ2
DQ1
VDDQ
5
6
VDDCA
CA3
CA4
CS0#
VSS
VSS
DM0
DQ7
DQ6
DQ5
VSS
6
7
VDD2
CS1#
CKE0
CKE1
VSS
VDDQ
DQS0#
DQS0
VSS
VSS
VDDQ
7
8
VSS
CK
CK#
RFU
VSS
VSS
DM1
VSS
VDD2
CHA
8
9
VDDCA
VDDCA
CA5
CA6
VSS
RFU
DQS1#
DQS1
DQ9
DQ8
VSS
9
11
VDD2
ZQ0
ZQ1
RFU
VSS
VSS
DQ24
DM3
DQ15
DQ14
VDDQ
11
10
CHA
CA7
CA8
CA9
VSS
VDDQ
DQ13
DQ12
DQ11
DQ10
VDDQ
10
12
VSS
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VSS
RFU
VDDQ
VSS
VDDQ
DQ25
DQ26
DQS3#
DQS3
VSS
12
GroundSupplyChannel BChannel ATop View (ball down)
13
VDDQ
DQ28
DQ24
DQ15
DQ11
DM1
DQS1#
NC
DQS0#
DQ2
DQ23
DQ21
VSS
DQ29
DQ28
DQ27
VSS
13
16
VDD1
DQ31
DQ27
DQS3
DQ14
DQ10
VSS
VDD2
DQ7
DQ5
DQ1
DQS2
DQ20
DQ17
VSS
VDD1
VSS
16
17
NC
VDD2
VDD2
VSS
VDDQ
VSS
VDDQ
CHB
VSS
VDDQ
VDDQ
VSS
VSS
VDDQ
VSS
VSS
NC
17
14
VSS
DQ29
DQ25
DM3
DQ12
DQ8
DQS1
DM0
DQS0
DQ3
DM2
DQ22
DQ18
VSS
DQ31
DQ30
VDDQ
14
15
VDD1
DQ30
DQ26
DQS3#
DQ13
DQ9
VSS
VSS
DQ6
DQ4
DQ0
DQS2#
DQ19
DQ16
VDD2
VSS
VSS
15
VREFCA
VREFDQ
VREFCA
VREFDQ
NC
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Table 8: Ball/Pad Descriptions
Symbol Type Description
CA[9:0] Input Command/address inputs: Provide the command and address inputs according
to the command truth table.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All CA inputs are sampled on
both rising and falling edges of CK. CS and CKE inputs are sampled at the rising
edge of CK. AC timings are referenced to clock.
CKE[1:0] Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock
signals, input buffers, and output drivers. Power-saving modes are entered and
exited via CKE transitions. CKE is considered part of the command code. CKE is
sampled at the rising edge of CK.
CS[1:0]# Input Chip select: CS# is considered part of the command code and is sampled at the
rising edge of CK.
DM[3:0] Input Input data mask: DM is an input mask signal for write data. Although DM balls
are input-only, the DM loading is designed to match that of DQ and DQS balls.
DM[3:0] is DM for each of the four data bytes, respectively.
DQ[31:0] I/O Data input/output: Bidirectional data bus.
DQS[3:0],
DQS[3:0]#
I/O Data strobe: The data strobe is bidirectional (used for read and write data) and
complementary (DQS and DQS#). It is edge-aligned output with read data and
centered input with write data. DQS[3:0]/DQS[3:0]# is DQS for each of the four
data bytes, respectively.
VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity.
VSSQ Supply DQ ground: Isolated on the die for improved noise immunity.
VDDCA Supply Command/address power supply: Command/address power supply.
VSSCA Supply Command/address ground: Isolated on the die for improved noise immunity.
VDD1 Supply Core power: Supply 1.
VDD2 Supply Core power: Supply 2.
VSS Supply Common ground
VREFCA, VREFDQ Supply Reference voltage: VREFCA is reference for command/address input buffers,
VREFDQ is reference for DQ input buffers.
ZQ Reference External impedance (240 ohm): This signal is used to calibrate the device out-
put impedance.
DNU – Do not use: Must be grounded or left floating.
NC – No connect: Not internally connected.
(NC) – No connect: Balls indicated as (NC) are no connects, however, they could be con-
nected together internally.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Ball Assignments and Descriptions
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Functional Description
Mobile LPDDR2 is a high-speed SDRAM internally configured as a 4- or 8-bank memory
device. LPDDR2 devices use a double data rate architecture on the command/address
(CA) bus to reduce the number of input pins in the system. The 10-bit CA bus is used to
transmit command, address, and bank information. Each command uses one clock cy-
cle, during which command information is transferred on both the rising and falling
edges of the clock.
LPDDR2-S4 devices use a double data rate architecture on the DQ pins to achieve high-
speed operation. The double data rate architecture is essentially a 4n prefetch architec-
ture with an interface designed to transfer two data bits per DQ every clock cycle at the
I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or
WRITE command. The address and BA bits registered coincident with the ACTIVATE
command are used to select the row and bank to be accessed. The address bits regis-
tered coincident with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
Figure 32: Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
xRow-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode
registers
Column
decoder
Bank 0
Memory array
Bank 0
row-
address
latch
and
decoder
Sense amplifier
Bank
control
logic
Bank 1
Bank 2
Bank 3
x
y - 1
3
3
Refresh
counter
n
nn
4n
4n
4n
CK out
DATA
DQS, DQS#
CK, CK#
COL0
COL0
CK in
MUX
DQS
generator
n
n
n
n
n
DQS, DQS#
Read
latch
WRITE
FIFO
and
drivers
Data
n
n
n
n
4n
4
4
4
4
Mask
4
4
4
4
4
8
n
n
1
Bank 1
Bank 2
Bank 3
Input
registers
DM
DQ0–DQn-1
CA0
CA1
CK
CS#
CA2
CK#
Command / Address
Multiplex and Decode
CKE
CA3
CA4
CA5
CA6
CA7
CA8
CA9
I/O gating
DM mask logic
DRVRS
RCVRS
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Functional Description
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Power-Up
The following sequence must be used to power up the device. Unless specified other-
wise, this procedure is mandatory (see Figure 33 (page 49)). Power-up and initializa-
tion by means other than those specified will result in undefined operation.
1. Voltage Ramp
While applying power (after Ta), CKE must be held LOW (≤0.2 × VDDCA), and all other
inputs must be between VILmin and VIHmax. The device outputs remain at High-Z while
CKE is held LOW.
On or before the completion of the voltage ramp (Tb), CKE must be held LOW. DQ, DM,
DQS, and DQS# voltage levels must be between VSSQ and VDDQ during voltage ramp to
avoid latchup. CK, CK#, CS#, and CA input levels must be between VSSCA and VDDCA dur-
ing voltage ramp to avoid latchup.
The following conditions apply for voltage ramp:
• Ta is the point when any power supply first reaches 300mV.
• Noted conditions apply between Ta and power-down (controlled or uncontrolled).
• Tb is the point at which all supply and reference voltages are within their defined op-
erating ranges.
• Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms.
• For supply and reference voltage operating conditions, see the Recommended DC
Operating Conditions table.
• The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed
100mV.
Voltage Ramp Completion
After Ta is reached:
•V
DD1 must be greater than VDD2 - 200mV
•V
DD1 and VDD2 must be greater than VDDCA - 200mV
•V
DD1 and VDD2 must be greater than VDDQ - 200mV
•V
REF must always be less than all other supply voltages
Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100ns, after which CKE can
be asserted HIGH. The clock must be stable at least tINIT2 = 5 × tCK prior to the first
CKE LOW-to-HIGH transition (Tc). CKE, CS#, and CA inputs must observe setup and
hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subse-
quent falling and rising edges).
If any MRRs are issued, the clock period must be within the range defined for tCKb
(18ns to 100ns). MRWs can be issued at normal clock frequencies as long as all AC tim-
ings are met. Some AC parameters (for example, tDQSCK) could have relaxed timings
(such as tDQSCKb) before the system is appropriately configured. While keeping CKE
HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td).
2. RESET Command
After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional
PRECHARGE ALL command can be issued prior to the MRW RESET command.
Wait at least tINIT4 while keeping CKE asserted and issuing NOP commands.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Up
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
3. MRRs and Device Auto Initialization (DAI) Polling
After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit com-
mands are supported. After Te, CKE can go LOW in alignment with power-down entry
and exit specifications (see Power-Down (page 101)).
The MRR command can be used to poll the DAI bit, which indicates when device auto
initialization is complete; otherwise, the controller must wait a minimum of tINIT5, or
until the DAI bit is set, before proceeding.
Because the memory output buffers are not properly configured by Te, some AC param-
eters must use relaxed timing specifications before the system is appropriately config-
ured.
After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the
device is in the idle state (Tf). DAI status can be determined by issuing the MRR com-
mand to MR0.
The device sets the DAI bit no later than tINIT5 after the RESET command. The control-
ler must wait at least tINIT5 or until the DAI bit is set before proceeding.
4. ZQ Calibration
After tINIT5 (Tf), the MRW initialization calibration (ZQ calibration) command can be
issued to the memory (MR10).
This command is used to calibrate output impedance over process, voltage, and tem-
perature. In systems where more than one Mobile LPDDR2 device exists on the same
bus, the controller must not overlap MRW ZQ calibration commands. The device is
ready for normal operation after tZQINIT.
5. Normal Operation
After (Tg), MRW commands must be used to properly configure the memory (output
buffer drive strength, latencies, etc.). Specifically, MR1, MR2, and MR3 must be set to
configure the memory for the target frequency and memory configuration.
After the initialization sequence is complete, the device is ready for any valid command.
After Tg, the clock frequency can be changed using the procedure described in Input
Clock Frequency Changes and Clock Stop with CKE HIGH (page 110).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Up
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Figure 33: Voltage Ramp and Initialization Sequence
Ta Tb Tc Td Te Tf Tg
RESET MRR MRW
ZQ
_CAL Valid
CK/CK#
Supplies
CKE
CA
RTT
DQ
tINIT0
tINIT1 tINIT3
tINIT4 tZQINIT
tINIT5
tISCKE
tINIT2
Note: 1. High-Z on the CA bus indicates valid NOP.
Table 9: Initialization Timing Parameters
Parameter
Value
Unit CommentMin Max
tINIT0 – 20 ms Maximum voltage ramp time
tINIT1 100 – ns Minimum CKE LOW time after completion of voltage ramp
tINIT2 5 – tCK Minimum stable clock before first CKE HIGH
tINIT3 200 – μs Minimum idle time after first CKE assertion
tINIT4 1 – μs Minimum idle time after RESET command
tINIT5 – 10 μs Maximum duration of device auto initialization
tZQINIT 1 – μs ZQ initial calibration (S4 devices only)
tCKb 18 100 ns Clock cycle time during boot
Note: 1. The tINIT0 maximum specification is not a tested limit and should be used as a general
guideline. For voltage ramp times exceeding tINIT0 MAX, please contact the factory.
Initialization After RESET (Without Voltage Ramp)
If the RESET command is issued before or after the power-up initialization sequence,
the reinitialization procedure must begin at Td.
Power-Off
While powering off, CKE must be held LOW (≤0.2 × VDDCA); all other inputs must be be-
tween VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Off
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DQ, DM, DQS, and DQS# voltage levels must be between VSSQ and VDDQ during the
power-off sequence to avoid latchup. CK, CK#, CS#, and CA input levels must be be-
tween VSSCA and VDDCA during the power-off sequence to avoid latchup.
Tx is the point where any power supply drops below the minimum value specified in
the Recommended DC Operating Conditions table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is pow-
ered off.
Required Power Supply Conditions Between Tx and Tz:
•V
DD1 must be greater than VDD2 - 200mV
•V
DD1 must be greater than VDDCA - 200mV
•V
DD1 must be greater than VDDQ - 200mV
•V
REF must always be less than all other supply voltages
The voltage difference between VSS, VSSQ, and VSSCA must not exceed 100mV.
For supply and reference voltage operating conditions, see Recommended DC Operat-
ing Conditions table.
Uncontrolled Power-Off
When an uncontrolled power-off occurs, the following conditions must be met:
• At Tx, when the power supply drops below the minimum values specified in the Rec-
ommended DC Operating Conditions table, all power supplies must be turned off and
all power-supply current capacity must be at zero, except for any static charge re-
maining in the system.
• After Tz (the point at which all power supplies first reach 300mV), the device must
power off. The time between Tx and Tz must not exceed tPOFF. During this period, the
relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must de-
crease with a slope lower than 0.5 V/μs between Tx and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of
the device.
Table 10: Power-Off Timing
Parameter Symbol Min Max Unit
Maximum power-off ramp time tPOFF – 2 sec
Mode Register Definition
LPDDR2 devices contain a set of mode registers used for programming device operating
parameters, reading device information and status, and for initiating special operations
such as DQ calibration, ZQ calibration, and device reset.
Mode Register Assignments and Definitions
The MRR command is used to read from a register. The MRW command is used to write
to a register. An “R” in the access column of the mode register assignment table indi-
cates read-only; a “W” indicates write-only; “R/W” indicates read or write capable or
enabled.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 11: Mode Register Assignments
Notes 1–5 apply to all parameters and conditions
MR# MA[7:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link
0 00h Device info R RFU RZQI DNVI DI DAI go to MR0
1 01h Device feature 1 W nWR (for AP) WC BT BL go to MR1
2 02h Device feature 2 W RFU RL and WL go to MR2
3 03h I/O config-1 W RFU DS go to MR3
4 04h SDRAM refresh
rate
R TUF RFU Refresh rate go to MR4
5 05h Basic config-1 R LPDDR2 Manufacturer ID go to MR5
6 06h Basic config-2 R Revision ID1 go to MR6
7 07h Basic config-3 R Revision ID2 go to MR7
8 08h Basic config-4 R I/O width Density Type go to MR8
9 09h Test mode W Vendor-specific test mode go to MR9
10 0Ah I/O calibration W Calibration code go to MR10
11–15 0Bh ≈ 0Fh Reserved – RFU go to MR11
16 10h PASR_Bank W Bank mask go to MR16
17 11h PASR_Seg W Segment mask go to MR17
18–19 12h–13h Reserved – RFU go to MR18
20–31 14h–1Fh Reserved for NVM MR20–MR30
32 20h DQ calibration
pattern A
R See Table 48 (page 97). go to MR32
33–39 21h–27h Do not use go to MR33
40 28h DQ calibration
pattern B
R See Table 48 (page 97). go to MR40
41–47 29h–2Fh Do not use go to MR41
48–62 30h–3Eh Reserved – RFU go to MR48
63 3Fh RESET W X go to MR63
64–126 40h–7Eh Reserved – RFU go to MR64
127 7Fh Do not use go to MR127
128–190 80h–BEh Reserved for vendor use RVU go to MR128
191 BFh Do not use go to MR191
192–254 C0h–FEh Reserved for vendor use RVU go to MR192
255 FFh Do not use go to MR255
Notes: 1. RFU bits must be set to 0 during MRW.
2. RFU bits must be read as 0 during MRR.
3. For READs to a write-only or RFU register, DQS will be toggled and undefined data is
returned.
4. RFU mode registers must not be written.
5. WRITEs to read-only registers must have no impact on the functionality of the device.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 12: MR0 Device Information (MA[7:0] = 00h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU RZQI DNVI DI DAI
Table 13: MR0 Op-Code Bit Definitions
Notes 1–4 apply to all parameters and conditions
Register Information Tag Type OP Definition
Device auto initialization
status
DAI Read-only OP0 0b: DAI complete
1b: DAI in progress
Device information DI Read-only OP1 0b
1b: NVM
Data not valid information DNVI Read-only OP2 0b: DNVI not supported
Built-in self test for RZQ
information
RZQI Read-only OP[4:3] 00b: RZQ self test not supported
01b: ZQ pin might be connected to VDDCA or left float-
ing
10b: ZQ pin might be shorted to ground
11b: ZQ pin self test complete; no error condition de-
tected
Notes: 1. If RZQI is supported, it will be set upon completion of the MRW ZQ initialization calibra-
tion.
2. If ZQ is connected to VDDCA to set default calibration, OP[4:3] must be set to 01. If ZQ is
not connected to VDDCA, either OP[4:3] = 01 or OP[4:3] = 10 could indicate a ZQ-pin as-
sembly error. It is recommended that the assembly error be corrected.
3. In the case of a possible assembly error (either OP[4:3] = 01 or OP[4:3] = 10, as defined
above), the device will default to factory trim settings for RON and will ignore ZQ cali-
bration commands. In either case, the system might not function as intended.
4. If a ZQ self test returns a value of 11b, this indicates that the device has detected a resis-
tor connection to the ZQ pin. Note that this result cannot be used to validate the ZQ
resistor value, nor does it indicate that the ZQ resistor tolerance meets the specified lim-
its (240 ohms ±1%).
Table 14: MR1 Device Feature 1 (MA[7:0] = 01h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
nWR (for AP) WC BT BL
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 15: MR1 Op-Code Bit Definitions
Feature Type OP Definition Notes
BL = burst length Write-only OP[2:0] 010b: BL4 (default)
011b: BL8
100b: BL16
All others: Reserved
BT = burst type Write-only OP3 0b: Sequential (default)
1b: Interleaved
WC = wrap control Write-only OP4 0b: Wrap (default)
1b: No wrap
nWR = number of tWR clock
cycles
Write-only OP[7:5] 001b: nWR = 3 (default) 1
010b: nWR = 4
011b: nWR = 5
100b: nWR = 6
101b: nWR = 7
110b: nWR = 8
All others: Reserved
Note: 1. The programmed value in nWR register is the number of clock cycles that determines
when to start internal precharge operation for a WRITE burst with AP enabled. It is de-
termined by RU (tWR/tCK).
Table 16: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC)
Notes 1–5 apply to all parameters and conditions
BL BT C3 C2 C1 C0 WC
Burst Cycle Number and Burst Address Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
4AnyX X0b0bWrap0123
X X1b0b 2301
Any X X X 0b No
wrap
yy +
1
y +
2
y +
3
8SeqX0b0b0bWrap01234567
X0b1b0b 23456701
X1b0b0b 45670123
X1b1b0b 67012345
IntX0b0b0b 01234567
X0b1b0b 23016745
X1b0b0b 45670123
X1b1b0b 67452301
Any X X X 0b No
wrap
Illegal (not supported)
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 16: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) (Continued)
Notes 1–5 apply to all parameters and conditions
BL BT C3 C2 C1 C0 WC
Burst Cycle Number and Burst Address Sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16Seq0b0b0b0bWrap0123456789ABCDEF
0b0b1b0b 23456789ABCDEF01
0b1b0b0b 456789ABCDEF0123
0b1b1b0b 6789ABCDEF012345
1b0b0b0b 89ABCDEF01234567
1b0b1b0b ABCDEF0123456789
1b1b0b0b CDEF0123456789AB
1b1b1b0b EF0123456789ABCD
Int X X X 0b Illegal (not supported)
Any X X X 0b No
wrap
Illegal (not supported)
Notes: 1. C0 input is not present on CA bus. It is implied zero.
2. For BL = 4, the burst address represents C[1:0].
3. For BL = 8, the burst address represents C[2:0].
4. For BL = 16, the burst address represents C[3:0].
5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boun-
dary. The variable y can start at any address with C0 equal to 0, but must not start at any
address shown in the following table.
Table 17: No-Wrap Restrictions
Width 64Mb 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb
Cannot cross full-page boundary
x16 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001
x32 7E, 7F, 00, 01 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001
Cannot cross sub-page boundary
x16 7E, 7F, 80, 81 0FE, 0FF, 100, 101 1FE, 1FF, 200, 201 3FE, 3FF, 400, 401
x32 None None None None
Note: 1. No-wrap BL = 4 data orders shown are prohibited.
Table 18: MR2 Device Feature 2 (MA[7:0] = 02h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU RL and WL
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 19: MR2 Op-Code Bit Definitions
Feature Type OP Definition
RL and
WL
Write-only OP[3:0] 0001b: RL3/WL1 (default)
0010b: RL4/WL2
0011b: RL5/WL2
0100b: RL6/WL3
0101b: RL7/WL4
0110b: RL8/WL4
All others: Reserved
Table 20: MR3 I/O Configuration 1 (MA[7:0] = 03h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
RFU DS
Table 21: MR3 Op-Code Bit Definitions
Feature Type OP Definition
DS Write-only OP[3:0] 0000b: Reserved
0001b: 34.3 ohm typical
0010b: 40 ohm typical (default)
0011b: 48 ohm typical
0100b: 60 ohm typical
0101b: Reserved
0110b: 80 ohm typical
0111b: 120 ohm typical
All others: Reserved
Table 22: MR4 Device Temperature (MA[7:0] = 04h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
TUF RFU SDRAM refresh rate
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 23: MR4 Op-Code Bit Definitions
Notes 1–8 apply to all parameters and conditions
Feature Type OP Definition
SDRAM refresh
rate
Read-only OP[2:0] 000b: SDRAM low temperature operating limit exceeded
001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW
010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW
011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C)
100b: Reserved
101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, do not derate SDRAM AC
timing
110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, derate SDRAM AC timing
111b: SDRAM high temperature operating limit exceeded
Temperature up-
date flag (TUF)
Read-only OP7 0b: OP[2:0] value has not changed since last read of MR4
1b: OP[2:0] value has changed since last read of MR4
Notes: 1. A MODE REGISTER READ from MR4 will reset OP7 to 0.
2. OP7 is reset to 0 at power-up.
3. If OP2 = 1, the device temperature is greater than 85˚C.
4. OP7 is set to 1 if OP[2:0] has changed at any time since the last MR4 read.
5. The device might not operate properly when OP[2:0] = 000b or 111b.
6. For specified operating temperature range and maximum operating temperature, refer
to the Operating Temperature Range table.
7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing param-
eters: tRCD, tRC, tRAS, tRP, and tRRD. The tDQSCK parameter must be derated as speci-
fied in AC Timing. Prevailing clock frequency specifications and related setup and hold
timings remain unchanged.
8. The recommended frequency for reading MR4 is provided in Temperature Sensor (page
94).
Table 24: MR5 Basic Configuration 1 (MA[7:0] = 05h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
LPDDR2 Manufacturer ID
Table 25: MR5 Op-Code Bit Definitions
Feature Type OP Definition
Manufacturer ID Read-only OP[7:0] 1111 1111b: Micron
All others: Reserved
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 26: MR6 Basic Configuration 2 (MA[7:0] = 06h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID1
Note: 1. MR6 is vendor-specific.
Table 27: MR6 Op-Code Bit Definitions
Feature Type OP Definition
Revision ID1 Read-only OP[7:0] 0000 0000b: Version A
Table 28: MR7 Basic Configuration 3 (MA[7:0] = 07h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Revision ID2
Table 29: MR7 Op-Code Bit Definitions
Feature Type OP Definition
Revision ID2 Read-only OP[7:0] 0000 0000b: Version A
Note: 1. MR7 is vendor-specific.
Table 30: MR8 Basic Configuration 4 (MA[7:0] = 08h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
I/O width Density Type
Table 31: MR8 Op-Code Bit Definitions
Feature Type OP Definition
Type Read-only OP[1:0] 00b
01b
10b: NVM
11b: Reserved
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 31: MR8 Op-Code Bit Definitions (Continued)
Feature Type OP Definition
Density Read-only OP[5:2] 0000b: 64Mb
0001b: 128Mb
0010b: 256Mb
0011b: 512Mb
0100b: 1Gb
0101b: 2Gb
0110b: 4Gb
0111b: 8Gb
1000b: 16Gb
1001b: 32Gb
All others: Reserved
I/O width Read-only OP[7:6] 00b: x32
01b: x16
10b: x8
11b: not used
Table 32: MR9 Test Mode (MA[7:0] = 09h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Vendor-specific test mode
Table 33: MR10 Calibration (MA[7:0] = 0Ah)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
S4 Calibration code
Table 34: MR10 Op-Code Bit Definitions
Notes 1–4 apply to all parameters and conditions
Feature Type OP Definition
Calibration code Write-only OP[7:0] 0xFF: Calibration command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQRESET
All others: Reserved
Notes: 1. Host processor must not write MR10 with reserved values.
2. The device ignores calibration commands when a reserved value is written into MR10.
3. See AC timing table for the calibration latency.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQ
Calibration Commands (page 99)) or default calibration (through the ZQRESET com-
mand) is supported. If ZQ is connected to VDDCA, the device operates with default cali-
bration, and ZQ calibration commands are ignored. In both cases, the ZQ connection
must not change after power is supplied to the device.
Table 35: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Reserved
Table 36: MR16 PASR Bank Mask (MA[7:0] = 010h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Bank mask (4-bank or 8-bank)
Table 37: MR16 Op-Code Bit Definitions
Feature Type OP Definition
Bank[7:0] mask Write-only OP[7:0] 0b: refresh enable to the bank = unmasked (default)
1b: refresh blocked = masked
Note: 1. For 4-bank devices, only OP[3:0] are used.
Table 38: MR17 PASR Segment Mask (MA[7:0] = 011h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
Segment mask
Note: 1. This table applies for 1Gb to 8Gb devices only.
Table 39: MR17 PASR Segment Mask Definitions
Feature Type OP Definition
Segment[7:0] mask Write-only OP[7:0] 0b: refresh enable to the segment: = unmasked (default)
1b: refresh blocked: = masked
Table 40: MR17 PASR Row Address Ranges in Masked Segments
Segment OP Segment Mask
1Gb 2Gb, 4Gb 8Gb
R[12:10] R[13:11] R[14:12]
0 0 XXXXXXX1 000b
1 1 XXXXXX1X 001b
2 2 XXXXX1XX 010b
3 3 XXXX1XXX 011b
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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Table 40: MR17 PASR Row Address Ranges in Masked Segments (Continued)
Segment OP Segment Mask
1Gb 2Gb, 4Gb 8Gb
R[12:10] R[13:11] R[14:12]
4 4 XXX1XXXX 100b
5 5 XX1XXXXX 101b
6 6 X1XXXXXX 110b
7 7 1XXXXXXX 111b
Note: 1. X is “Don’t Care” for the designated segment.
Table 41: Reserved Mode Registers
Mode Reg-
ister MA Address Restriction OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
MR[18:19] MA[7:0] 12h–13h RFU Reserved
MR[20:31] 14h–1Fh NVM1
MR[33:39] 21h–27h DNU1
MR[41:47] 29h–2Fh
MR[48:62] 30h–3Eh RFU
MR[64:126] 40h–7Eh RFU
MR127 7Fh DNU
MR[128:190] 80h–BEh RVU1
MR191 BFh DNU
MR[192:254] C0h–FEh RVU
MR255 FFh DNU
Note: 1. NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use.
Table 42: MR63 RESET (MA[7:0] = 3Fh) – MRW Only
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
X
Note: 1. For additional information on MRW RESET see MODE REGISTER WRITE Command (page
98).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Mode Register Definition
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ACTIVATE Command
The ACTIVATE command is issued by holding CS# LOW, CA0 LOW, and CA1 HIGH at the
rising edge of the clock. The bank addresses BA[2:0] are used to select the desired bank.
Row addresses are used to determine which row to activate in the selected bank. The
ACTIVATE command must be applied before any READ or WRITE operation can be exe-
cuted. The device can accept a READ or WRITE command at tRCD after the ACTIVATE
command is issued. After a bank has been activated, it must be precharged before an-
other ACTIVATE command can be applied to the same bank. The bank active and pre-
charge times are defined as tRAS and tRP, respectively. The minimum time interval be-
tween successive ACTIVATE commands to the same bank is determined by the RAS cy-
cle time of the device (tRC). The minimum time interval between ACTIVATE commands
to different banks is tRRD.
Figure 34: ACTIVATE Command
Bank n
row addr Row addr
ACTIVATE NOP ACTIVATE READ PRECHARGE ACTIVATE
NOP NOP
Bank m
row addr Row addr Bank n
col addr Col addr Bank n Bank n
row addr Row addr
T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3
CK#
CK
CA[9:0]
CMD
tRRD
tRCD
tRC
tRAS tRP
Notes: 1. tRCD = 3, tRP = 3, tRRD = 2.
2. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE com-
mand uses tRPpb timing. In this figure, tRP is used to denote either an all-bank PRE-
CHARGE or a single-bank PRECHARGE.
8-Bank Device Operation
Two rules regarding 8-bank device operation must be observed. One rule restricts the
number of sequential ACTIVATE commands that can be issued; the second provides ad-
ditional RAS precharge time for a PRECHARGE ALL command.
The 8-Bank Device Sequential Bank Activation Restriction: No more than four banks
can be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. To con-
vert to clocks, divide tFAW[ns] by tCK[ns], and round up to the next integer value. For
example, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued in clock n,
no more than three further ACTIVATE commands can be issued at or between clock
n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW.
The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command
must equal tRPab, which is greater than tRPpb.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
ACTIVATE Command
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Figure 35: tFAW Timing (8-Bank Devices)
CK#
CK
CA[9:0]
Tn Tn+ Tm Tm+ Tx Tx+ Ty Ty + 1 Ty + 2 Tz Tz + 1 Tz + 2
Bank
A
ACTIVATE NOP
CMD
Bank
A
Bank
B
ACTIVATE NOP
Bank
B
Bank
C
ACTIVATE NOP
Bank
C
Bank
D
ACTIVATE NOP
Bank
D
NOP NOP
Bank
E
ACTIVATE NOP
Bank
E
tRRD
tFAW
tRRD tRRD
Note: 1. Exclusively for 8-bank devices.
Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS# LOW, CA0
HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this
time to determine whether the access cycle is a READ operation (CA2 HIGH) or a
WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst
READ or burst WRITE operation on successive clock cycles.
A new burst access must not interrupt the previous 4-bit burst operation when BL = 4.
When BL = 8 or BL = 16, READs can be interrupted by READs and WRITEs can be inter-
rupted by WRITEs, provided that the interrupt occurs on a 4-bit boundary and that
tCCD is met.
Burst READ Command
The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)
is defined from the rising edge of the clock on which the READ command is issued to
the rising edge of the clock from which the tDQSCK delay is measured. The first valid
data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the
READ command is issued. The data strobe output is driven LOW tRPRE before the first
valid rising strobe edge. The first bit of the burst is synchronized with the first rising
edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-
aligned with the data strobe. The RL is programmed in the mode registers.
Pin input timings for the data strobe are measured relative to the crosspoint of DQS and
its complement, DQS#.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Read and Write Access Modes
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Figure 36: READ Output Timing – tDQSCK (MAX)
RL - 1 RL RL + BL/2
CK#
CK
DQS#
DQS
DQ
tLZ(DQS)
DOUT DOUT DOUT DOUT
tHZ(DQS)
tRPRE tRPST
tDQSCKmax
tQH
tLZ(DQ) tHZ(DQ)
tDQSQmax
tCL
tCH
tQH
tDQSQmax
Transitioning data
Notes: 1. tDQSCK can span multiple clock periods.
2. An effective burst length of 4 is shown.
Figure 37: READ Output Timing – tDQSCK (MIN)
RL - 1 RL RL + BL/2
CK#
CK
DQS#
DQS
DQ
tLZ(DQS)
DOUT DOUT DOUT DOUT
tHZ(DQS)
tRPRE
tDQSCKmin
tQH
tLZ(DQ)
tDQSQmax
tCL
tCH
tQH
tDQSQmax
tRPST
tHZ(DQ)
Transitioning data
Note: 1. An effective burst length of 4 is shown.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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Figure 38: Burst READ – RL = 5, BL = 4, tDQSCK > tCK
Bank n
col addr Col addr
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 5
Transitioning data
NOP NOP NOP NOP
tDQSCK
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
CK#
CK
Figure 39: Burst READ – RL = 3, BL = 8, tDQSCK < tCK
Bank n
col addr Col addr
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning data
NOP NOP NOP NOP
tDQSCK
NOP
DOUT A4 DOUT A5 DOUT A6 DOUT A7DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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Figure 40: tDQSCKDL Timing
Col addr
Bank n
col addr
READ NOP
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
Transitioning data
NOP NOP NOP NOP
tDQSCKm
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
CK#
CK
1
Col addr
Bank n
col addr
READ NOP
Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
…32ms maximum
32ms maximum…
NOP NOP NOP NOP
tDQSCKn
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
CK#
CK
1
Notes: 1. tDQSCKDL = (tDQSCKn - tDQSCKm).
2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 32ms rolling window.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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Figure 41: tDQSCKDM Timing
Col addr
Bank n
col addr
READ NOP
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
Transitioning data
NOP NOP NOP NOP
tDQSCKm
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
CK#
CK
1
Col addr
Bank n
col addr
READ NOP
Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
…1.6μs maximum
1.6μs maximum…
NOP NOP NOP NOP
tDQSCKn
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
CK#
CK
1
Notes: 1. tDQSCKDM = (tDQSCKn - tDQSCKm).
2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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Figure 42: tDQSCKDS Timing
Col addr
Bank n
col addr
READ NOP
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
Transitioning data
NOP NOP NOP NOP
tDQSCKm
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3DOUT A0 DOUT A1 DOUT A2 DOUT A3DOUT A0 DOUT A1 DOUT A2 DOUT A3DOUT A0 DOUT A1 DOUT A2 DOUT A3DOUT A2 DOUT A3
NOP NOP
CK#
CK
1
Col addr
Bank n
col addr
READ NOP
Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8
CA
[9:0]
CMD
DQS#
DQS
DQ
RL = 5
…160ns maximum
160ns maximum…
NOP NOP NOP NOP
tDQSCKn
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4
NOP NOP
CK#
CK
1
Notes: 1. tDQSCKDS = (tDQSCKn - tDQSCKm).
2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling
window.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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Figure 43: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4
Bank n
col addr Col addr
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3 WL = 1
BL/2
Transitioning data
NOP NOP NOP NOP
tDQSCK tDQSSmin
WRITE
DIN A0 DIN A1 DDOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Bank n
col addr Col addr
The minimum time from the burst READ command to the burst WRITE command is
defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles. Note that if a READ
burst is truncated with a burst TERMINATE (BST) command, the effective burst length
of the truncated READ burst should be used for BL when calculating the minimum
READ-to-WRITE delay.
Figure 44: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2
Bank n
col addr a Col addr a
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning data
READ NOP NOP NOP
tCCD = 2
NOP
DOUT B0 DOUT B1 DOUT B2 DOUT B3DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Bank n
col addr b Col addr b
A seamless burst READ operation is supported by enabling a READ command at every
other clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and
every eighth clock cycle for BL = 16 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst READ Command
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READs Interrupted by a READ
A burst READ can be interrupted by another READ with a 4-bit burst boundary, provi-
ded that tCCD is met.
Figure 45: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning data
READ NOP NOP NOP
tCCD = 2
NOP
DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B4 DOUT B5
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Bank n
col addr a Col addr a Bank n
col addr b Col addr b
Note: 1. READs can only be interrupted by other READs or the BST command.
Burst WRITE Command
The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is
defined from the rising edge of the clock on which the WRITE command is issued to the
rising edge of the clock from which the tDQSS delay is measured. The first valid data
must be driven WL × tCK + tDQSS from the rising edge of the clock from which the
WRITE command is issued. The data strobe signal (DQS) must be driven LOW tWPRE
prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to
the associated edge of the DQS and held valid until tDH after that edge. Burst data is
sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is com-
pleted. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE
command to the same bank can be issued.
Pin input timings are measured relative to the crosspoint of DQS and its complement,
DQS#.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst WRITE Command
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Figure 46: Data Input (WRITE) Timing
DQS
DQS#
DQS#
DQS
DQ
DM
VIL(AC)
VIH(AC)
tDS
tWPRE tDQSH tDQSL tWPST
tDH
tDS tDH
tDH VIL(AC)
VIH(AC)
tDS
VIL(AC)
VIH(AC)
DIN DIN DIN DIN
VIL(DC)
VIH(DC)
VIL(DC)
VIH(DC)
tDH
VIL(DC)
VIH(DC)
tDS
VIL(AC)
VIH(AC)
VIL(DC)
VIH(DC)
Don’t Care
Figure 47: Burst WRITE – WL = 1, BL = 4
Bank n
col addr Col addr
WRITE NOP
T0 T1 T2 T3 T4 Tx Tx + 1 Ty Ty + 1
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
tWR
Completion of burst WRITE
Transitioning data
NOP NOP NOP PRECHARGE
tDQSSmax tDSS tDSS
NOP
DIN A0 DIN A1 DIN A2 DIN A3
ACTIVATE NOP
Bank n Bank n
row addr Row addr
DQS#
DQS
DQ
tWR
tDQSSmin tDSH tDSH tRP
DIN A0 DIN A1 DIN A2 DIN A3
Case 1: tDQSSmax
Case 2: tDQSSmin
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst WRITE Command
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Figure 48: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4
Bank m
col addr a Col addr a
WRITE NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1 RL = 3
tWTR
Transitioning data
NOP NOP NOP NOP READ
DIN A0 DIN A1 DIN A2 DIN A3
NOP NOP
Bank n
col addr b Col addr b
Notes: 1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
3. If a WRITE burst is truncated with a BST command, the effective burst length of the
truncated WRITE burst should be used as BL to calculate the minimum WRITE-to-READ
delay.
Figure 49: Seamless Burst WRITE – WL = 1, BL = 4, tCCD = 2
Bank m
col addr a Col addr a
WRITE NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
Transitioning data
WRITE NOP NOP NOP
tCCD = 2
NOP
DIN B0 DIN B1 DIN B2 DIN B3DIN A0 DIN A1 DIN A2 DIN A3
NOP NOP
Bank n
col addr b Col addr b
Note: 1. The seamless burst WRITE operation is supported by enabling a WRITE command every
other clock for BL = 4 operation, every four clocks for BL = 8 operation, or every eight
clocks for BL = 16 operation. This operation is supported for any activated bank.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst WRITE Command
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WRITEs Interrupted by a WRITE
A burst WRITE can only be interrupted by another WRITE with a 4-bit burst boundary,
provided that tCCD (MIN) is met.
A WRITE burst interrupt can occur on even clock cycles after the initial WRITE com-
mand, provided that tCCD (MIN) is met.
Figure 50: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2
Bank m
col addr a Col addr a
WRITE NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
Transitioning data
WRITE NOP NOP NOP
tCCD = 2
NOP
DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7DIN A0 DIN A1 DIN A2 DIN A3
NOP NOP
Bank n
col addr b Col addr b
Notes: 1. WRITEs can only be interrupted by other WRITEs or the BST command.
2. The effective burst length of the first WRITE equals two times the number of clock cycles
between the first WRITE and the interrupting WRITE.
BURST TERMINATE Command
The BURST TERMINATE (BST) command is initiated with CS# LOW, CA0 HIGH, CA1
HIGH, CA2 LOW, and CA3 LOW at the rising edge of the clock. A BST command can only
be issued to terminate an active READ or WRITE burst. Therefore, a BST command can
only be issued up to and including BL/2 - 1 clock cycles after a READ or WRITE com-
mand. The effective burst length of a READ or WRITE command truncated by a BST
command is as follows:
• Effective burst length = 2 × (number of clock cycles from the READ or WRITE com-
mand to the BST command).
• If a READ or WRITE burst is truncated with a BST command, the effective burst length
of the truncated burst should be used for BL when calculating the minimum READ-
to-WRITE or WRITE-to-READ delay.
• The BST command only affects the most recent READ or WRITE command. The BST
command truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the ris-
ing edge of the clock where the BST command is issued. The BST command truncates
an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the
BST command is issued.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
BURST TERMINATE Command
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• The 4-bit prefetch architecture enables BST command assertion on even clock cycles
following a WRITE or READ command. The effective burst length of a READ or WRITE
command truncated by a BST command is thus an integer multiple of four.
Figure 51: Burst WRITE Truncated by BST – WL = 1, BL = 16
Bank m
col addr a Col addr a
WRITE NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
Transitioning dataBST prohibited
NOP NOP BST NOP
WL × tCK + tDQSS
NOP
DIN A4 DIN A5 DIN A6 DIN A7DIN A0 DIN A1 DIN A2 DIN A3
NOP NOP
Notes: 1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising
edge of the clock where the BST command is issued.
2. BST can only be issued an even number of clock cycles after the WRITE command.
3. Additional BST commands are not supported after T4 and must not be issued until after
the next READ or WRITE command.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
BURST TERMINATE Command
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Figure 52: Burst READ Truncated by BST – RL = 3, BL = 16
Bank n
col addr a Col addr a
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning dataBST prohibited
NOP NOP BST NOP
RL × tCK + tDQSCK + tDQSQ
NOP
DOUT A4 DOUT A5 DOUT A6 DOUT A7DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Notes: 1. The BST command truncates an ongoing READ burst (RL × tCK + tDQSCK + tDQSQ) after
the rising edge of the clock where the BST command is issued.
2. BST can only be issued an even number of clock cycles after the READ command.
3. Additional BST commands are not supported after T4 and must not be issued until after
the next READ or WRITE command.
Write Data Mask
On LPDDR2 devices, one write data mask (DM) pin for each data byte (DQ) is suppor-
ted, consistent with the implementation on LPDDR SDRAM. Each DM can mask its re-
spective DQ for any given cycle of the burst. Data mask timings match data bit timing,
but are inputs only. Internal data mask loading is identical to data bit loading to ensure
matched system timing.
Figure 53: Data Mask Timing
DQS
DQS#
DQ
DM
tDS tDH tDS
VIL(AC)
VIH(AC)
VIL(AC)
VIH(AC)
VIL(DC)
VIH(DC)
tDH
VIL(DC)
VIH(DC)
Don’t Care
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Write Data Mask
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Figure 54: Write Data Mask – Second Data Bit Masked
DQS
DQS#
CK#
CK
DQ
Don’t Care
DM
CMD
WL = 2
tDQSSmax
tDQSSmin
DOUT 0 DOUT 1 DOUT 2 DOUT 3
WRITE
tWTR
tWR
DQS#
DQS
DQ
DM
DOUT 0 DOUT 1 DOUT 2 DOUT 3
Case 1: tDQSSmin
Case 2: tDQSSmax
Note: 1. For the data mask function, WL = 2, BL = 4 is shown; the second data bit is masked.
PRECHARGE Command
The PRECHARGE command is used to precharge or close a bank that has been activa-
ted. The PRECHARGE command is initiated with CS# LOW, CA0 HIGH, CA1 HIGH, CA2
LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command can be
used to precharge each bank independently or all banks simultaneously. For 4-bank de-
vices, the AB flag and bank address bits BA0 and BA1 are used to determine which
bank(s) to precharge. For 8-bank devices, the AB flag and the bank address bits BA0,
BA1, and BA2 are used to determine which bank(s) to precharge. The precharged
bank(s) will be available for subsequent row access tRPab after an all bank PRECHARGE
command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that 8-bank devices can meet the instantaneous current demand required to
operate, the row precharge time (tRP) for an all bank PRECHARGE in 8-bank devices
(tRPab) will be longer than the row precharge time for a single-bank PRECHARGE
(tRPpb). For 4-bank devices, tRPab is equal to tRPpb.
ACTIVATE to PRECHARGE timing is shown in ACTIVATE Command (page 61).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Table 43: Bank Selection for PRECHARGE by Address Bits
AB (CA4r)
BA2
(CA9r)
BA1
(CA8r)
BA0
(CA7r)
Precharged Bank(s)
4-Bank Device
Precharged Bank(s)
8-Bank Device
0 0 0 0 Bank 0 only Bank 0 only
0 0 0 1 Bank 1 only Bank 1 only
0 0 1 0 Bank 2 only Bank 2 only
0 0 1 1 Bank 3 only Bank 3 only
0 1 0 0 Bank 0 only Bank 4 only
0 1 0 1 Bank 1 only Bank 5 only
0 1 1 0 Bank 2 only Bank 6 only
0 1 1 1 Bank 3 only Bank 7 only
1 Don’t Care Don’t Care Don’t Care All banks All banks
READ Burst Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2
clock cycles after a READ command. A new bank ACTIVATE command can be issued to
the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE com-
mand cannot be issued until after tRAS is satisfied.
The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ com-
mand. tRTP begins BL/2 - 2 clock cycles after the READ command.
If the burst is truncated by a BST command, the effective BL value is used to calculate
when tRTP begins.
Figure 55: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2
Bank m
col addr a Col addr a
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
tRP
Transitioning data
NOP NOP PRECHARGE NOP
tRTP
NOP
DOUT A4 DOUT A5 DOUT A6 DOUT A7DOUT A0 DOUT A1 DOUT A2 DOUT A3
ACTIVATE NOP
Bank m Bank m
row addr Row addr
BL/2
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Figure 56: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3
Bank m
col addr a Col addr a
READ NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
tRP
Transitioning data
NOP PRECHARGE NOPNOP
tRTP = 3
BL/2
ACTIVATE
DOUT A0 DOUT A1 DOUT A2 DOUT A3
NOP NOP
Bank m Bank m
row addr Row addr
WRITE Burst Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time (tWR) must be provided before a PRECHARGE
command can be issued. tWR delay is referenced from the completion of the burst
WRITE. The PRECHARGE command must not be issued prior to the tWR delay. For
WRITE-to-PRECHARGE timings see Table 44 (page 80).
These devices write data to the array in prefetch quadruples (prefetch = 4). An internal
WRITE operation can only begin after a prefetch group has been completely latched.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +
BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the
mode register. For truncated bursts, BL is the effective burst length.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Figure 57: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4
Bank n
col addr Col addr
WRITE NOP
T0 T1 T2 T3 T4 Tx Tx + 1 Ty Ty + 1
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
tWR
Completion of burst WRITE
Transitioning data
NOP NOP NOP PRECHARGE
tDQSSmax
NOP
DIN A0 DIN A1 DIN A2 DIN A3
ACTIVATE NOP
Bank n Bank n
row addr Row addr
DQS#
DQS
DQ
tDQSSmin
≥tRP
DIN A0 DIN A1 DIN A2 DIN A3
Case 1: tDQSSmax
Case 2: tDQSSmin
Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge function. When a READ
or WRITE command is issued to the device, the auto precharge bit (AP) can be set to
enable the active bank to automatically begin precharge at the earliest possible mo-
ment during the burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, then normal READ or
WRITE burst operation is executed and the bank remains active at the completion of
the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge func-
tion is engaged. This feature enables the PRECHARGE operation to be partially or com-
pletely hidden during burst READ cycles (dependent upon READ or WRITE latency),
thus improving system performance for random data access.
READ Burst with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge
function is engaged.
These devices start an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 +
RU(tRTP/tCK) clock cycles later than the READ with auto precharge command, which-
ever is greater. For auto precharge calculations see Table 44 (page 80).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Following an auto precharge operation, an ACTIVATE command can be issued to the
same bank if the following two conditions are satisfied simultaneously:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto pre-
charge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 58: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2
Bank m
col addr a Col addr a
READ w/AP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
RL = 3
Transitioning data
NOP NOP NOP ACTIVATE
tRTP
BL/2
NOP
DOUT
A0 DOUT
A1 DOUT
A2 DOUT
A3
NOP NOP
Bank m
row addr Row addr
≥tRPpb
WRITE Burst with Auto Precharge
If AP (CA0f) is HIGH when a WRITE command is issued, the WRITE with auto precharge
function is engaged. The device starts an auto precharge at the clock rising edge tWR
cycles after the completion of the burst WRITE.
Following a WRITE with auto precharge, an ACTIVATE command can be issued to the
same bank if the following two conditions are met:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto pre-
charge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Figure 59: WRITE Burst with Auto Precharge – WL = 1, BL = 4
Bank n
col addr Col addr
WRITE NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 1
tWR
Transitioning data
NOP NOP NOP NOP NOP
DIN A0 DIN A1 DIN A2 DIN A3
ACTIVATE NOP
Bank n
row addr Row addr
≥tRPpb
Table 44: PRECHARGE and Auto Precharge Clarification
From
Command To Command Minimum Delay Between Commands Unit Notes
READ PRECHARGE to same bank as READ BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1
PRECHARGE ALL BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1
BST PRECHARGE to same bank as READ 1 CLK 1
PRECHARGE ALL 1 CLK 1
READ w/AP PRECHARGE to same bank as READ w/AP BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1, 2
PRECHARGE ALL BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1
ACTIVATE to same bank as READ w/AP BL/2 + MAX(2, RU(tRTP/tCK)) - 2 + RU(tRPpb/
tCK)
CLK 1
WRITE or WRITE w/AP (same bank) Illegal CLK 3
WRITE or WRITE w/AP (different bank) RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1 CLK 3
READ or READ w/AP (same bank) Illegal CLK 3
READ or READ w/AP (different bank) BL/2 CLK 3
WRITE PRECHARGE to same bank as WRITE WL + BL/2 + RU(tWR/tCK) + 1 CLK 1
PRECHARGE ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1
BST PRECHARGE to same bank as WRITE WL + RU(tWR/tCK) + 1 CLK 1
PRECHARGE ALL WL + RU(tWR/tCK) + 1 CLK 1
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
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Table 44: PRECHARGE and Auto Precharge Clarification (Continued)
From
Command To Command Minimum Delay Between Commands Unit Notes
WRITE w/AP PRECHARGE to same bank as WRITE w/AP WL + BL/2 + RU(tWR/tCK) + 1 CLK 1, 2
PRECHARGE ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1
ACTIVATE to same bank as WRITE w/AP WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRPpb/tCK) CLK 1
WRITE or WRITE w/AP (same bank) Illegal CLK 3
WRITE or WRITE w/AP (different bank) BL/2 CLK 3
READ or READ w/AP (same bank) Illegal CLK 3
READ or READ w/AP (different bank) WL + BL/2 + RU(tWTR/tCK) + 1 CLK 3
PRECHARGE PRECHARGE to same bank as PRECHARGE 1 CLK 1
PRECHARGE ALL 1 CLK 1
PRECHARGE
ALL
PRECHARGE 1 CLK 1
PRECHARGE ALL 1 CLK 1
Notes: 1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE
command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank.
The PRECHARGE period is satisfied after tRP, depending on the latest PRECHARGE com-
mand issued to that bank.
2. Any command issued during the specified minimum delay time is illegal.
3. After READ with auto precharge, seamless READ operations to different banks are sup-
ported. After WRITE with auto precharge, seamless WRITE operations to different banks
are supported. READ with auto precharge and WRITE with auto precharge must not be
interrupted or truncated.
REFRESH Command
The REFRESH command is initiated with CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH
at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at the ris-
ing edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising edge of
the clock. Per-bank REFRESH is only supported in devices with eight banks.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to
the bank scheduled by the bank counter in the memory device. The bank sequence for
per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The
bank count is synchronized between the controller and the SDRAM by resetting the
bank count to zero. Synchronization can occur upon issuing a RESET command or at
every exit from self refresh.
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met:
•tRFCab has been satisfied after the prior REFab command
•tRFCpb has been satisfied after the prior REFpb command
•tRP has been satisfied after the prior PRECHARGE command to that bank
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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•tRRD has been satisfied after the prior ACTIVATE command (if applicable, for exam-
ple after activating a row in a different bank than the one affected by the REFpb com-
mand)
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb), howev-
er, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or WRITE command.
When the per-bank REFRESH cycle has completed, the affected bank will be in the idle
state.
After issuing REFpb, the following conditions must be met:
•tRFCpb must be satisfied before issuing a REFab command
•tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank
•tRRD must be satisfied before issuing an ACTIVATE command to a different bank
•tRFCpb must be satisfied before issuing another REFpb command
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All
banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL
command prior to issuing an all-bank REFRESH command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. The REFab command
must not be issued to the device until the following conditions have been met:
•tRFCab has been satisfied following the prior REFab command
•tRFCpb has been satisfied following the prior REFpb command
•tRP has been satisfied following the prior PRECHARGE commands
After an all-bank REFRESH cycle has completed, all banks will be idle. After issuing RE-
Fab:
•tRFCab latency must be satisfied before issuing an ACTIVATE command
•tRFCab latency must be satisfied before issuing a REFab or REFpb command
Table 45: REFRESH Command Scheduling Separation Requirements
Symbol
Minimum
Delay
From To Notes
tRFCab REFab REFab
ACTIVATE command to any bank
REFpb
tRFCpb REFpb REFab
ACTIVATE command to same bank as REFpb
REFpb
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Table 45: REFRESH Command Scheduling Separation Requirements (Con-
tinued)
Symbol
Minimum
Delay
From To Notes
tRRD REFpb ACTIVATE command to a different bank than REFpb
ACTIVATE REFpb 1
ACTIVATE command to a different bank than the prior
ACTIVATE command
Note: 1. A bank must be in the idle state before it is refreshed, so REFab is prohibited following
an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle
state.
Mobile LPDDR2 devices provide significant flexibility in scheduling REFRESH com-
mands as long as the required boundary conditions are met (see Figure 64 (page 88)).
In the most straightforward implementations, a REFRESH command should be sched-
uled every tREFI. In this case, self refresh can be entered at any time.
Users may choose to deviate from this regular refresh pattern, for instance, to enable a
period in which no refresh is required. As an example, using a 1Gb LPDDR2 device, the
user can choose to issue a refresh burst of 4096 REFRESH commands at the maximum
supported rate (limited by tREFBW), followed by an extended period without issuing
any REFRESH commands, until the refresh window is complete. The maximum suppor-
ted time without REFRESH commands is calculated as follows: tREFW - (R/8) × tREFBW
= tREFW - R × 4 × tRFCab.
For example, a 1Gb device at TC ≤ 85˚C can be operated without a refresh for up to 32ms
- 4096 × 4 × 130ns ≈ 30ms.
Both the regular and the burst/pause patterns can satisfy refresh requirements if they
are repeated in every 32ms window. It is critical to satisfy the refresh requirement in
every rolling refresh window during refresh pattern transitions. The supported transi-
tion from a burst pattern to a regular distributed pattern is shown in Figure 61 (page
85). If this transition occurs immediately after the burst refresh phase, all rolling
tREFW intervals will meet the minimum required number of REFRESH commands.
A nonsupported transition is shown in Figure 62 (page 86). In this example, the regu-
lar refresh pattern starts after the completion of the pause phase of the burst/pause re-
fresh pattern. For several rolling tREFW intervals, the minimum number of REFRESH
commands is not satisfied.
Understanding this pattern transition is extremely important, even when only one pat-
tern is employed. In self refresh mode, a regular distributed refresh pattern must be as-
sumed. Micron recommends entering self refresh mode immediately following the
burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the
burst phase (see Figure 63 (page 87)).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 60: Regular Distributed Refresh Pattern
0ms 32ms 64ms 96ms
tREFBW tREFBW
tREFI tREFI
4,096
4,097
8,192
8,193
12,288
12,289
16,384
Notes: 1. Compared to repetitive burst REFRESH with subsequent REFRESH pause.
2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has
one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command
per 0.52μs, followed by ≈ 30ms without any REFRESH command.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 61: Supported Transition from Repetitive REFRESH Burst
0ms 32ms 64ms 96ms
tREFBW tREFBW
tREFI tREFI
4,096
4,097
8,192
10,240
12,288
16,384
Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has
one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command
per 0.52μs, followed by ≈ 30ms without any REFRESH command.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 62: Nonsupported Transition from Repetitive REFRESH Burst
0ms 32ms 64ms 96ms
tREFBW tREFBW
tREFI tREFI
tREFW = 32ms2
Insufficient REFRESH commands
in this refresh window!
4,096
4,097
8,192
8,193
10,240
12,288
Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern.
2. There are only ≈ 2048 REFRESH commands in the indicated tREFW window. This does not
provide the required minimum number of REFRESH commands (R).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 63: Recommended Self Refresh Entry and Exit
0ms 32ms
Self refresh
tREFBW tREFBW
4,096
4,097
8,192
Note: 1. In conjunction with a burst/pause refresh pattern.
REFRESH Requirements
1. Minimum Number of REFRESH Commands
Mobile LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands with-
in any rolling refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85˚C). For actual
values per density and the resulting average refresh interval (tREFI), see Table 86 (page
150).
For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device
Temperature (MA[7:0] = 04h) table.
For devices supporting per-bank REFRESH, a REFab command can be replaced by a full
cycle of eight REFpb commands.
2. Burst REFRESH Limitation
To limit current consumption, a maximum of eight REFab commands can be issued in
any rolling tREFBW (tREFBW = 4 × 8 × tRFCab). This condition does not apply if REFpb
commands are used.
3. REFRESH Requirements and Self Refresh
If any time within a refresh window is spent in self refresh mode, the number of re-
quired REFRESH commands in that window is reduced to the following:
R´ = RU tSRF
tREFI
Where RU represents the round-up function.
= R - RU R × tSRF
tREFW
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 64: tSRF Definition
Example A1
CKE
Example B2
CKE
Example C3
CKE
Example D4
CKE
tSRF
tSRF
tREFW
tSRF2
tSRF1
tSRF
Exit self refresh modeEnter self refresh mode
Exit self refresh modeEnter self refresh mode
Exit self refresh modeEnter self refresh mode
Exit self refresh modeEnter self refresh mode
Exit self refresh mode
tREFW
tREFW
tREFW
Notes: 1. Time in self refresh mode is fully enclosed in the refresh window (tREFW).
2. At self refresh entry.
3. At self refresh exit.
4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 +
tSRF2.
Figure 65: All-Bank REFRESH Operation
AB
PRECHARGE NOP
T0 T1 T2 T3 T4 Tx Tx + 1 Ty Ty + 1
CK#
CK
CA[9:0]
CMD NOP REFab NOP REFab
≥tRPab ≥tRFCab ≥tRFCab
NOP Valid NOP
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
REFRESH Command
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Figure 66: Per-Bank REFRESH Operation
AB
PRECHARGE
REFRESH to bank 0
NOP
T0 T1 Tx Tx + 1 Tx + 2 Ty Ty + 1 Tz Tz + 1
CK#
CK
CA[9:0]
CMD NOP REFpb NOP REFpb
≥tRPab ≥tRFCpb ≥tRFCpb
NOP ACTIVATE NOP
Bank 1
Row A Row A
REFRESH to bank 1 ACTIVATE command
to bank 1
Notes: 1. Prior to T0, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of
the system is powered down. When in the self refresh mode, the device retains data
without external clocking. The device has a built-in timer to accommodate SELF RE-
FRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS#
LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock.
CKE must be HIGH during the clock cycle preceding a SELF REFRESH command. A
NOP command must be driven in the clock cycle following the SELF REFRESH com-
mand. After the power-down command is registered, CKE must be held LOW to keep
the device in self refresh mode.
Mobile LPDDR2 devices can operate in self refresh mode in both the standard and ex-
tended temperature ranges. These devices also manage self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power con-
sumption across the operating temperature range. See Table 4 for details.
After the device has entered self refresh mode, all external signals other than CKE are
“Don’t Care.” For proper self refresh operation, power supply pins (VDD1, VDD2, VDDQ,
and VDDCA) must be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is
turned off, VREFDQ must also be turned off. Prior to exiting self refresh, both VDDQ and
VREFDQ must be within their respective minimum/maximum operating ranges (see the
Single-Ended AC and DC Input Levels for DQ and DM table). VREFDQ can be at any level
between 0 and VDDQ; VREFCA can be at any level between 0 and VDDCA during self re-
fresh.
Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (see AC
and DC Logic Input Measurement Levels for Single-Ended Signals (page 127)). After en-
tering self refresh mode, the device initiates at least one all-bank REFRESH command
internally during tCKESR. The clock is internally disabled during SELF REFRESH opera-
tion to save power. The device must remain in self refresh mode for at least tCKESR. The
user can change the external clock frequency or halt the external clock one clock after
self refresh entry is registered; however, the clock must be restarted and stable before
the device can exit SELF REFRESH operation.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
SELF REFRESH Operation
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Exiting self refresh requires a series of commands. First, the clock must be stable prior
to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least
equal to the self refresh exit interval (tXSR), must be satisfied before a valid command
can be issued to the device. This provides completion time for any internal refresh in
progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP com-
mands must be registered on each rising clock edge during tXSR.
Using self refresh mode introduces the possibility that an internally timed refresh event
could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting
self refresh, at least one REFRESH command (one all-bank command or eight per-bank
commands) must be issued before issuing a subsequent SELF REFRESH command.
Figure 67: SELF REFRESH Operation
Exit
SR ValidNOPNOP
Enter
SR NOP
Enter self refresh mode
Input clock frequency can be changed
or clock can be stopped during self refresh.
Valid
CK/CK#
CKE
CS#
CMD
tCKESR (MIN) tXSR (MIN)
tIHCKE tIHCKE
tISCKE tISCKE
Exit self refresh mode
Don’t Care
Notes: 1. Input clock frequency can be changed or stopped during self refresh, provided that
upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the
clock frequency is between the minimum and maximum frequencies for the particular
speed grade.
2. The device must be in the all banks idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during
tXSR.
Partial-Array Self Refresh – Bank Masking
Devices in densities of 64Mb–512Mb are comprised of four banks; densities of 1Gb and
higher are comprised of eight banks. Each bank can be configured independently
whether or not a SELF REFRESH operation will occur in that bank. One 8-bit mode reg-
ister (accessible via the MRW command) is assigned to program the bank-masking sta-
tus of each bank up to eight banks. For bank masking bit assignments, see the MR16
PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables.
The mask bit to the bank enables or disables a refresh operation of the entire memory
space within the bank. If a bank is masked using the bank mask register, a REFRESH op-
eration to the entire bank is blocked and bank data retention is not guaranteed in self
refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask
bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the array
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
SELF REFRESH Operation
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space being refreshed within that bank is determined by the programmed status of the
segment mask bits.
Partial-Array Self Refresh – Segment Masking
Programming segment mask bits is similar to programming bank mask bits. For densi-
ties 1Gb and higher, eight segments are used for masking (see the MR17 PASR Segment
Mask (MA[7:0] = 011h) and MR17 PASR Segment Mask Definitions tables). A mode reg-
ister is used for programming segment mask bits up to eight bits. For densities less than
1Gb, segment masking is not supported.
When the mask bit to an address range (represented as a segment) is programmed as
“masked,” a REFRESH operation to that segment is blocked. Conversely, when a seg-
ment mask bit to an address range is unmasked, refresh to that segment is enabled.
A segment masking scheme can be used in place of or in combination with a bank
masking scheme. Each segment mask bit setting is applied across all banks. For seg-
ment masking bit assignments, see the tables noted above.
Table 46: Bank and Segment Masking Example
Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask (MR16) 01000001
Segment 0 0–M–––––M
Segment 1 0–M–––––M
Segment 2 1 M M M M M M M M
Segment 3 0–M–––––M
Segment 4 0–M–––––M
Segment 5 0–M–––––M
Segment 6 0–M–––––M
Segment 7 1 M M M M M M M M
Note: 1. This table provides values for an 8-bank device with REFRESH operations masked to
banks 1 and 7, and segments 2 and 7.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
SELF REFRESH Operation
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MODE REGISTER READ
The MODE REGISTER READ (MRR) command is used to read configuration and status
data from SDRAM mode registers. The MRR command is initiated with CS# LOW, CA0
LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode reg-
ister is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available
on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the ris-
ing edge of the clock where MRR is issued. Subsequent data beats contain valid but un-
defined content, except in the case of the DQ calibration function, where subsequent
data beats contain valid content as described in Table 48 (page 97). All DQS are tog-
gled for the duration of the mode register READ burst.
The MRR command has a burst length of four. MRR operation (consisting of the MRR
command and the corresponding data traffic) must not be interrupted. The MRR com-
mand period (tMRR) is two clock cycles.
Figure 68: MRR Timing – RL = 3, tMRR = 2
Register
A
Register
A
MRR1NOP2NOP2
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ[7:0]3
RL = 3
MRR1Valid
tMRR = 2 tMRR = 2
DQ[MAX:8]
Register
BRegister
B
DOUT BDOUT A
Transitioning data Undefined
Notes: 1. MRRs to DQ calibration registers MR32 and MR40 are described in DQ Calibration (page
96).
2. Only the NOP command is supported during tMRR.
3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain
valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration
of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCKmax/tCK) + 4/2 + 1 clock cycles.
READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ com-
mand, the MRR command must not be issued before BL/2 clock cycles have completed.
Following a WRITE command, the MRR command must not be issued before WL + 1 +
BL/2 + RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is trunca-
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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ted with a BST command, the effective burst length of the truncated burst should be
used for the BL value.
Figure 69: READ to MRR Timing – RL = 3, tMRR = 2
Bank m
col addr a Col addr a
READ NOP2
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ[7:0]
DQ[MAX:8]
RL = 3
Transitioning data Undefined
tMRR = 2
BL/21
DOUT BDOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Valid
Register
B
Register
B
MRR
Notes: 1. The minimum number of clock cycles from the burst READ command to the MRR com-
mand is BL/2.
2. Only the NOP command is supported during tMRR.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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Figure 70: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4
Bank n
col addr a Col addr a
WRITE
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ
WL = 3
tWTR
Transitioning data
tMRR = 2
RL = 3
DIN A0 DIN A1 DIN A2 DIN A3
Valid
Register
B
Register
B
MRR1NOP2
Notes: 1. The minimum number of clock cycles from the burst WRITE command to the MRR com-
mand is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. Only the NOP command is supported during tMRR.
Temperature Sensor
Mobile LPDDR2 devices feature a temperature sensor whose status can be read from
MR4. This sensor can be used to determine an appropriate refresh rate, determine
whether AC timing derating is required in the extended temperature range, and/or
monitor the operating temperature. Either the temperature sensor or the device operat-
ing temperature can be used to determine whether operating temperature require-
ments are being met (see Operating Temperature Range table).
Temperature sensor data can be read from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no
older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the operating temperature specification that applies for the standard or extended
temperature ranges (see table noted above). For example, TCASE could be above 85˚C
when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommo-
date the parameters in the temperature sensor definitions table.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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Table 47: Temperature Sensor Definitions and Operating Conditions
Parameter Description Symbol Min/Max Value Unit
System temperature
gradient
Maximum temperature gradient experi-
enced by the memory device at the temper-
ature of interest over a range of 2˚C
TempGradient MAX System-dependent ˚C/s
MR4 READ interval Time period between MR4 READs from the
system
ReadInterval MAX System-dependent ms
Temperature sensor
interval
Maximum delay between internal updates
of MR4
tTSI MAX 32 ms
System response
delay
Maximum response time from an MR4 READ
to the system response
SysRespDelay MAX System-dependent ms
Device temperature
margin
Margin above maximum temperature to
support controller response
TempMargin MAX 2 ˚C
Mobile LPDDR2 devices accommodate the temperature margin between the point at
which the device temperature enters the extended temperature range and the point at
which the controller reconfigures the system accordingly. To determine the required
MR4 polling frequency, the system must use the maximum TempGradient and the max-
imum response time of the system according to the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C
For example, if TempGradient is 10˚C/s and the SysRespDelay is 1ms:
10°C
s × (ReadInterval + 32ms + 1ms) ≤ 2°C
In this case, ReadInterval must not exceed 167ms.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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Figure 71: Temperature Sensor Timing
Host MR4 READ
Device
Temp
Margin
MR4
Trip Level
2C
MR4 = 0x03
MRR MR4 = 0x03 MRR MR4 = 0x86
tTSI
< (tTSI + ReadInterval + SysRespDelay)
ReadInterval SysRespDelay
MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 Time
Temp
TempGradient
Temperture sensor update
DQ Calibration
Mobile LPDDR2 devices feature a DQ calibration function that outputs one of two pre-
defined system timing calibration patterns. For x16 devices, pattern A (MRR to MRR32),
and pattern B (MRR to MRR40), will return the specified pattern on DQ0 and DQ8; x32
devices return the specified pattern on DQ0, DQ8, DQ16, and DQ24.
For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the
MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the
same information as DQ0 during the MRR burst. MRR DQ calibration commands can
occur only in the idle state.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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Figure 72: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2
MRR NOP1NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
CA[9:0]
CMD
DQS#
DQS
DQ0
DQ[7:1]
DQ8
DQ[15:9]
DQ16
DQ[23:17]
DQ24
DQ[31:25]
RL = 3
Transitioning data Optionally driven the same as DQ0 or 0b
tMRR = 2
tMRR = 2
00111010
Reg 40Reg 40Reg 32Reg 32
MRR
00111010
00111010
00111010
00111010
00111010
00111010
00111010
Pattern A Pattern B
x32
x16
Note: 1. Only the NOP command is supported during tMRR.
Table 48: Data Calibration Pattern Description
Pattern MR#
Bit Time
0
Bit Time
1
Bit Time
2
Bit Time
3Description
Pattern A MR32 1 0 1 0 Reads to MR32 return DQ calibration pattern A
Pattern B MR40 0 0 1 1 Reads to MR40 return DQ calibration pattern B
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER READ
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MODE REGISTER WRITE Command
The MODE REGISTER WRITE (MRW) command is used to write configuration data to
the mode registers. The MRW command is initiated with CS# LOW, CA0 LOW, CA1 LOW,
CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by
CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained in
CA9f–CA2f. The MRW command period is defined by tMRW. MRWs to read-only regis-
ters have no impact on the functionality of the device.
MRW can only be issued when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
Figure 73: MODE REGISTER WRITE Timing – RL = 3, tMRW = 5
MR dataMR addr
MRW NOP2MRW
T0 T1 T2 Tx Tx + 1 Tx + 2 Ty1Ty + 1 Ty + 2
CK#
CK
CA[9:0]
CMD Valid
tMRW tMRW
MR dataMR addr
NOP2NOP2NOP2
Notes: 1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during tMRW.
Table 49: Truth Table for MRR and MRW
Current State Command Intermediate State Next State
All banks idle MRR Reading mode register, all banks idle All banks idle
MRW Writing mode register, all banks idle All banks idle
MRW (RESET) Resetting, device auto initialization All banks idle
Bank(s) active MRR Reading mode register, bank(s) idle Bank(s) active
MRW Not allowed Not allowed
MRW (RESET) Not allowed Not allowed
MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (reset-
ting) state in the power-on initialization sequence (see 2. RESET Command under Pow-
er-Up (page 47)). The MRW RESET command can be issued from the idle state. This
command resets all mode registers to their default values. Only the NOP command is
supported during tINIT4. After MRW RESET, boot timings must be observed until the
device initialization sequence is complete and the device is in the idle state. Array data
is undefined after the MRW RESET command has completed.
For MRW RESET timing, see Figure 33 (page 49).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER WRITE Command
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MRW ZQ Calibration Commands
The MRW command is used to initiate a ZQ calibration command that calibrates output
driver impedance across process, temperature, and voltage. LPDDR2-S4 devices sup-
port ZQ calibration. To achieve tighter tolerances, proper ZQ calibration must be per-
formed.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET,
tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for
resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and
tZQCS is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table
for ZQ calibration command code definitions.
ZQINIT must be performed for LPDDR2 devices. ZQINIT provides an output impe-
dance accuracy of ±15%. After initialization, the ZQ calibration long (ZQCL) can be used
to recalibrate the system to an output impedance accuracy of ±15%. A ZQ calibration
short (ZQCS) can be used periodically to compensate for temperature and voltage drift
in the system.
ZQRESET resets the output impedance calibration to a default accuracy of ±30% across
process, voltage, and temperature. This command is used to ensure output impedance
accuracy to ±30% when ZQCS and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output im-
pedance errors within tZQCS for all speed bins, assuming the maximum sensitivities
specified in Table 80 and Table 81 (page 142) are met. The appropriate interval between
ZQCS commands can be determined using these tables and system-specific parame-
ters.
Mobile LPDDR2 devices are subject to temperature drift rate (Tdriftrate) and voltage drift
rate (Vdriftrate) in various applications. To accommodate drift rates and calculate the
necessary interval between ZQCS commands, apply the following formula:
ZQcorrection
(Tsens × Tdriftrate) + (V
sens × Vdriftrate)
Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and volt-
age sensitivities.
For example, if Tsens = 0.75%/˚C, Vsens = 0.20%/mV, Tdriftrate = 1˚C/sec, and Vdriftrate =
15 mV/sec, then the interval between ZQCS commands is calculated as:
1.5
(0.75 × 1) + (0.20 × 15) = 0.4s
A ZQ calibration command can only be issued when the device is in the idle state with
all banks precharged.
No other activities can be performed on the data bus during calibration periods
(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to accurately calibrate
output impedance. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any giv-
en time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER WRITE Command
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In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT,
tZQCS, and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to VDDCA. In this situation,
the device must ignore ZQ calibration commands and the device will use the default
calibration settings.
Figure 74: ZQ Timings
MR dataMR addr
MRW NOP
T0 T1 T2 T3 T4 T5 Tx Tx + 1 Tx + 2
CK#
CK
CA[9:0]
CMD Valid
tZQINIT
NOP NOP NOP NOP
MRW
CMD Valid
tZQCS
MRW
CMD Valid
tZQCL
MRW
CMD Valid
tZQRESET
ZQINIT
ZQCS
ZQCL
ZQRESET
NOP NOP NOP NOP NOP
NOP NOP NOP NOP NOP
NOP NOP NOP NOP NOP
Notes: 1. Only the NOP command is supported during ZQ calibrations.
2. CKE must be registered HIGH continuously during the calibration period.
3. All devices connected to the DQ bus should be High-Z during the calibration process.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
MODE REGISTER WRITE Command
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ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be
connected between the ZQ pin and ground. A single resistor can be used for each device
or one resistor can be shared between multiple devices if the ZQ calibration timings for
each device do not overlap. The total capacitive loading on the ZQ pin must be limited
(see the Input/Output Capacitance table).
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS# is HIGH at
the rising edge of clock. A NOP command must be driven in the clock cycle following
power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE opera-
tions are in progress. CKE can go LOW while any other operations such as ACTIVATE,
PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down IDD
specification will not be applied until such operations are complete.
If power-down occurs when all banks are idle, this mode is referred to as idle power-
down; if power-down occurs when there is a row active in any bank, this mode is refer-
red to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, and
CKE. In power-down mode, CKE must be held LOW; all other input signals are “Don’t
Care.” CKE LOW must be maintained until tCKE is satisfied. VREFCA must be maintained
at a valid level during power-down.
VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be
turned off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their re-
spective minimum/maximum operating ranges (see AC and DC Operating Conditions).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is only limited by the refresh requirements outlined in REFRESH
Command.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS# HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until tCKE is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit laten-
cy is defined in the AC Timing section.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 75: Power-Down Entry and Exit Timing
Exit
PD ValidNOPNOP
Enter
PD NOP
Enter power-down mode
Input clock frequency can be changed
or the input clock can be stopped during power-down.
1
Valid
CK/CK#
CKE
CS#
CMD
tCKE
(MIN) tXP
(MIN)
tCKE
(MIN)
2 tCK (MIN)
tIHCKE tIHCKE
Exit power-down mode
Don’t Care
tISCKE tISCKE
Note: 1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified fre-
quencies for the speed grade in use, and that prior to power-down exit, a minimum of
two stable clocks complete.
Figure 76: CKE Intensive Environment
CK#
CK
CKE
tCKE
tCKE tCKE tCKE
Figure 77: REFRESH-to-REFRESH Timing in CKE Intensive Environments
CK#
CK
CKE
CMD
tCKE
tCKE tCKE tCKE
REFRESH REFRESH
tXP tREFI
tXP
Note: 1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are en-
sured.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 78: READ to Power-Down Entry
CK#
CK
CKE1, 2
T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9
CMD
DQ
DQS#
DQS
READ
DOUT DOUT DOUT DOUT
RL tISCKE
CK#
CK
CKE1, 2
T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9
CMD
DQ
DQS#
DQS
READ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
RL tISCKE
BL = 4
BL = 8
Notes: 1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at (RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1) clock cycles after
the clock on which the READ command is registered.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 79: READ with Auto Precharge to Power-Down Entry
CK#
CK
CKE1, 2
T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9
CMD
DQ
DQS#
DQS
READ w/AP PRE4
DOUT DOUT DOUT DOUT
RL tISCKE
BL/23
READ w/AP PRE4
BL/23
CK#
CK
CKE1, 2
T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9
CMD
DQ
DQS#
DQS
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
RL tISCKE
BL = 4
BL = 8
Notes: 1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the
clock on which the READ command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
4. Start internal PRECHARGE.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 80: WRITE to Power-Down Entry
CK#
CK
CKE1
T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6
CMD
DQ
DQS#
DQS
WRITE
DIN DIN DIN DIN
WL
tWR
tWR
CK#
CK
CKE1
T0 T1 Tm Tm +m1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4
CMD
DQ
DQS#
DQS
WRITE
DIN DIN DIN DIN DIN DIN DIN DIN
WL tISCKE
BL/2
BL/2
tISCKE
BL = 4
BL = 8
Note: 1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK)) clock cycles after the clock
on which the WRITE command is registered.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 81: WRITE with Auto Precharge to Power-Down Entry
CK#
CK
CKE1
T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6
CMD
DQ
DQS#
DQS
WRITE w/AP PRE2
DIN DIN DIN DIN
WL
BL/2
BL/2
CK#
CK
CKE1
T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4
CMD
DQ
DQS#
DQS
DIN DIN DIN DIN DIN DIN DIN DIN
WL
tISCKE
tWR
tWR
PRE2
tISCKE
BL = 4
BL = 8
WRITE w/AP
Notes: 1. CKE can be registered LOW at (WL + 1 + BL/2 + RU(tWR/tCK + 1) clock cycles after the
WRITE command is registered.
2. Start internal PRECHARGE.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 82: REFRESH Command to Power-Down Entry
CK#
CK
CKE1
CMD
tCKE
REFRESH
tCKE
tIHCKE
tISCKE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Note: 1. CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
Figure 83: ACTIVATE Command to Power-Down Entry
CK#
CK
CKE1
CMD
tCKE
ACTIVATE
tCKE
tIHCKE
tISCKE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Note: 1. CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is regis-
tered.
Figure 84: PRECHARGE Command to Power-Down Entry
CK#
CK
CKE1
CMD
tCKE
PRE
tCKE
tIHCKE
tISCKE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Note: 1. CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is regis-
tered.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
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Figure 85: MRR Command to Power-Down Entry
CK#
CK
CKE1
T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9
CMD
DQ
DQS#
DQS
MRR
DOUT DOUT DOUT DOUT
RL tISCKE
Note: 1. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the
clock on which the MRR command is registered.
Figure 86: MRW Command to Power-Down Entry
CK#
CK
CKE1
CMD
tMRW
MRW
tISCKE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Note: 1. CKE can be registered LOW tMRW after the clock on which the MRW command is regis-
tered.
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS# LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. The NOP command
must be driven in the clock cycle following power-down entry. CKE must not go LOW
while MRR or MRW operations are in progress. CKE can go LOW while other operations
such as ACTIVATE, auto precharge, PRECHARGE, or REFRESH are in progress, however,
deep power-down IDD specifications will not be applied until those operations com-
plete. The contents of the array will be lost upon entering DPD mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. VREFDQ can be at any level between 0
and VDDQ, and VREFCA can be at any level between 0 and VDDCA during DPD. All power
supplies (including VREF) must be within the specified limits prior to exiting DPD (see
AC and DC Operating Conditions).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Deep Power-Down
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To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be sta-
ble. To resume operation, the device must be fully reinitialized using the power-up initi-
alization sequence.
Figure 87: Deep Power-Down Entry and Exit Timing
RESETNOP
Enter
DPD NOP
Enter DPD mode
Input clock frequency can be changed
or the input clock can be stopped during DPD.
NOP
CK/CK#
CKE
CS#
CMD
tDPD
tINIT31, 2
tIHCKE
tISCKE
tRP
tISCKE
Exit DPD mode
Don’t Care
2 tCK (MIN)
Exit
DPD
Notes: 1. The initialization sequence can start at any time after Tx + 1.
2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode
Register Definition.
Input Clock Frequency Changes and Stop Events
Input Clock Frequency Changes and Clock Stop with CKE LOW
During CKE LOW, Mobile LPDDR2 devices support input clock frequency changes and
clock stop under the following conditions:
• Refresh requirements are met
• Only REFab or REFpb commands can be in process
• Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre-
quency
• Related timing conditions,tRCD and tRP, have been met prior to changing the fre-
quency
• The initial clock frequency must be maintained for a minimum of two clock cycles af-
ter CKE goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to
CKE going HIGH
For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock
cycle.
After the input clock frequency is changed and CKE is held HIGH, additional MRW
commands may be required to set the WR, RL, etc. These settings may require adjust-
ment to meet minimum timing requirements at the target clock frequency.
For clock stop, CK is held LOW and CK# is held HIGH.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Input Clock Frequency Changes and Stop Events
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Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, LPDDR2 devices support input clock frequency changes and clock
stop under the following conditions:
• REFRESH requirements are met
• Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have
completed, including any associated data bursts, prior to changing the frequency
• Related timing conditions, tRCD, tWR, tWRA, tRP, tMRW, and tMRR, etc., are met
• CS# must be held HIGH
• Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)
for a minimum of 2 × tCK + tXP.
For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock
cycle.
After the input clock frequency is changed, additional MRW commands may be re-
quired to set the WR, RL, etc. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK is held LOW and CK# is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwan-
ted commands issued between operations. A NOP command can only be issued at
clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The
NOP command has two possible encodings: CS# HIGH at the clock rising edge N; and
CS# LOW with CA0, CA1, CA2 HIGH at the clock rising edge N.
The NOP command will not terminate a previous operation that is still in process, such
as a READ burst or WRITE burst cycle.
Simplified Bus Interface State Diagram
The state diagram (see Figure 88 (page 111)) provides a simplified illustration of the bus
interface, supported state transitions, and the commands that control them. For a com-
plete description of device behavior, use the information provided in the state diagram
with the truth tables and timing specifications.
The truth tables describe device behavior and applicable restrictions when considering
the actual state of all banks.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
NO OPERATION Command
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Figure 88: Simplified Bus Interface State Diagram
Power
applied
Resetting Self
refreshing
Refreshing
Power-on
Resetting
MR reading
Idle
MR reading
Active
MR reading
Active
power-down
Idle
power-down
Deep
power-down
Idle1
Active BST
BST
PR
Precharging
MR writing
Writing Reading
Reading
with
auto precharge
Writing
with
auto precharge
Resetting
power-down
RESET
MRR
RESET
MRR
MRW
MRRWR
RD
PD
PDX
PDX
PD
PDX
PD
DPDX
DPD
SREF
REF
WRA
WRA
RDA
RDA
SREFX
RDWR
Automatic sequence
Command sequence
PR = PRECHARGE
PRA = PRECHARGE ALL
ACT = ACTIVATE
WR(A) = WRITE (with auto precharge)
RD(A) = READ (with auto precharge)
BST = BURST TERMINATE
RESET = RESET is achieved through
MRW command
MRW = MODE REGISTER WRITE
MRR = MODE REGISTER READ
PD = enter power-down
PDX = exit power-down
SREF = enter self refresh
SREFX = exit self refresh
DPD = enter deep power-down
DPDX = exit deep power-down
REF = REFRESH
PR, PRA
ACT
Note: 1. All banks are precharged in the idle state.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
NO OPERATION Command
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Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an ille-
gal event, the device must be powered down and then restarted using the specified initi-
alization sequence before normal operation can continue.
Table 50: Command Truth Table
Notes 1–11 apply to all parameters conditions
Command
Command Pins CA Pins
CK
Edge
CKE
CS# CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK(n-1) CK(n)
MRW H H L L L L L MA0 MA1 MA2 MA3 MA4 MA5
H H X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
MRR H H L L L L H MA0 MA1 MA2 MA3 MA4 MA5
H H X MA6 MA7 X
REFRESH
(per bank)
HHLLLHL X
HHX X
REFRESH
(all banks)
HHLLLHH X
HHX X
Enter self
refresh
HLLLLH X
XLX X
ACTIVATE
(bank)
H H L L H R8 R9 R10 R11 R12 BA0 BA1 BA2
H H X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14
WRITE (bank) H H L H L L RFU RFU C1 C2 BA0 BA1 BA2
H H X AP C3 C4 C5 C6 C7 C8 C9 C10 C11
READ (bank) H H L H L H RFU RFU C1 C2 BA0 BA1 BA2
H H X AP C3 C4 C5 C6 C7 C8 C9 C10 C11
PRECHARGE
(bank)
HHLHHLHABX X BA0 BA1 BA2
HHX X
BST H H L H H L L X
HHX X
Enter DPD H L L H H L X
XLX X
NOP H H L H H H X
HHX X
Maintain PD,
SREF, DPD,
(NOP)
LLLHHH X
LLX X
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Table 50: Command Truth Table (Continued)
Notes 1–11 apply to all parameters conditions
Command
Command Pins CA Pins
CK
Edge
CKE
CS# CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK(n-1) CK(n)
NOP H H H X
HHX X
Maintain PD,
SREF, DPD,
(NOP)
LLH X
LLX X
Enter power-
down
HLH X
XLX X
Exit PD, SREF,
DPD
LHH X
XHX X
Notes: 1. All commands are defined by the current state of CS#, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during self refresh and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS# and CKE are sampled on the rising edge of the clock.
10. Per-bank refresh is only supported in devices with eight banks.
11. The least-significant column address C0 is not transmitted on the CA bus, and is inferred
to be zero.
Table 51: CKE Truth Table
Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care”
Current State CKEn-1 CKEnCS#
Command
nOperation nNext State Notes
Active
power-down
L L X X Maintain active power-down Active
power-down
L H H NOP Exit active power-down Active 6, 7
Idle power-down L L X X Maintain idle power-down Idle
power-down
L H H NOP Exit idle power-down Idle 6, 7
Resetting idle
power-down
L L X X Maintain resetting power-down Resetting
power-down
L H H NOP Exit resetting power-down Idle or resetting 6, 7, 8
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Table 51: CKE Truth Table (Continued)
Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care”
Current State CKEn-1 CKEnCS#
Command
nOperation nNext State Notes
Deep power-
down
L L X X Maintain deep power-down Deep
power-down
L H H NOP Exit deep power-down Power-on 9
Self refresh L L X X Maintain self refresh Self refresh
L H H NOP Exit self refresh Idle 10, 11
Bank(s) active H L H NOP Enter active power-down Active
power-down
All banks idle H L H NOP Enter idle power-down Idle
power-down
H L L Enter self
refresh
Enter self refresh Self refresh
H L L DPD Enter deep power-down Deep
power-down
Resetting H L H NOP Enter resetting power-down Resetting
power-down
Other states H H Refer to the command truth table
Notes: 1. Current state = the state of the device immediately prior to the clock rising edge n.
2. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
3. CKEn = the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the
previous clock edge.
4. CS#= the logic state of CS# at the clock rising edge n.
5. Command n = the command registered at clock edge n, and operation n is a result of
command n.
6. Power-down exit time (tXP) must elapse before any command other than NOP is issued.
7. The clock must toggle at least twice prior to the tXP period.
8. Upon exiting the resetting power-down state, the device will return to the idle state if
tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power Down.
10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued.
11. The clock must toggle at least twice prior to the tXSR time.
Table 52: Current State Bank n to Command to Bank n Truth Table
Notes 1–5 apply to all parameters and conditions
Current State Command Operation Next State Notes
Any NOP Continue previous operation Current state
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Table 52: Current State Bank n to Command to Bank n Truth Table (Continued)
Notes 1–5 apply to all parameters and conditions
Current State Command Operation Next State Notes
Idle ACTIVATE Select and activate row Active
Refresh (per bank) Begin to refresh Refreshing (per bank) 6
Refresh (all banks) Begin to refresh Refreshing (all banks) 7
MRW Load value to mode register MR writing 7
MRR Read value from mode register Idle, MR reading
RESET Begin device auto initialization Resetting 7, 8
PRECHARGE Deactivate row(s) in bank or banks Precharging 9, 10
Row active READ Select column and start read burst Reading
WRITE Select column and start write burst Writing
MRR Read value from mode register Active MR reading
PRECHARGE Deactivate row(s) in bank or banks Precharging 9
Reading READ Select column and start new read burst Reading 11, 12
WRITE Select column and start write burst Writing 11, 12, 13
BST Read burst terminate Active 14
Writing WRITE Select column and start new write burst Writing 11, 12
READ Select column and start read burst Reading 11, 12, 15
BST Write burst terminate Active 14
Power-on MRW RESET Begin device auto initialization Resetting 7, 9
Resetting MRR Read value from mode register Resetting MR reading
Notes: 1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP
has been met, if the previous state was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
Idle: The bank or banks have been precharged, and tRP has been met.
Active: A row in the bank has been activated, and tRCD has been met. No data bursts or
accesses and no register accesses are in progress.
Reading: A READ burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
Writing: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
NOP commands or supported commands to the other bank must be issued on any clock
edge occurring during these states. Supported commands to the other banks are deter-
mined by that bank’s current state, and the definitions given in Table 53 (page 116).
Precharge: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank is in the idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when tRCD is
met. After tRCD is met, the bank is in the active state.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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READ with AP enabled: Starts with registration of a READ command with auto pre-
charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state.
WRITE with AP enabled: Starts with registration of a WRITE command with auto pre-
charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP com-
mands must be applied to each rising clock edge during these states.
Refresh (per bank): Starts with registration of a REFRESH (per bank) command and ends
when tRFCpb is met. After tRFCpb is met, the bank is in the idle state.
Refresh (all banks): Starts with registration of a REFRESH (all banks) command and ends
when tRFCab is met. After tRFCab is met, the device is in the all banks idle state.
Idle MR reading: Starts with registration of the MRR command and ends when tMRR is
met. After tMRR is met, the device is in the all banks idle state.
Resetting MR reading: Starts with registration of the MRR command and ends when
tMRR is met. After tMRR is met, the device is in the all banks idle state.
Active MR reading: Starts with registration of the MRR command and ends when tMRR
is met. After tMRR is met, the bank is in the active state.
MR writing: Starts with registration of the MRW command and ends when tMRW is met.
After tMRW is met, the device is in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, the device is in the all banks idle state.
6. Bank-specific; requires that the bank is idle and no bursts are in progress.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. Not bank-specific.
9. This command may or may not be bank specific. If all banks are being precharged, they
must be in a valid state for precharging.
10. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
11. A command other than NOP should not be issued to the same bank while a burst READ
or burst WRITE with auto precharge is enabled.
12. The new READ or WRITE command could be auto precharge enabled or auto precharge
disabled.
13. A WRITE command can be issued after the completion of the READ burst; otherwise, a
BST must be issued to end the READ prior to asserting a WRITE command.
14. Not bank-specific. The BST command affects the most recent READ/WRITE burst started
by the most recent READ/WRITE command, regardless of bank.
15. A READ command can be issued after completion of the WRITE burst; otherwise, a BST
must be used to end the WRITE prior to asserting another READ command.
Table 53: Current State Bank n to Command to Bank m Truth Table
Notes 1–6 apply to all parameters and conditions
Current State
of Bank nCommand to Bank mOperation Next State for Bank mNotes
Any NOP Continue previous operation Current state of bank m
Idle Any Any command supported to bank m–7
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Table 53: Current State Bank n to Command to Bank m Truth Table (Continued)
Notes 1–6 apply to all parameters and conditions
Current State
of Bank nCommand to Bank mOperation Next State for Bank mNotes
Row activating,
active, or pre-
charging
ACTIVATE Select and activate row in bank mActive 8
READ Select column and start READ burst
from bank m
Reading 9
WRITE Select column and start WRITE burst to
bank m
Writing 9
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
MRR READ value from mode register Idle MR reading or active
MR reading
11, 12, 13
BST READ or WRITE burst terminates an on-
going READ/WRITE from/to bank m
Active 7
Reading
(auto precharge
disabled)
READ Select column and start READ burst
from bank m
Reading 9
WRITE Select column and start WRITE burst to
bank m
Writing 9, 14
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Writing
(auto precharge
disabled)
READ Select column and start READ burst
from bank m
Reading 9, 15
WRITE Select column and start WRITE burst to
bank m
Writing 9
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Reading with
auto precharge
READ Select column and start READ burst
from bank m
Reading 9, 16
WRITE Select column and start WRITE burst to
bank m
Writing 9, 14, 16
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Writing with
auto precharge
READ Select column and start READ burst
from bank m
Reading 9, 15, 16
WRITE Select column and start WRITE burst to
bank m
Writing 9, 16
ACTIVATE Select and activate row in bank mActive
PRECHARGE Deactivate row(s) in bank or banks Precharging 10
Power-on MRW RESET Begin device auto initialization Resetting 17, 18
Resetting MRR Read value from mode register Resetting MR reading
Notes: 1. This table applies when: the previous state was self refresh or power-down; after tXSR
or tXP has been met; and both CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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3. Current state definitions:
Idle: The bank has been precharged and tRP has been met.
Active: A row in the bank has been activated, tRCD has been met, no data bursts or ac-
cesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and the READ has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE
has not yet terminated or been terminated.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. A BST command cannot be issued to another bank; it applies only to the bank represen-
ted by the current state.
6. The states listed below must not be interrupted by any executable command. NOP com-
mands must be applied during each clock cycle while in these states:
Idle MRR: Starts with registration of the MRR command and ends when tMRR has been
met. After tMRR is met, the device is in the all banks idle state.
Reset MRR: Starts with registration of the MRR command and ends when tMRR has been
met. After tMRR is met, the device is in the all banks idle state.
Active MRR: Starts with registration of the MRR command and ends when tMRR has
been met. After tMRR is met, the bank is in the active state.
MRW: Starts with registration of the MRW command and ends when tMRW has been
met. After tMRW is met, the device is in the all banks idle state.
7. BST is supported only if a READ or WRITE burst is ongoing.
8. tRRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m.
9. READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
10. This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
11. MRR is supported in the row-activating state.
12. MRR is supported in the precharging state.
13. The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
14. A WRITE command can be issued after the completion of the READ burst; otherwise a
BST must be issued to end the READ prior to asserting a WRITE command.
15. A READ command can be issued after the completion of the WRITE burst; otherwise, a
BST must be issued to end the WRITE prior to asserting another READ command.
16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
17. Not bank-specific; requires that all banks are idle and no bursts are in progress.
18. RESET command is achieved through MODE REGISTER WRITE command.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Table 54: DM Truth Table
Functional Name DM DQ Notes
Write enable L Valid 1
Write inhibit H X 1
Note: 1. Used to mask write data, and is provided simultaneously with the corresponding input
data.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
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Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed below may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this document is not
implied. Exposure to absolute maximum rating conditions for extended periods may
adversely affect reliability.
Table 55: Absolute Maximum DC Ratings
Parameter Symbol Min Max Unit Notes
VDD1 supply voltage relative to VSS VDD1 –0.4 +2.3 V 1
VDD2 supply voltage relative to VSS VDD2 (1.2V) –0.4 +1.6 V 1
VDDCA supply voltage relative to VSSCA VDDCA –0.4 +1.6 V 1, 2
VDDQ supply voltage relative to VSSQ VDDQ –0.4 +1.6 V 1, 3
Voltage on any ball relative to VSS VIN, VOUT –0.4 +1.6 V
Storage temperature TSTG –55 +125 ˚C 4
Notes: 1. See 1. Voltage Ramp under Power-Up (page 47).
2. VREFCA 0.6 ≤ VDDCA; however, VREFCA may be ≥ VDDCA provided that VREFCA ≤ 300mV.
3. VREFDQ 0.6 ≤ VDDQ; however, VREFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV.
4. Storage temperature is the case surface temperature on the center/top side of the de-
vice. For measurement conditions, refer to the JESD51-2 standard.
Input/Output Capacitance
Table 56: Input/Output Capacitance
Note 1 applies to all parameters and conditions
Parameter Symbol
LPDDR2 1066-466 LPDDR2 400-200
Unit NotesMIN MAX MIN MAX
Input capacitance, CK and CK# CCK 1.0 2.0 1.0 2.0 pF 2, 3
Input capacitance delta, CK and CK# CDCK 0 0.20 0 0.25 pF 2, 3, 4
Input capacitance, all other input-
only pins
CI1.0 2.0 1.0 2.0 pF 2, 3, 5
Input capacitance delta, all other input-
only pins
CDI –0.40 +0.40 –0.50 +0.50 pF 2, 3, 6
Input/output capacitance, DQ, DM, DQS,
DQS#
CIO 1.25 2.5 1.25 2.5 pF 2, 3, 7, 8
Input/output capacitance delta, DQS,
DQS#
CDDQS 0 0.25 0 0.30 pF 2, 3, 8, 9
Input/output capacitance delta, DQ, DM CDIO –0.5 +0.5 –0.6 +0.6 pF 2, 3, 8, 10
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Electrical Specifications
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Table 56: Input/Output Capacitance (Continued)
Note 1 applies to all parameters and conditions
Parameter Symbol
LPDDR2 1066-466 LPDDR2 400-200
Unit NotesMIN MAX MIN MAX
Input/output capacitance ZQ CZQ 0 2.5 0 2.5 pF 2, 3, 11
Notes: 1. TC –40˚C to +105˚C; VDDQ = 1.14–1.3V; VDDCA = 1.14–1.3V; VDD1 = 1.7–1.95V; VDD2 = 1.28–
1.42V.
2. This parameter applies to die devices only (does not include package capacitance).
3. This parameter is not subject to production testing. It is verified by design and character-
ization. The capacitance is measured according to JEP147 (procedure for measuring in-
put capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, VSSCA, and
VSSQ applied; all other pins are left floating.
4. Absolute value of CCK - CCK#.
5. CI applies to CS#, CKE, and CA[9:0].
6. CDI = CI - 0.5 × (CCK + CCK#).
7. DM loading matches DQ and DQS.
8. MR3 I/O configuration drive strength OP[3:0] = 0001b (34.3 ohm typical).
9. Absolute value of CDQS and CDQS#.
10. CDIO = CIO - 0.5 × (CDQS + CDQS#) in byte-lane.
11. Maximum external load capacitance on ZQ pin: 5pF.
Electrical Specifications – IDD Specifications and Conditions
The following definitions and conditions are used in the IDD measurement tables unless
stated otherwise:
• LOW: VIN ≤ VIL(DC)max
• HIGH: VIN ≥ V IH(DC)min
• STABLE: Inputs are stable at a HIGH or LOW level
• SWITCHING: See the following three tables
Table 57: Switching for CA Input Signals
Notes 1–3 apply to all parameters and conditions
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
Cycle N N + 1 N + 2 N + 3
CS# HIGH HIGH HIGH HIGH
CA0 H L L L L H H H
CA1 H H H L L L L H
CA2 H L L L L H H H
CA3 H H H L L L L H
CA4 H L L L L H H H
CA5 H H H L L L L H
CA6 H L L L L H H H
CA7 H H H L L L L H
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Electrical Specifications – IDD Specifications and Conditions
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Table 57: Switching for CA Input Signals (Continued)
Notes 1–3 apply to all parameters and conditions
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CK Rising/
CK#Falling
CK Falling/
CK# Rising
CA8 H L L L L H H H
CA9 H H H L L L L H
Notes: 1. CS# must always be driven HIGH.
2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.
3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measure-
ment for IDD values that require switching on the CA bus.
Table 58: Switching for IDD4R
Clock CKE CS#
Clock Cycle
Number Command CA[2:0] CA[9:3] All DQ
Rising H L N Read_Rising HLH LHLHLHL L
Falling H L N Read_Falling LLL LLLLLLL L
Rising H H N +1 NOP LLL LLLLLLL H
Falling H H N + 1 NOP HLH LHLLHLH L
Rising H L N + 2 Read_Rising HLH LHLLHLH H
Falling H L N + 2 Read_Falling LLL HHHHHHH H
Rising H H N + 3 NOP LLL HHHHHHH H
Falling H H N + 3 NOP HLH LHLHLHL L
Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Table 59: Switching for IDD4W
Clock CKE CS#
Clock Cycle
Number Command CA[2:0] CA[9:3] All DQ
Rising H L N Write_Rising LLH LHLHLHL L
Falling H L N Write_Falling LLL LLLLLLL L
Rising H H N +1 NOP LLL LLLLLLL H
Falling H H N + 1 NOP HLH LHLLHLH L
Rising H L N + 2 Write_Rising LLH LHLLHLH H
Falling H L N + 2 Write_Falling LLL HHHHHHH H
Rising H H N + 3 NOP LLL HHHHHHH H
Falling H H N + 3 NOP HLH LHLHLHL L
Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Electrical Specifications – IDD Specifications and Conditions
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Table 60: IDD Specification Parameters and Operating Conditions
Notes 1–3 apply to all parameters and conditions
Parameter/Condition Symbol Power Supply Notes
Operating one bank active-precharge current (SDRAM): tCK = tCKmin;
tRC = tRCmin; CKE is HIGH; CS# is HIGH between valid commands; CA bus in-
puts are switching; Data bus inputs are stable
IDD01 VDD1
IDD02 VDD2
IDD0in VDDCA, VDDQ 4
Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS# is HIGH;
All banks are idle; CA bus inputs are switching; Data bus inputs are stable
IDD2P1 VDD1
IDD2P2 VDD2
IDD2P,in VDDCA, VDDQ 4
Idle power-down standby current with clock stop: CK = LOW, CK# =
HIGH; CKE is LOW; CS# is HIGH; All banks are idle; CA bus inputs are stable;
Data bus inputs are stable
IDD2PS1 VDD1
IDD2PS2 VDD2
IDD2PS,in VDDCA, VDDQ 4
Idle non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS# is
HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta-
ble
IDD2N1 VDD1
IDD2N2 VDD2
IDD2N,in VDDCA, VDDQ 4
Idle non-power-down standby current with clock stopped: CK = LOW;
CK# = HIGH; CKE is HIGH; CS# is HIGH; All banks are idle; CA bus inputs are
stable; Data bus inputs are stable
IDD2NS1 VDD1
IDD2NS2 VDD2
IDD2NS,in VDDCA, VDDQ 4
Active power-down standby current: tCK = tCKmin; CKE is LOW; CS# is
HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are
stable
IDD3P1 VDD1
IDD3P2 VDD2
IDD3P,in VDDCA, VDDQ 4
Active power-down standby current with clock stop: CK = LOW, CK# =
HIGH; CKE is LOW; CS# is HIGH; One bank is active; CA bus inputs are stable;
Data bus inputs are stable
IDD3PS1 VDD1
IDD3PS2 VDD2
IDD3PS,in VDDCA, VDDQ 4
Active non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS#
is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are
stable
IDD3N1 VDD1
IDD3N2 VDD2
IDD3N,in VDDCA, VDDQ 4
Active non-power-down standby current with clock stopped: CK =
LOW, CK# = HIGH CKE is HIGH; CS# is HIGH; One bank is active; CA bus inputs
are stable; Data bus inputs are stable
IDD3NS1 VDD1
IDD3NS2 VDD2
IDD3NS,in VDDCA, VDDQ 4
Operating burst READ current: tCK = tCKmin; CS# is HIGH between valid
commands; One bank is active; BL = 4; RL = RL (MIN); CA bus inputs are
switching; 50% data change each burst transfer
IDD4R1 VDD1
IDD4R2 VDD2
IDD4R,in VDDCA
IDD4RQ VDDQ 5
Operating burst WRITE current: tCK = tCKmin; CS# is HIGH between valid
commands; One bank is active; BL = 4; WL = WLmin; CA bus inputs are switch-
ing; 50% data change each burst transfer
IDD4W1 VDD1
IDD4W2 VDD2
IDD4W,in VDDCA, VDDQ 4
All-bank REFRESH burst current: tCK = tCKmin; CKE is HIGH between valid
commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data
bus inputs are stable
IDD51 VDD1
IDD52 VDD2
IDD5IN VDDCA, VDDQ 4
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Electrical Specifications – IDD Specifications and Conditions
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Table 60: IDD Specification Parameters and Operating Conditions (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter/Condition Symbol Power Supply Notes
All-bank REFRESH average current (–30˚C to +85˚C): tCK = tCKmin; CKE is
HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data
bus inputs are stable
IDD5AB1 VDD1
IDD5AB2 VDD2
IDD5AB,in VDDCA, VDDQ 4
All-bank REFRESH average current (+85˚C to +105˚C): tCK = tCKmin; CKE
is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching;
Data bus inputs are stable
IDD5ABET1 VDD1
IDD5ABET2 VDD2
IDD5AB,ETin VDDCA, VDDQ 4, 8
Per-bank REFRESH average current (–30˚C to +85˚C): tCK = tCKmin; CKE is
HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching;
Data bus inputs are stable
IDD5PB1 VDD1 6
IDD5PB2 VDD2 6
IDD5PB,in VDDCA, VDDQ 4, 6
Per-bank REFRESH average current (+85˚C to +105˚C): tCK = tCKmin; CKE
is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching;
Data bus inputs are stable
IDD5PBET1 VDD1 6
IDD5PBET2 VDD2 6
IDD5PB,ETin VDDCA, VDDQ 4, 6, 8
Self refresh current (–30˚C to +85˚C): CK = LOW, CK# = HIGH; CKE is LOW;
CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh
rate
IDD61 VDD1 7
IDD62 VDD2 7
IDD6IN VDDCA, VDDQ 4, 7
Self refresh current (+85˚C to +105˚C): CK = LOW, CK# = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable
IDD6ET1 VDD1 7, 8
IDD6ET2 VDD2 7, 8
IDD6ET,in VDDCA, VDDQ 4, 7, 8
Deep power-down current: CK = LOW, CK# = HIGH; CKE is LOW; CA bus in-
puts are stable; Data bus inputs are stable
IDD81 VDD1 8
IDD82 VDD2 8
IDD8IN VDDCA, VDDQ 4, 8
Notes: 1. IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
3. The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh, before going into the extended temperature range.
4. Measured currents are the sum of VDDQ and VDDCA.
5. Guaranteed by design with output reference load and RON = 40 ohm.
6. Per-bank REFRESH is only applicable for LPDDR2-S4 device densities 1Gb or higher.
7. This is the general definition that applies to full-array self refresh.
8. IDD6ET, IDD5ABET, IDD5PBET, and IDD8 are typical values, are sampled only, and are not tes-
ted.
AC and DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the de-
vice must be initialized properly.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Operating Conditions
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Table 61: Recommended DC Operating Conditions
Symbol
LPDDR2-S4B
Power Supply UnitMin Typ Max
VDD111.70 1.80 1.95 Core power 1 V
VDD2 1.14 1.20 1.30 Core power 2 V
VDDCA 1.14 1.20 1.30 Input buffer power V
VDDQ 1.14 1.20 1.30 I/O buffer power V
Note: 1. VDD1 uses significantly less power than VDD2.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Operating Conditions
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Table 62: Input Leakage Current
Parameter/Condition Symbol Min Max Unit Notes
Input leakage current: For CA, CKE,
CS#, CK, CK#; Any input 0V ≤ VIN ≤ VDDCA;
(All other pins not under test = 0V)
IL–2 2 μA1
VREF supply leakage current: VREFDQ =
VDDQ/2, or VREFCA = VDDCA/2; (All other
pins not under test = 0V)
IVREF –1 1 μA2
Notes: 1. Although DM is for input only, the DM leakage must match the DQ and DQS/DQS# out-
put leakage specification.
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA
and VREFDQ pins should be minimal.
Table 63: Operating Temperature Range
Parameter/Condition Symbol Min Max Unit
WT temperature range TCASE1–30 +85 ˚C
AT temperature range –40 +105 ˚C
Notes: 1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
2. Some applications require operation in the maximum case temperature range, between
85˚C and 105˚C. For some LPDDR2 devices, derating may be necessary to operate in this
range (see the MR4 Device Temperature (MA[7:0] = 04h) table).
3. Either the device operating temperature or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor (page 94)). When using the temper-
ature sensor, the actual device case temperature may be higher than the TCASE rating
that applies for the operating temperature range. For example, TCASE could be above
85˚C when the temperature sensor indicates a temperature of less than 85˚C.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Operating Conditions
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AC and DC Logic Input Measurement Levels for Single-Ended Signals
Table 64: Single-Ended AC and DC Input Levels for CA and CS# Inputs
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VIHCA(AC) AC input logic HIGH VREF + 0.220 Note 2 VREF + 0.300 Note 2 V 1, 2
VILCA(AC) AC input logic LOW Note 2 VREF - 0.220 Note 2 VREF - 0.300 V 1, 2
VIHCA(DC) DC input logic HIGH VREF + 0.130 VDDCA VREF + 0.200 VDDCA V1
VILCA(DC) DC input logic LOW VSSCA VREF - 0.130 VSSCA VREF - 0.200 V 1
VREFCA(DC) Reference voltage for
CA and CS# inputs
0.49 × VDDCA 0.51 × VDDCA 0.49 × VDDCA 0.51 × VDDCA V 3, 4
Notes: 1. For CA and CS# input-only pins. VREF = VREFCA(DC).
2. See Overshoot and Undershoot Definition.
3. The AC peak noise on VREFCA could prevent VREFCA from deviating more than ±1% VDDCA
from VREFCA(DC) (for reference, approximately ±12mV).
4. For reference, approximately VDDCA/2 ±12mV.
Table 65: Single-Ended AC and DC Input Levels for CKE
Symbol Parameter Min Max Unit Notes
VIHCKE CKE input HIGH level 0.8 × VDDCA Note 1 V 1
VILCKE CKE input LOW level Note 1 0.2 × VDDCA V1
Note: 1. See Overshoot and Undershoot Definition.
Table 66: Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VIHDQ(AC) AC input logic HIGH VREF + 0.220 Note 2 VREF + 0.300 Note 2 V 1, 2
VILDQ(AC) AC input logic LOW Note 2 VREF - 0.220 Note 2 VREF - 0.300 V 1, 2
VIHDQ(DC) DC input logic HIGH VREF + 0.130 VDDQ VREF + 0.200 VDDQ V1
VILDQ(DC) DC input logic LOW VSSQ VREF - 0.130 VSSQ VREF - 0.200 V 1
VREFDQ(DC) Reference voltage for
DQ and DM inputs
0.49 × VDDQ 0.51 × VDDQ 0.49 × VDDQ 0.51 × VDDQ V 3, 4
Notes: 1. For DQ input-only pins. VREF = VREFDQ(DC).
2. See Overshoot and Undershoot Definition.
3. The AC peak noise on VREFDQ could prevent VREFDQ from deviating more than ±1% VDDQ
from VREFDQ(DC) (for reference, approximately ±12mV).
4. For reference, approximately. VDDQ/2 ±12mV.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
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VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages VREFCA and
VREFDQ are illustrated below. This figure shows a valid reference voltage VREF(t) as a
function of time. VDD is used in place of VDDCA for VREFCA, and VDDQ for VREFDQ. VREF(DC)
is the linear average of VREF(t) over a very long period of time (for example, 1 second)
and is specified as a fraction of the linear average of VDDQ or VDDCA, also over a very long
period of time (for example, 1 second). This average must meet the MIN/MAX require-
ments in Table 64 (page 127). Additionally, VREF(t) can temporarily deviate from VREF(DC)
by no more than ±1% VDD. VREF(t) cannot track noise on VDDQ or VDDCA if doing so
would force VREF outside these specifications.
Figure 89: VREF DC Tolerance and VREF AC Noise Limits
VREF(DC)
VREF(DC)max
VDD/2
VDD
VSS
VREF(DC)min
Voltage
Time
VREF(AC) noise VREF(t)
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and
VIL(DC) are dependent on VREF.
VREF DC variations affect the absolute voltage a signal must reach to achieve a valid
HIGH or LOW, as well as the time from which setup and hold times are measured. When
VREF is outside the specified levels, devices will function correctly with appropriate tim-
ing deratings as long as:
•V
REF is maintained between 0.44 x VDDQ (or VDDCA) and 0.56 x VDDQ (or VDDCA), and
• the controller achieves the required single-ended AC and DC input levels from instan-
taneous VREF (see Table 64 (page 127)).
System timing and voltage budgets must account for VREF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associ-
ated with VREF AC noise. Timing and voltage effects due to AC noise on VREF up to the
specified limit (±1% VDD) are included in LPDDR2 timings and their associated derat-
ings.
Input Signal
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
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Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal
0.380V
0.000V
0.470V
0.576V
0.588V
0.600V
0.612V
0.624V
0.730V
0.820V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
1.200V
1.550V
–0.350V
VDD
VDD + 0.35V
narrow pulse width
VSS - 0.35V
narrow pulse width
VSS
0.380V
0.470V
0.576V
0.588V
0.600V
0.612V
0.624V
0.730V
0.820V
Minimum VIL and VIH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and VIH levels with ringback
Notes: 1. Numbers reflect typical values.
2. For CA[9:0], CK, CK#, and CS# VDD stands for VDDCA. For DQ, DM, DQS, and DQS#, VDD
stands for VDDQ.
3. For CA[9:0], CK, CK#, and CS# VSS stands for VSSCA. For DQ, DM, DQS, and DQS#, VSS
stands for VSSQ.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
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Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal
0.300V
0.000V
0.400V
0.576V
0.588V
0.600V
0.612V
0.624V
0.800V
0.900V
VIL(AC)
VIL(DC)
VREF - AC noise
VREF - DC error
VREF + DC error
VREF + AC noise
VIH(DC)
VIH(AC)
1.200V
1.550V
–0.350V
VDD
VDD + 0.35V
narrow pulse width
VSS - 0.35V
narrow pulse width
VSS
0.300V
0.400V
0.576V
0.588V
0.600V
0.612V
0.624V
0.800V
0.900V
Minimum VIL and VIH levels
VIH(DC)
VIH(AC)
VIL(AC)
VIL(DC)
VIL and VIH levels with ringback
Notes: 1. Numbers reflect typical values.
2. For CA[9:0], CK, CK#, and CS# VDD stands for VDDCA. For DQ, DM, DQS, and DQS#, VDD
stands for VDDQ.
3. For CA[9:0], CK, CK#, and CS# VSS stands for VSSCA. For DQ, DM, DQS, and DQS#, VSS
stands for VSSQ.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
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AC and DC Logic Input Measurement Levels for Differential Signals
Figure 92: Differential AC Swing Time and tDVAC
tDVAC
tDVAC
1/2 cycle
Time
VIH,diff(AC)min
VIH,diff(DC)min
0.0
VIH,diff(DC)max
VIH,diff(AC)max
CK, CK#
DQS, DQS#
Differential Voltage
Table 67: Differential AC and DC Input Levels
For CK and CK#, VREF = VREFCA(DC); For DQS and DQS# VREF = VREFDQ(DC)
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VIH,diff(AC) Differential input
HIGH AC
2 × (VIH(AC) - VREF) Note 1 2 × (VIH(AC) - VREF) Note 1 V 2
VIL,diff(AC) Differential input
LOW AC
Note 1 2 × (VREF - VIL(AC)) Note 1 2 × (VREF - VIL(AC))V 2
VIH,diff(DC) Differential input
HIGH
2 × (VIH(DC) - VREF) Note 1 2 × (VIH(DC) - VREF) Note 1 V 3
VIL,diff(DC) Differential input
LOW
Note 1 2 × (VREF - VIL(DC)) Note 1 2 × (VREF - VIL(DC))V 3
Notes: 1. These values are not defined, however the single-ended signals CK, CK#, DQS, and DQS#
must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals and
must comply with the specified limitations for overshoot and undershoot (see Overshoot
and Undershoot Definition).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Differential
Signals
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2. For CK and CK#, use VIH/VIL(AC) of CA and VREFCA; for DQS and DQS#, use VIH/VIL(AC) of DQ
and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced
voltage level also applies.
3. Used to define a differential signal slew rate.
Table 68: CK/CK# and DQS/DQS# Time Requirements Before Ringback
(tDVAC)
Slew Rate (V/ns)
tDVAC (ps) at VIH/VILdiff(AC) =
440mV
tDVAC (ps) at VIH/VILdiff(AC) =
600mV
Min Min
> 4.0 175 75
4.0 170 57
3.0 167 50
2.0 163 38
1.8 162 34
1.6 161 29
1.4 159 22
1.2 155 13
1.0 150 0
< 1.0 150 0
Single-Ended Requirements for Differential Signals
Each individual component of a differential signal (CK, CK#, DQS, and DQS#) must also
comply with certain requirements for single-ended signals.
CK and CK# must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS, DQS# must
meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid transi-
tion.
The applicable AC levels for CA and DQ differ by speed bin.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Differential
Signals
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Figure 93: Single-Ended Requirements for Differential Signals
Time
VDDCA or VDDQ
VSSCA or VSSQ
VDDCA/2 or VDDQ/2
VSEH(AC)min
VSEH(AC)
VSEL(AC)max
VSEL(AC)
CK or DQS
Differential Voltage
Note that while CA and DQ signal requirements are referenced to VREF, the single-ended
components of differential signals also have a requirement with respect to
VDDQ/2 for DQS, and VDDCA/2 for CK.
The transition of single-ended signals through the AC levels is used to measure setup
time. For single-ended components of differential signals, the requirement to reach
VSEL(AC)max or VSEH(AC)min has no bearing on timing. This requirement does, however,
add a restriction on the common mode characteristics of these signals (see "Single-
Ended AC and DC Input Levels for CA and CS# Inputs" for CK/CK# single-ended re-
quirements, and "Single-Ended AC and DC Input Levels for DQ and DM" for DQ and
DQM single-ended requirements).
Table 69: Single-Ended Levels for CK, CK#, DQS, DQS#
Symbol Parameter
LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200
Unit NotesMin Max Min Max
VSEH(AC) Single-ended HIGH
level for strobes
(VDDQ/2) + 0.220 Note 1 (VDDQ/2) + 0.300 Note 1 V 2, 3
Single-ended HIGH
level for CK, CK#
(VDDCA/2) + 0.220 Note 1 (VDDCA/2) + 0.300 Note 1 V 2, 3
VSEL(AC) Single-ended LOW
level for strobes
Note 1 (VDDQ/2) - 0.220 Note 1 (VDDQ/2) + 0.300 V 2, 3
Single-ended LOW
level for CK, CK#
Note 1 (VDDCA/2) - 0.220 Note 1 (VDDCA/2) + 0.300 V 2, 3
Notes: 1. These values are not defined, however, the single-ended signals CK, CK#, DQS0, DQS#0,
DQS1, DQS#1, DQS2, DQS#2, DQS3, DQS#3 must be within the respective limits
(VIH(DC)max/ VIL(DC)min) for single-ended signals, and must comply with the specified limi-
tations for overshoot and undershoot (See Overshoot and Undershoot Definition).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Differential
Signals
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2. For CK and CK#, use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0] and DQS#[3:0]), use
VIH/VIL(AC) of DQ.
3. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on
VREFCA. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced level
applies.
Differential Input Crosspoint Voltage
To ensure tight setup and hold times as well as output skew parameters with respect to
clock and strobe, each crosspoint voltage of differential input signals (CK, CK#, DQS,
and DQS#) must meet the specifications in Table 69 (page 133). The differential input
crosspoint voltage (VIX) is measured from the actual crosspoint of the true signal and its
and complement to the midlevel between VDD and VSS.
Figure 94: VIX Definition
VDDCA, VDDQ
VSSCA, VSSQ
VDDCA/2,
VDDQ/2
VDDCA/2,
VDDQ/2
CK#, DQS#
VIX
CK, DQS
VDDCA, VDDQ
VSSCA, VSSQ
CK#, DQS#
VIX
VIX
CK, DQS
VIX
X
XX
X
Table 70: Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#)
Symbol Parameter
LPDDR2-1066 to LPDDR2-200
Unit NotesMin Max
VIXCA(AC) Differential input crosspoint voltage rela-
tive to VDDCA/2 for CK and CK#
–120 120 mV 1, 2
VIXDQ(AC) Differential input crosspoint voltage rela-
tive to VDDQ/2 for DQS and DQ#
–120 120 mV 1, 2
Notes: 1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differ-
ential input signals must cross.
2. For CK and CK#, VREF = VREFCA(DC). For DQS and DQS#, VREF = VREFDQ(DC).
Input Slew Rate
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Differential
Signals
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Table 71: Differential Input Slew Rate Definition
Description
Measured1
Defined byFrom To
Differential input slew rate for rising
edge (CK/CK# and DQS/DQS#)
VIL,diff,max VIH,diff,min [VIH,diff,min - VIL,diff,maxΔTRdiff
Differential input slew rate for falling
edge (CK/CK# and DQS/DQS#)
VIH,diff,min VIL,diff,max [VIH,diff,min - VIL,diff,maxΔTFdiff
Note: 1. The differential signals (CK/CK# and DQS/DQS#) must be linear between these thresh-
olds.
Figure 95: Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS#
VIH,diff,min
0
VIL,diff,max
Time
Differential Input Voltage
ΔTFdiff ΔTRdiff
Output Characteristics and Operating Conditions
Table 72: Single-Ended AC and DC Output Levels
Symbol Parameter Value Unit Notes
VOH(AC) AC output HIGH measurement level (for output slew rate) VREF + 0.12 V
VOL(AC) AC output LOW measurement level (for output slew rate) VREF - 0.12 V
VOH(DC) DC output HIGH measurement level (for I-V curve linearity) 0.9 x VDDQ V1
VOL(DC) DC output LOW measurement level (for I-V curve linearity) 0.1 x VDDQ V2
IOZ Output leakage current (DQ, DM, DQS, DQS#); DQ,
DQS, DQS# are disabled; 0V ≤ VOUT ≤ VDDQ
MIN –5 μA
MAX +5 μA
MMpupd Delta output impedance between pull-up and pull-
down for DQ/DM
MIN –15 %
MAX +15 %
Notes: 1. IOH = –0.1mA.
2. IOL = 0.1mA.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Characteristics and Operating Conditions
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Table 73: Differential AC and DC Output Levels
Symbol Parameter Value Unit
VOHdiff(AC) AC differential output HIGH measurement level (for output SR) + 0.2 x VDDQ V
VOLdiff(AC) AC differential output LOW measurement level (for output SR) - 0.2 x VDDQ V
Single-Ended Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended
signals.
Table 74: Single-Ended Output Slew Rate Definition
Description
Measured
Defined byFrom To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)ΔTRSE
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)ΔTFSE
Note: 1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
Figure 96: Single-Ended Output Slew Rate Definition
VOH(AC)
VREF
VOL(AC)
Time
Single-Ended Output Voltage (DQ)
ΔTFSE ΔTRSE
Table 75: Single-Ended Output Slew Rate
Notes 1–5 apply to all parameters conditions
Parameter Symbol
Value
UnitMin Max
Single-ended output slew rate (output impedance = 40Ω  SRQSE 1.5 3.5 V/ns
Single-ended output slew rate (output impedance = 60Ω  SRQSE 1.0 2.5 V/ns
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Characteristics and Operating Conditions
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Table 75: Single-Ended Output Slew Rate (Continued)
Notes 1–5 apply to all parameters conditions
Parameter Symbol
Value
UnitMin Max
Output slew-rate-matching ratio (pull-up to pull-down) 0.7 1.4 –
Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single-
ended signals.
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and
voltage over the entire temperature and voltage range. For a given output, the ratio
represents the maximum difference between pull-up and pull-down drivers due to proc-
ess variation.
4. The output slew rate for falling and rising edges is defined and measured between
VOL(AC) and VOH(AC).
5. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per
data byte driving LOW.
Differential Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential
signals.
Table 76: Differential Output Slew Rate Definition
Description
Measured
Defined byFrom To
Differential output slew rate for rising edge VOL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)ΔTRdiff
Differential output slew rate for falling edge VOH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)ΔTFdiff
Note: 1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Characteristics and Operating Conditions
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Figure 97: Differential Output Slew Rate Definition
VOH,diff(AC)
0
VOL,diff(AC)
Time
Differential Output Voltage (DQS, DQS#)
ΔTFdiff ΔTRdiff
Table 77: Differential Output Slew Rate
Parameter Symbol
Value
UnitMin Max
Differential output slew rate (output impedance = 40Ω  SRQdiff 3.0 7.0 V/ns
Differential output slew rate (output impedance = 60Ω  SRQdiff 2.0 5.0 V/ns
Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single-
ended signals.
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is defined and measured between
VOL(AC) and VOH(AC).
4. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per
data byte driving LOW.
Table 78: AC Overshoot/Undershoot Specification
Applies for CA[9:0], CS#, CKE, CK, CK#, DQ, DQS, DQS#, DM
Parameter 1066 933 800 667 533 400 333 Unit
Maximum peak amplitude provided for overshoot area 0.35 0.35 0.35 0.35 0.35 0.35 0.35 V
Maximum peak amplitude provided for undershoot area 0.35 0.35 0.35 0.35 0.35 0.35 0.35 V
Maximum area above VDD10.15 0.17 0.20 0.24 0.30 0.40 0.48 V/ns
Maximum area below VSS20.15 0.17 0.20 0.24 0.30 0.40 0.48 V/ns
Notes: 1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ,
DM, DQS, and DQS#.
2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM,
DQS, and DQS#.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Characteristics and Operating Conditions
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Figure 98: Overshoot and Undershoot Definition
Overshoot area
VDD
VSS
Volts (V)
Undershoot area
Maximum amplitude
Maximum amplitude
Time (ns)
Notes: 1. VDD stands for VDDCA for CA[9:0], CK, CK#, CS#, and CKE. VDD stands for VDDQ for DQ,
DM, DQS, and DQS#.
2. VSS stands for VSSCA for CA[9:0], CK, CK#, CS#, and CKE. VSS stands for VSSQ for DQ, DM,
DQS, and DQS#.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Characteristics and Operating Conditions
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HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not intended as a precise representation of any particu-
lar system environment or a depiction of the actual load presented by a production test-
er. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production
test conditions, generally with one or more coaxial transmission lines terminated at the
tester electronics.
Figure 99: HSUL_12 Driver Output Reference Load for Timing and Slew Rate
LPDDR2
VREF 0.5 × VDDQ
Output
CLOAD = 5pF
VTT = 0.5 × VDDQ
50Ω
Note: 1. All output timing parameter values (tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported
with respect to this reference load. This reference load is also used to report slew rate.
Output Driver Impedance
Output driver impedance is selected by a mode register during initialization. To achieve
tighter tolerances, ZQ calibration is required. Output specifications refer to the default
output drive unless specifically stated otherwise. The output driver impedance RON is
defined by the value of the external reference resistor RZQ as follows:
RONPU = VDDQ - VOUT
ABS(IOUT)
When RONPD is turned off.
RONPD = VOUT
When RONPU is turned off.
ABS(IOUT)
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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Figure 100: Output Driver
To other
circuitry
(RCV, etc.)
Output Driver
Chip in Drive Mode
IPU
RONPU
RONPD
IPD
IOUT
VDDQ
VOUT
DQ
VSSQ
Output Driver Impedance Characteristics with ZQ Calibration
Output driver impedance is defined by the value of the external reference resistor RZQ.
Typical RZQ is 240 ohms.
Table 79: Output Driver DC Electrical Characteristics with ZQ Calibration
Notes 1–4 apply to all parameters and conditions
RONnom Resistor VOUT Min Typ Max Unit Notes
ΩRON34PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/7
RON34PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/7
ΩRON40PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/6
RON40PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/6
ΩRON48PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/5
RON48PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/5
ΩRON60PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/4
RON60PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/4
ΩRON80PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/3
RON80PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/3
ΩRON120PD 0.5 × VDDQ 0.85 1.00 1.15 RZQ/2
RON120PU 0.5 × VDDQ 0.85 1.00 1.15 RZQ/2
Mismatch between
pull-up and pull-down
MMPUPD –15.00 +15.00 % 5
Notes: 1. Applies across entire operating temperature range after calibration.
2. RZQ Ω
3. The tolerance limits are specified after calibration, with fixed voltage and temperature.
For behavior of the tolerance limits if temperature or voltage changes after calibration
Output Driver Temperature and Voltage Sensitivity (page 142).
4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x VDDQ.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure RONPU and RONPD, both at 0.5 × VDDQ:
MMPUPD = RONPU – RONPD × 100
RON,nom
For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen.
Table 80: Output Driver Sensitivity Definition
Resistor VOUT Min Max Unit
RONPD 0.5 × VDDQ 85 – (dRONdT ΔT|) – (dRONdV ΔV|) 115 + (dRONdT ΔT|) – (dRONdV ΔV|) %
RONPU
Notes: 1. ΔT = T - T (at calibration). ΔV = V - V (at calibration).
2. dRONdT and dRONdV are not subject to production testing; they are verified by design
and characterization.
Table 81: Output Driver Temperature and Voltage Sensitivity
Symbol Parameter Min Max Unit
RONdT RON temperature sensitivity 0.00 0.75 %/˚C
RONdV RON voltage sensitivity 0.00 0.20 %/mV
Output Impedance Characteristics Without ZQ Calibration
Output driver impedance is defined by design and characterization as the default set-
ting.
Table 82: Output Driver DC Electrical Characteristics Without ZQ Calibration
RONnom Resistor VOUT Min Typ Max Unit
ΩRON34PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/7
RON34PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/7
ΩRON40PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/6
RON40PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/6
ΩRON48PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/5
RON48PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/5
ΩRON60PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/4
RON60PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/4
ΩRON80PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/3
RON80PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/3
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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Table 82: Output Driver DC Electrical Characteristics Without ZQ Calibration (Continued)
RONnom Resistor VOUT Min Typ Max Unit
ΩRON120PD 0.5 × VDDQ 0.70 1.00 1.30 RZQ/2
RON120PU 0.5 × VDDQ 0.70 1.00 1.30 RZQ/2
Notes: 1. Applies across entire operating temperature range without calibration.
2. RZQ Ω
Table 83: I-V Curves
Voltage (V)
RON
Ω
(RZQ)
Pull-Down Pull-Up
Current (mA) / RON (ohms) Current (mA) / RON (ohms)
Default Value after
ZQRESET With Calibration
Default Value after
ZQRESET With Calibration
Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA)
0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
0.05 0.19 0.32 0.21 0.26 –0.19 –0.32 –0.21 –0.26
0.10 0.38 0.64 0.40 0.53 –0.38 –0.64 –0.40 –0.53
0.15 0.56 0.94 0.60 0.78 –0.56 –0.94 –0.60 –0.78
0.20 0.74 1.26 0.79 1.04 –0.74 –1.26 –0.79 –1.04
0.25 0.92 1.57 0.98 1.29 –0.92 –1.57 –0.98 –1.29
0.30 1.08 1.86 1.17 1.53 –1.08 –1.86 –1.17 –1.53
0.35 1.25 2.17 1.35 1.79 –1.25 –2.17 –1.35 –1.79
0.40 1.40 2.46 1.52 2.03 –1.40 –2.46 –1.52 –2.03
0.45 1.54 2.74 1.69 2.26 –1.54 –2.74 –1.69 –2.26
0.50 1.68 3.02 1.86 2.49 –1.68 –3.02 –1.86 –2.49
0.55 1.81 3.30 2.02 2.72 –1.81 –3.30 –2.02 –2.72
0.60 1.92 3.57 2.17 2.94 –1.92 –3.57 –2.17 –2.94
0.65 2.02 3.83 2.32 3.15 –2.02 –3.83 –2.32 –3.15
0.70 2.11 4.08 2.46 3.36 –2.11 –4.08 –2.46 –3.36
0.75 2.19 4.31 2.58 3.55 –2.19 –4.31 –2.58 –3.55
0.80 2.25 4.54 2.70 3.74 –2.25 –4.54 –2.70 –3.74
0.85 2.30 4.74 2.81 3.91 –2.30 –4.74 –2.81 –3.91
0.90 2.34 4.92 2.89 4.05 –2.34 –4.92 –2.89 –4.05
0.95 2.37 5.08 2.97 4.23 –2.37 –5.08 –2.97 –4.23
1.00 2.41 5.20 3.04 4.33 –2.41 –5.20 –3.04 –4.33
1.05 2.43 5.31 3.09 4.44 –2.43 –5.31 –3.09 –4.44
1.10 2.46 5.41 3.14 4.52 –2.46 –5.41 –3.14 –4.52
1.15 2.48 5.48 3.19 4.59 –2.48 –5.48 –3.19 –4.59
1.20 2.50 5.55 3.23 4.65 –2.50 –5.55 –3.23 –4.65
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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Figure 101: Output Impedance = 240 Ohms, I-V Curves After ZQRESET
6
4
2
0
–2
–4
–6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
mA
Voltage
PD (MAX)
PD (MIN)
PU MAX)
PU (MIN)
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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Figure 102: Output Impedance = 240 Ohms, I-V Curves After Calibration
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
6
4
2
0
–2
–4
–6
mA
Voltage
PD (MAX)
PD (MIN)
PU MAX)
PU (MIN)
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
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Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks vio-
lating minimum or maximum values may result in device malfunction.
Table 84: Definitions and Calculations
Symbol Description Calculation Notes
tCK(avg) and
nCK
The average clock period across any consecutive
200-cycle window. Each clock period is calculated
from rising clock edge to rising clock edge.
Unit tCK(avg) represents the actual clock average
tCK(avg)of the input clock under operation. Unit
nCK represents one clock cycle of the input clock,
counting from actual clock edge to actual clock
edge.
tCK(avg)can change no more than ±1% within a
100-clock-cycle window, provided that all jitter
and timing specifications are met.
tCK(avg) = Σ tCKj /N
Where N = 200
N
j = 1
tCK(abs) The absolute clock period, as measured from one
rising clock edge to the next consecutive rising
clock edge.
1
tCH(avg) The average HIGH pulse width, as calculated
across any 200 consecutive HIGH pulses. tCH(avg) = Σ tCHj /(N × tCK(avg))
Where N = 200
N
j = 1
tCL(avg) The average LOW pulse width, as calculated
across any 200 consecutive LOW pulses. tCL(avg) = Σ tCLj /(N × tCK(avg))
Where N = 200
N
j = 1
tJIT(per) The single-period jitter defined as the largest de-
viation of any signal tCK from tCK(avg). tJIT(per) = min/max of tCKi – tCK(avg)
Where i = 1 to 200
1
tJIT(per),act The actual clock jitter for a given system.
tJIT(per),
allowed
The specified clock period jitter allowance.
tJIT(cc) The absolute difference in clock periods between
two consecutive clock cycles. tJIT(cc) defines the
cycle-to-cycle jitter.
tJIT(cc) = max of tCKi + 1 – tCKi
1
tERR(nper) The cumulative error across n multiple consecu-
tive cycles from tCK(avg). tERR(nper) = Σ tCKj – (n × tCK(avg))
i + n – 1
j = i
1
tERR(nper),act The actual cumulative error over n cycles for a
given system.
tERR(nper),
allowed
The specified cumulative error allowance over n
cycles.
tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Specification
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Table 84: Definitions and Calculations (Continued)
Symbol Description Calculation Notes
tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2
tJIT(duty) Defined with absolute and average specifications
for tCH and tCL, respectively.
tJIT(duty),min =
MIN((tCH(abs),min – tCH(avg),min),
(tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max =
MAX((tCH(abs),max – tCH(avg),max),
(tCL(abs),max – tCL(avg),max)) × tCK(avg)
Notes: 1. Not subject to production testing.
2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
tCK(abs), tCH(abs), and tCL(abs)
These parameters are specified with their average values; however, the relationship be-
tween the average timing and the absolute instantaneous timing (defined in the follow-
ing table) is applicable at all times.
Table 85: tCK(abs), tCH(abs), and tCL(abs) Definitions
Parameter Symbol Minimum Unit
Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min ps1
Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg)
Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg)
Notes: 1. tCK(avg),min is expressed in ps for this table.
2. tJIT(duty),min is a negative value.
Clock Period Jitter
LPDDR2 devices can tolerate some clock period jitter without core timing parameter
derating. This section describes device timing requirements with clock period jitter
(tJIT(per)) in excess of the values found in the AC Timing section. Calculating cycle time
derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters
Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) ex-
tend across multiple clock cycles. Clock period jitter impacts these parameters when
measured in numbers of clock cycles. Within the specification limits, the device is char-
acterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device op-
eration where clock jitter is outside specification limits, the number of clocks or
tCK(avg), may need to be increased based on the values for each core timing parameter.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Period Jitter
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Cycle Time Derating for Core Timing Parameters
For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed
tERR(tnPARAM),allowed, cycle time derating may be required for core timing parame-
ters.
CycleTimeDerating = max
tPARAM +
tERR(tnPARAM),act – tERR(tnPARAM),allowed – tCK(avg) , 0
tnPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings de-
termined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters
For each core timing parameter and a given number of clocks (tnPARAM), clock cycle
derating should be specified with tJIT(per).
For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) ex-
ceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the
equation below results in a positive value for a core timing parameter (tCORE), the re-
quired clock cycle derating will be that positive value (in clocks).
ClockCycleDerating = RU tPARAM + tERR(tnPARAM),act – tERR(tnPARAM),allowed – tnPARAM
tCK(avg)
Cycle-time derating analysis should be conducted for each core timing parameter.
Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb,
tIHCKEb) are measured from a command/address signal (CKE, CS, or CA[9:0]) transi-
tion edge to its respective clock signal (CK/CK#) crossing. The specification values are
not affected by the tJIT(per) applied, because the setup and hold times are relative to
the clock signal crossing that latches the command/address. Regardless of clock jitter
values, these values must be met.
Clock Jitter Effects on READ Timing Parameters
tRPRE
When the device is operated with input clock jitter, tRPRE must be derated by the
tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output derat-
ings are relative to the input clock:
tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max
tCK(avg)
For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = –172ps, and tJIT(per),act,max = +193ps, then tRPRE,min,derated =
0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 =
0.8628 tCK(avg).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Period Jitter
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tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition
(DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be
met with respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and
tCL(abs)min. These parameters determine the absolute data valid window at the device
pin. The absolute minimum data valid window at the device pin = min [(tQSH(abs)min
× tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax -
tQHSmax)]. This minimum data valid window must be met at the target frequency re-
gardless of clock jitter.
tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min
can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.
Clock Jitter Effects on WRITE Timing Parameters
tDS, tDH
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3;
and m = DQ[31:0]) transition edge to its respective data strobe signal (DQSn, DQSn#: n
= 0,1,2,3) crossing. The specification values are not affected by the amount of tJIT(per)
applied, because the setup and hold times are relative to the clock signal crossing that
latches the command/address. Regardless of clock jitter values, these values must be
met.
tDSS, tDSH
These parameters are measured from a data strobe signal crossing (DQSx, DQSx#) to its
clock signal crossing (CK/CK#). The specification values are not affected by the amount
of tJIT(per)) applied, because the setup and hold times are relative to the clock signal
crossing that latches the command/address. Regardless of clock jitter values, these val-
ues must be met.
tDQSS
tDQSS is measured from the clock signal crossing (CK/CK#) to the first latching data
strobe signal crossing (DQSx, DQSx#). When the device is operated with input clock jit-
ter, this parameter must be derated by the actual tJIT(per),act of the input clock in ex-
cess of tJIT(per),allowed.
tDQSS(min,derated) = 0.75 - tJIT(per),act,min – tJIT(per),allowed, min
tCK(avg)
tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max
tCK(avg)
For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps,
tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then:
tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) =
0.75 - (-172 + 100)/2500 = 0.7788 tCK(avg), and
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Clock Period Jitter
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tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) =
1.25 - (193 - 100)/2500 = 1.2128 tCK(avg).
Refresh Requirements
Table 86: Refresh Requirement Parameters (Per Density)
Parameter Symbol 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Unit
Number of banks 44448888
Refresh window: TCASE ≤ 85˚ tREFW 32 32 32 32 32 32 32 32 ms
Refresh window:
85˚C < TCASE ≤ 105˚C
tREFW 88888888ms
Required number of REFRESH
commands (MIN)
R 2048 2048 4096 4096 4096 8192 8192 8192
Average time be-
tween REFRESH com-
mands (for reference
only) TCASE ≤ 85˚C
REFab tREFI 15.6 15.6 7.8 7.8 7.8 3.9 3.9 3.9 μs
REFpb tREFIpb (REFpb not supported below 1Gb) 0.975 0.4875 0.4875 0.4875 μs
Refresh cycle time tRFCab 90 90 90 90 130 130 130 210 ns
Per-bank REFRESH cycle time tRFCpb na 60 60 60 90 ns
Burst REFRESH window =
4 × 8 × tRFCab
tREFBW 2.88 2.88 2.88 2.88 4.16 4.16 4.16 6.72 μs
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Refresh Requirements
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AC Timing
Table 87: AC Timing
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes1066 933 800 667 533 400 333
Maximum frequency – – 533 466 400 333 266 200 166 MHz
Clock Timing
Average clock period tCK(avg) MIN – 1.875 2.15 2.5 3 3.75 5 6 ns
MAX – 100 100 100 100 100 100 100
Average HIGH pulse width tCH(avg) MIN – 0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK
(avg)
MAX – 0.55 0.55 0.55 0.55 0.55 0.55 0.55
Average LOW pulse width tCL(avg) MIN – 0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK
(avg)
MAX – 0.55 0.55 0.55 0.55 0.55 0.55 0.55
Absolute clock period tCK(abs) MIN – tCK(avg)min ± tJIT(per)min ps
Absolute clock HIGH pulse width tCH(abs) MIN – 0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK
(avg)
MAX – 0.57 0.57 0.57 0.57 0.57 0.57 0.57
Absolute clock LOW pulse width tCL(abs) MIN – 0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK
(avg)
MAX – 0.57 0.57 0.57 0.57 0.57 0.57 0.57
Clock period jitter
(with supported jitter)
tJIT(per),
allowed
MIN – -90 -95 -100 -110 -120 -140 -150 ps
MAX – 90 95 100 110 120 140 150
Maximum clock jitter between
two consectuive clock cycles
(with supported jitter)
tJIT(cc),
allowed
MAX – 180 190 200 220 240 280 300 ps
Duty cycle jitter
(with supported jitter)
tJIT(duty),
allowed
MIN – MIN ((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) × tCK(avg)
ps
MAX – MAX ((tCH(abs),max - tCH(avg),max),
(tCL(abs),max - tCL(avg),max)) × tCK(avg)
Cumulative errors across 2 cycles tERR(2per),
allowed
MIN – -132 -140 -147 -162 -177 -206 -221 ps
MAX – 132 140 147 162 177 206 221
Cumulative errors across 3 cycles tERR(3per),
allowed
MIN – -157 -166 -175 -192 -210 -245 -262 ps
MAX – 157 166 175 192 210 245 262
Cumulative errors across 4 cycles tERR(4per),
allowed
MIN – -175 -185 -194 -214 -233 -272 -291 ps
MAX – 175 185 194 214 233 272 291
Cumulative errors across 5 cycles tERR(5per),
allowed
MIN – -188 -199 -209 -230 -251 -293 -314 ps
MAX – 188 199 209 230 251 293 314
Cumulative errors across 6 cycles tERR(6per),
allowed
MIN – -200 -211 -222 -244 -266 -311 -333 ps
MAX – 200 211 222 244 266 311 333
Cumulative errors across 7 cycles tERR(7per),
allowed
MIN – -209 -221 -232 -256 -279 -325 -348 ps
MAX – 209 221 232 256 279 325 348
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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Table 87: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes1066 933 800 667 533 400 333
Cumulative errors across 8 cycles tERR(8per),
allowed
MIN – -217 -229 -241 -266 -290 -338 -362 ps
MAX – 217 229 241 266 290 338 362
Cumulative errors across 9 cycles tERR(9per),
allowed
MIN – -224 -237 -249 -274 -299 -349 -374 ps
MAX – 224 237 249 274 299 349 374
Cumulative errors across 10 cycles tERR(10per),
allowed
MIN – -231 -244 -257 -282 -308 -359 -385 ps
MAX – 231 244 257 282 308 359 385
Cumulative errors across 11 cycles tERR(11per),
allowed
MIN – -237 -250 -263 -289 -316 -368 -395 ps
MAX – 237 250 263 289 316 368 395
Cumulative errors across 12 cycles tERR(12per),
allowed
MIN – -242 -256 -269 -296 -323 -377 -403 ps
MAX – 242 256 269 296 323 377 403
Cumulative errors across n = 13,
14, 15…, 49, 50 cycles
tERR(nper),
allowed
MIN tERR(nper),allowed,min = (1 + 0.68ln(n)) ×
tJIT(per),allowed,min
ps
MAX tERR(nper), allowed,max = (1 + 0.68ln(n)) ×
tJIT(per),allowed,max
ZQ Calibration Parameters
Initialization calibration time tZQINIT MIN – 1 1 1 1 1 1 1 μs
Long calibration time tZQCL MIN 6 360 360 360 360 360 360 360 ns
Short calibration time tZQCS MIN 6 90 90 90 90 90 90 90 ns
Calibration RESET time tZQRESET MIN 3 50 50 50 50 50 50 50 ns
READ Parameters3
DQS output access time from
CK/CK#
tDQSCK MIN – 2500 2500 2500 2500 2500 2500 2500 ps
MAX – 5500 5500 5500 5500 5500 5500 5500
DQSCK delta short tDQSCKDS MAX – 330 380 450 540 670 900 1080 ps 4
DQSCK delta medium tDQSCKDM MAX – 680 780 900 1050 1350 1800 1900 ps 5
DQSCK delta long tDQSCKDL MAX – 920 1050 1200 1400 1800 2400 – ps 6
DQS-DQ skew tDQSQ MAX – 200 220 240 280 340 400 500 ps
Data-hold skew factor tQHS MAX – 230 260 280 340 400 480 600 ps
DQS output HIGH pulse width tQSH MIN – tCH(abs) - 0.05 tCK
(avg)
DQS output LOW pulse width tQSL MIN – tCL(abs) - 0.05 tCK
(avg)
Data half period tQHP MIN – MIN (tQSH, tQSL) tCK
(avg)
DQ/DQS output hold time from
DQS
tQH MIN – tQHP - tQHS ps
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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Table 87: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes1066 933 800 667 533 400 333
READ preamble tRPRE MIN – 0.9 0.9 0.9 0.9 0.9 0.9 0.9 tCK
(avg)
7
READ postamble tRPST MIN – tCL(abs) - 0.05 tCK
(avg)
8
DQS Low-Z from clock tLZ(DQS) MIN – tDQSCK (MIN) - 300 ps
DQ Low-Z from clock tLZ(DQ) MIN – tDQSCK(MIN) - (1.4 × tQHS(MAX)) ps
DQS High-Z from clock tHZ(DQS) MAX – tDQSCK (MAX) - 100 ps
DQ High-Z from clock tHZ(DQ) MAX – tDQSCK(MAX) + (1.4 × tDQSQ(MAX)) ps
WRITE Parameters3
DQ and DM input hold time (VREF
based)
tDH MIN – 210 235 270 350 430 480 600 ps
DQ and DM input setup time (VREF
based)
tDS MIN – 210 235 270 350 430 480 600 ps
DQ and DM input pulse width tDIPW MIN – 0.35 0.35 0.35 0.35 0.35 0.35 0.35 tCK
(avg)
Write command to first DQS latch-
ing transition
tDQSS MIN – 0.75 0.75 0.75 0.75 0.75 0.75 0.75 tCK
(avg)
MAX – 1.25 1.25 1.25 1.25 1.25 1.25 1.25 tCK
(avg)
DQS input high-level width tDQSH MIN – 0.4 0.4 0.4 0.4 0.4 0.4 0.4 tCK
(avg)
DQS input low-level width tDQSL MIN – 0.4 0.4 0.4 0.4 0.4 0.4 0.4 tCK
(avg)
DQS falling edge to CK setup time tDSS MIN – 0.2 0.2 0.2 0.2 0.2 0.2 0.2 tCK
(avg)
DQS falling edge hold time from
CK
tDSH MIN – 0.2 0.2 0.2 0.2 0.2 0.2 0.2 tCK
(avg)
Write postamble tWPST MIN – 0.4 0.4 0.4 0.4 0.4 0.4 0.4 tCK
(avg)
Write preamble tWPRE MIN – 0.35 0.35 0.35 0.35 0.35 0.35 0.35 tCK
(avg)
CKE Input Parameters
CKE minimum pulse width (HIGH
and LOW pulse width)
tCKE MIN 3 3 3 3 3 3 3 3 tCK
(avg)
CKE input setup time tISCKE MIN – 0.25 0.25 0.25 0.25 0.25 0.25 0.25 tCK
(avg)
9
CKE input hold time tIHCKE MIN – 0.25 0.25 0.25 0.25 0.25 0.25 0.25 tCK
(avg)
10
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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Table 87: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes1066 933 800 667 533 400 333
Command Address Input Parameters3
Address and control input setup
time
tIS MIN – 220 250 290 370 460 600 740 ps 11
Address and control input hold
time
tIH MIN – 220 250 290 370 460 600 740 ps 11
Address and control input pulse
width
tIPW MIN – 0.40 0.40 0.40 0.40 0.40 0.40 0.40 tCK
(avg)
Boot Parameters (10 MHz–55 MHz)12, 13, 14
Clock cycle time tCKb MAX – 100 100 100 100 100 100 100 ns
MIN– 18 181818181818
CKE input setup time tISCKEb MIN – 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
CKE input hold time tIHCKEb MIN – 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns
Address and control input setup
time
tISb MIN – 1150 1150 1150 1150 1150 1150 1150 ps
Address and control input hold
time
tIHb MIN – 1150 1150 1150 1150 1150 1150 1150 ps
DQS output data access time from
CK/CK#
tDQSCKb MIN – 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns
MAX – 10.0 10.0 10.0 10.0 10.0 10.0 10.0
Data strobe edge to output data
edge
tDQSQb MAX – 1.2 1.2 1.2 1.2 1.2 1.2 1.2 ns
Data hold skew factor tQHSb MAX – 1.2 1.2 1.2 1.2 1.2 1.2 1.2 ns
Mode Register Parameters
MODE REGISTER WRITE
command period
tMRW MIN 3 3 3 3 3 3 3 3 tCK
(avg)
MODE REGISTER READ
command period
tMRR MIN 2 2 2 2 2 2 2 2 tCK
(avg)
Core Parameters15
READ latency RL MIN 3 8 7 6 5 4 3 3 tCK
(avg)
WRITE latency WL MIN 1 4 4 3 2 2 1 1 tCK
(avg)
ACTIVATE-to-ACTIVATE
command period
tRC MIN – tRAS + tRPab (with all-bank precharge),
tRAS + tRPpb (with per-bank precharge)
ns 17
CKE minimum pulse width during
SELF REFRESH (low pulse width
during SELF REFRESH)
tCKESR MIN 3 15 15 15 15 15 15 15 ns
SELF REFRESH exit to next valid
command delay
tXSR MIN 2 tRFCab + 10 ns
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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Table 87: AC Timing (Continued)
Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-
tiples of tCK) as well as the timing specifications when values for both are indicated.
Parameter Symbol
Min/
Max
tCK
Min
Data Rate
Unit Notes1066 933 800 667 533 400 333
Exit power-down to next valid
command delay
tXP MIN 2 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns
CAS-to-CAS delay tCCD MIN 2 2 2 2 2 2 2 2 tCK
(avg)
Internal READ to PRECHARGE
command delay
tRTP MIN 2 7.5 7.5 7.5 7.5 7.5 7.5 7.5 ns
RAS-to-CAS delay tRCD Fast 3 15 15 15 15 15 15 15 ns
TYP3 18 181818181818
Row precharge time (single bank) tRPpb Fast 3 15 15 15 15 15 15 15 ns
TYP3 18 181818181818
Row precharge time (all banks) tRPab
4-bank
Fast 3 15 15 15 15 15 15 15 ns
TYP3 18 181818181818
Row precharge time (all banks) tRPab
8-bank
Fast 3 18 18 18 18 18 18 18 ns
TYP3 21 212121212121
Row active time tRAS MIN 3 42 42 42 42 42 42 42 ns
MAX– 70 707070707070 μs
WRITE recovery time tWR MIN3 15 151515151515ns
Internal WRITE-to-READ
command delay
tWTR MIN 2 7.5 7.5 7.5 7.5 7.5 10 10 ns
Active bank a to active bank btRRD MIN 2 10 10 10 10 10 10 10 ns
Four-bank activate window tFAW MIN8 50 505050505060ns
Minimum deep power-down time tDPD MIN – 500 500 500 500 500 500 500 μs
Temperature Derating16
tDQSCK derating tDQSCK
(derated)
MAX – 5620 6000 6000 6000 6000 6000 6000 ps
Core timing temperature
derating
tRCD
(derated)
MIN – tRCD + 1.875 ns
tRC
(derated)
MIN – tRC + 1.875 ns
tRAS
(derated)
MIN – tRAS + 1.875 ns
tRP
(derated)
MIN – tRP + 1.875 ns
tRRD
(derated)
MIN – tRRD + 1.875 ns
Notes: 1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine de-
vice capabilities.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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2. All AC timings assume an input slew rate of 1 V/ns.
3. READ, WRITE, and input setup and hold values are referenced to VREF.
4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.
tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is
<10˚C/s. Values do not include clock jitter.
5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a 1.6μs rolling window. tDQSCKDM is not tested and is
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measure-
ments (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point
when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in
the same access time (with respect to clock) as valid data transitions. These parameters
are not referenced to a specific voltage level but to the time when the device output is
no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,
tLZ(DQS), tLZ(DQ)). The figure below shows a method to calculate the point when the
device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and tLZ(DQ)
by measuring the signal at two different voltages. The actual voltage measurement
points are not critical as long as the calculation is consistent. The parameters tLZ(DQS),
tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters
tRPRE and tRPST are determined from the differential signal DQS/DQS#.
Output Transition Timing
VOL + 2x X mV
VOL + X mV
VOH - X mV
VOH - 2x X mV
2x X
X
2x Y
VOH
VOL
Y
T1 T2
VTT - Y mV
VTT VTT
VTT - 2x Y mV
VTT + 2x Y mV
VTT + Y mV tLZ(DQS), tLZ(DQ)
tHZ(DQS), tHZ(DQ)
T1 T2
Start driving point = 2 × T1 - T2 End driving point = 2 × T1 - T2
a
c
t
u
a
l
w
a
v
e
f
o
r
m
7. Measured from the point when DQS/DQS# begins driving the signal, to the point when
DQS/DQS# begins driving the first rising strobe edge.
8. Measured from the last falling strobe edge of DQS/DQS# to the point when DQS/DQS#
finishes driving the signal.
9. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK/CK# crossing.
10. CKE input hold time is measured from CK/CK# crossing to CKE reaching a HIGH/LOW
voltage level.
11. Input setup/hold time for signal (CA[9:0], CS#).
12. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. The letter b is appended to the boot parameter
symbols (for example, tCK during boot is tCKb).
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC Timing
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13. Mobile LPDDR2 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
14. The output skew parameters are measured with default output impedance settings
using the reference load.
15. The minimum tCK column applies only when tCK is greater than 6ns.
16. Timing derating applies for operation at 85˚C to 105˚C when the requirement to derate
is indicated by mode register 4 op-code (see the MR4 Device Temperature (MA[7:0] =
04h) table).
17. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
Figure 103: Command Input Setup and Hold Timing
tIS tIH
CommandNOP Command
T0 T1 T2 T3
CK#
CK
CS#
CA
rise
CA[9:0]
CMD
Don’t Care
Transitioning data
CA
fall CA
rise CA
fall CA
rise CA
fall CA
rise CA
fall
NOP
tIS tIH
tIS tIH tIS tIH
VIL(AC)
VIH(DC)
VIH(AC)
VIL(DC)
Notes: 1. The setup and hold timing shown applies to all commands.
2. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the
CKE pin, see Power-Down (page 101).
CA and CS# Setup, Hold, and Derating
For all input signals (CA and CS#), the total required setup time (tIS) and hold time (tIH)
is calculated by adding the data sheet tIS (base) and tIH (base) values to the ΔtIS and
ΔtIH derating values, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS. (See
the series of tables following this section.)
The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the
last crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical setup slew rate
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC)max. If the actual signal is consistently earlier than the typical
slew rate line between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for
the derating value (see Figure 104 (page 160)). If the actual signal is later than the typi-
cal slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for the derating
value (see Figure 106 (page 162)).
The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the
last crossing of VIL(DC)max and the first crossing of VREF(DC). The hold (tIH) typical slew
rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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and the first crossing of VREF(DC). If the actual signal is consistently later than the typical
slew rate line between the shaded DC-to-VREF(DC) region, use the typical slew rate for
the derating value (see Figure 105 (page 161)). If the actual signal is earlier than the typ-
ical slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of
a tangent line to the actual signal from the DC level to VREF(DC) level is used for the de-
rating value (see Figure 107 (page 163)).
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a
specified time, tVAC (see Table 92 (page 159)).
For slow slew rates the total setup time could be a negative value (that is, a valid input
signal will not have reached VIH/VIL(AC) at the time of the rising clock transition). A valid
input signal is still required to complete the transition and reach VIH/VIL(AC).
For slew rates between the values listed in Table 90, the derating values are obtained us-
ing linear interpolation. Slew rate values are not typically subject to production testing.
They are verified by design and characterization.
Table 88: CA and CS# Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)
Parameter
Data Rate
Reference1066 933 800 667 533 466
tIS (base) 0 30 70 150 240 300 VIH/VIL(AC) = VREF(DC) ±220mV
tIH (base) 90 120 160 240 330 390 VIH/VIL(DC) = VREF(DC) ±130mV
Note: 1. AC/DC referenced for 1 V/ns CA and CS# slew rate, and 2 V/ns differential CK/CK# slew
rate.
Table 89: CA and CS# Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate)
Parameter
Data Rate
Reference400 333 255 200
tIS (base) 300 440 600 850 VIH/VIL(AC) = VREF(DC) ±300mV
tIH (base) 400 540 700 950 VIH/VIL(DC) = VREF(DC) ±200mV
Note: 1. AC/DC referenced for 1 V/ns CA and CS# slew rate, and 2 V/ns differential CK/CK# slew
rate.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Table 90: Derating Values for AC/DC-Based tIS/tIH (AC220)
ΔtIS, ΔtIH derating in ps
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
CA, CS# slew
rate V/ns
2.0 110 65 110 65 110 65
1.5 74 43 73 43 73 43 89 59
1.0 0 0 0 0 0016 16 32 32
0.9 -3 -5 -3 -5 13 11 29 27 45 43
0.8 -8 -13 8 3 24 19 40 35 56 55
0.7 2 -6 1810342650466678
0.6 10 -3 26 13 42 33 58 65
0.5 4 -4 20163648
0.4 -7 2 17 34
Note: 1. Shaded cells are not supported.
Table 91: Derating Values for AC/DC-Based tIS/tIH (AC300)
ΔtIS, ΔtIH derating in ps
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
Δ
tIS
Δ
tIH
CA, CS# slew
rate V/ns
2.0 150 100 150 100 150 100
1.5 100 67 100 67 100 67 116 83
1.0 0 0 0 0 0016 16 32 32
0.9 -4 -8 -4 -8 12 8 28 24 44 40
0.8 -12-20 4 -4201236285248
0.7 -3 -18 13 -2 29 14 45 34 61 66
0.6 2 -21 18 -5 34 15 50 47
0.5 -12 -32 4 -12 20 20
0.4 -35 -40 -11 -8
Note: 1. Shaded cells are not supported.
Table 92: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC)
Slew Rate
(V/ns)
tVAC at 300mV (ps) tVAC at 220mV (ps)
Min Max Min Max
>2.0 75 – 175 –
2.0 57 – 170 –
1.5 50 – 167 –
1.0 38 – 163 –
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Table 92: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC)
(Continued)
Slew Rate
(V/ns)
tVAC at 300mV (ps) tVAC at 220mV (ps)
Min Max Min Max
0.9 34 – 162 –
0.8 29 – 161 –
0.7 22 – 159 –
0.6 13 – 155 –
0.5 0 – 150 –
<0.5 0 – 150 –
Figure 104: Typical Slew Rate and tVAC – tIS for CA and CS# Relative to Clock
VSSCA
CK#
CK
tVAC
Setup slew rate
rising signal
Setup slew rate
falling signal
ΔTF ΔTR
ΔTF
=
VIH(AC)min - VREF(DC)
ΔTR
=
VDDCA
Typical
slew rate
VREF to AC
region
VREF to AC
region
VREF(DC) - VIL(AC)max
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical
slew rate
tIH
tIS tIS
tIH
tVAC
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Figure 105: Typical Slew Rate – tIH for CA and CS# Relative to Clock
ΔTR ΔTF
Typical slew rate
DC to VREF
region
VSSCA
CK#
CK
VDDCA
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to VREF
region
Typical slew rate
Hold slew rate
rising signal
VREF(DC)
- VIL(DC)max
ΔTR
=
Hold slew rate
falling signal
VIH(DC)min
- VREF(DC)
ΔTF
=
tIH
tIS tIS
tIH
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Figure 106: Tangent Line – tIS for CA and CS# Relative to Clock
Setup slew rate
rising signal
ΔTF ΔTR
tangent line [VIH(AC)min
- VREF(DC)]
ΔTR
=
Setup slew rate
falling signal
tangent line [VREF(DC)
- VIL(AC)]max]
ΔTF
=
Tangent
line
Tangent
line
VREF to AC
region Typical
line
Typical
line
VSSCA
CK#
CK
VDDCA
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VREF to AC
region
tVAC
tIH
tIS tIS
tIH
tVAC
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Figure 107: Tangent Line – tIH for CA and CS# Relative to Clock
Tangent
line
DC to VREF
region
tIH
tIS tIS
VSSCA
VDDCA
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to VREF
region
Tangent
line
tIH
CK
CK#
Hold slew rate
falling signal
ΔTF
ΔTR
tangent line [VIH(DC)min - VREF(DC)]
ΔTF
=
Typical line
Hold slew rate
rising signal
tangent line [VREF(DC) - VIL(DC)max]
ΔTR
=
Typical
line
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
CA and CS# Setup, Hold, and Derating
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Data Setup, Hold, and Slew Rate Derating
For all input signals (DQ, DM) calculate the total required setup time (tDS) and hold
time (tDH) by adding the data sheet tDS(base) and tDH(base) values (see Table 93 (page
164)) to the ΔtDS and ΔtDH derating values, respectively (see Table 95 and Table 96
(page 166)). Example: tDS = tDS(base) + ΔtDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical tDS slew rate for a
falling signal is defined as the slew rate between the last crossing of VREF(DC) and the
first crossing of VIL(AC)max (see Figure 108 (page 167)).
If the actual signal is consistently earlier than the typical slew rate line in the figure,
"Typical Slew Rate and tVAC – tIS for CA and CS# Relative to Clock (CA and CS# Setup,
Hold, and Derating), the area shaded gray between the VREF(DC) region and the AC re-
gion, use the typical slew rate for the derating value. If the actual signal is later than the
typical slew rate line anywhere between the shaded VREF(DC) region and the AC region,
the slew rate of a tangent line to the actual signal from the AC level to the DC level is
used for the derating value (see figure "Tangent Line – tIS for CA and CS# Relative to
Clock" in CA and CS# Setup, Hold, and Derating).
The typical tDH slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC)max and the first crossing of VREF(DC). The typical tDH slew rate for a
falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the
first crossing of VREF(DC) (see Figure 109 (page 168)).
If the actual signal is consistently later than the typical slew rate line between the
shaded DC-level-to-VREF(DC) region, use the typical slew rate for the derating value. If
the actual signal is earlier than the typical slew rate line anywhere between shaded DC-
to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level
to the VREF(DC) level is used for the derating value (see Figure 111 (page 170)).
For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the
specified time, tVAC (see Table 97 (page 166)).
The total setup time for slow slew rates could be negative (that is, a valid input signal
may not have reached VIH/VIL(AC) at the time of the rising clock transition). A valid input
signal is still required to complete the transition and reach VIH/VIL(AC).
For slew rates between the values listed in Table 93 and Table 94, the derating values
can be obtained using linear interpolation. Slew rate values are not typically subject to
production testing. They are verified by design and characterization.
Table 93: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)
Parameter
Data Rate
Reference1066 933 800 667 533 466
tDS (base) -10 15 50 130 210 230 VIH/VIL(AC) = VREF(DC) ±220mV
tDH (base) 80 105 140 220 300 320 VIH/VIL(DC) = VREF(DC) ±130mV
Note: 1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS/DQS# slew
rate.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Table 94: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate)
Parameter
Data Rate
Reference400 333 255 200
tDS (base) 180 300 450 700 VIH/VIL(AC) = VREF(DC) ±300mV
tDH (base) 280 400 550 800 VIH/VIL(DC) = VREF(DC) ±200mV
Note: 1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS/DQS# slew
rate.
Table 95: Derating Values for AC/DC-Based tDS/tDH (AC220)
ΔtDS, ΔtDH derating in ps
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
DQ, DM
slew
rate
V/ns
2.0 110 65 110 65 110 65
1.5 74 43 73 43 73 43 89 59
1.0 0 0 0 0 0016 16 32 32
0.9 -3 -5 -3 -5 13 11 29 27 45 43
0.8 -8 -13 8 3 24 19 40 35 56 55
0.7 2 -61810342650466678
0.6 10 -3 26 13 42 33 58 65
0.5 4 -420163648
0.4 -7 2 17 34
Note: 1. Shaded cells are not supported.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Table 96: Derating Values for AC/DC-Based tDS/tDH (AC300)
ΔtDS, ΔtDH derating in ps
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
Δ
tDS
Δ
tDH
DQ, DM
slew
rate V/ns
2.0 150 100 150 100 150 100
1.5 100 67 100 67 100 67 116 83
1.0 0 0 0 0 0016 16 32 32
0.9 -4 -8 -4 -8 12 8 28 24 44 40
0.8 -12 -20 4 -4 20 12 36 28 52 48
0.7 -3 -18 13 -2 29 14 45 34 61 66
0.6 2 -21 18 -5 34 15 50 47
0.5 -12 -32 4 -12 20 20
0.4 4 -35 -40 -11 -8
Note: 1. Shaded cells are not supported.
Table 97: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC)
Slew Rate (V/ns)
tVAC at 300mV (ps) tVAC at 220mV (ps)
Min Max Min Max
>2.0 75 – 175 –
2.0 57 – 170 –
1.5 50 – 167 –
1.0 38 – 163 –
0.9 34 – 162 –
0.8 29 – 161 –
0.7 22 – 159 –
0.6 13 – 155 –
0.5 0 – 150 –
<0.5 0 – 150 –
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Figure 108: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe
VREF to AC
region
VREF to AC
region
Setup slew rate
rising signal
Setup slew rate
falling signal
ΔTF ΔTR
VREF(DC) - VIL(AC)max
ΔTF
=VIH(AC)min
- VREF(DC)
ΔTR
=
Typical
slew rate
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical
slew rate
tVAC
tVAC
tDH
tDS tDS
tDH
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Figure 109: Typical Slew Rate – tDH for DQ Relative to Strobe
Hold slew rate
falling signal
Hold slew rate
rising signal
VREF(DC) - VIL(DC)max
ΔTR
=
VIH(DC)min
- VREF(DC)
ΔTF
=
ΔTR ΔTF
Typical
slew rate
DC to VREF
region
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
DC to VREF
region
Typical
slew rate
tDH
tDS tDS
tDH
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Figure 110: Tangent Line – tDS for DQ with Respect to Strobe
ΔTF ΔTR
Setup slew rate
rising signal
Setup slew rate
falling signal
tangent line [V
REF(DC)
- V
IL(AC)max
]
ΔTF
=
tangent line [V
IH(AC)min
- V
REF(DC)
]
ΔTR
=
VSSQ
DQS#
DQS
VDDQ
VIH(DC)min
VREF(DC)
VIL(AC)max
VIL(DC)max
VIH(AC)min
Typical line
Tangent line
Typical
line
Tangent line
VREF to AC
region
VREF to AC
region
tVAC
tDH
tDS tDS
tDH
tVAC
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Figure 111: Tangent Line – tDH for DQ with Respect to Strobe
Tangent
line
DC to V
REF
region
VSSQ
VDDQ
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(DC)max
VIH(AC)min
DC to V
REF
region Tangent
line
DQS
DQS#
Hold slew rate
falling signal
ΔTF
ΔTR
tangent line [V
IH(DC)min
- V
REF(DC)
]
ΔTF
=
Typical line
Hold slew rate
rising signal
tangent line [V
REF(DC)
- V
IL(DC)max
]
ΔTR
=
Nominal
line
tDH
tDS tDS
tDH
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Data Setup, Hold, and Slew Rate Derating
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Revision History
Rev. O – 08/13
• Added IDD5ABET,IDD5PBET, and IDD6ETon IDDSpecification Tables, as well as IDDSpecifi-
cation Parameters and Operating Conditions Table
Rev. N – 05/13
• Added Dual Rank, Single Channel (3 Die) Package Block Diagram
• Added 216-Ball FBGA – 12mm x 12mm (Package Code LP) figure
• Updated 4Gb LPDDR2 Part Numbering figure
• Corrected clock on slew derating figures
• Tightened the IDD2N2 and IDD2NS2 limits
Rev. M – 10/12
• Corrected figure placement for Single Rank, Dual Channel Package Block Diagram
• Corrected note under 216-Ball 2-Channel FBGA – 12mm x 12mm figure
• Deleted inaccurate sentence under REFRESH Command: Bank addressing for the
per-bank REFRESH count is the same as established for the single-bank PRECHARGE
command (see Table 43 (page 73)).
Rev. L – 08/12
• Updated Self Refresh section to clarify CKE operation during self refresh
Rev. K – 07/12
• Changed WT lower limit from –25 to –30
Rev. J – 07/12
• Added IDD figures
Rev. I – 05/12
• Updated IDD tables
Rev. H – 04/12
• Deleted package code KV under Options on first page
• Deleted package code KV in 4Gb LPDDR2 Part Numbering figure
• Deleted package code KV in Package Codes and Descriptions table
• Changed channel A to channel B for package code LK in Package Codes and Descrip-
tions table
• Deleted package code KV in 216-Ball FBGA package dimension figure title
• Added drawing for 240-ball FBGA – 14mm x 14mm Dual Die (Package Code MC)
• Increased values for IDD2N2, IDD3P2, IDD3PS2, IDD3N1, IDD3NS1, IDD3N2, IDD3NS2, IDD4R1,
IDDR42, IDD4R,in, and IDD5PB2
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Revision History
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Rev. G – 04/12
• Changed AC9 from NC to VSS and added a note to the 168-Ball FBGA - 12mm x 12mm
figure
Rev. F – 03/12
• Changed B2 and B26 balls from VACC to NC on the 220-Ball 2-Channel FBGA - 14mm x
14mm figure
Rev. E – 02/12
• Corrected 168-ball SDP/DDP ball out drawing
• Updated IDD4R and IDD8,in values
• Added 216-ball (LK) package drawing
• Added 253-ball (EV) package drawing
• Added LL and LM package codes
• Deleted KH and KJ package codes
• Added solder ball composition to the Package Codes and Descriptions table
• Added note to IDD6 Partial-Array Self Refresh Current table
Rev. D – 12/11
• Changed B5, B8, F2, J2 and AC9 from VSS to NC on 168-ball FBGA ball assignment in
Signal Assignments
Rev. C – 12/11
• Changed status to Advance
• Updated IDD values
• Corrected H13 and N8 balls to NC in the 253-Ball 2-Channel FBGA – 11mm x 11mm
figure
• Updated packaging section
Rev. B – 05/11
• Editorial changes
Rev. A – 02/11
• Initial release; Preview status
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Revision History
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 172 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.