Am2502/3/4 Family Eight-Bit/Twelve-Bit Successive Approximation Registers Distinctive Characteristics @ Contains all the storage and control for successive Can be used as serial-to-parallel converter or ring approximation A-to-D converters. counters. @ Provision for register extension or truncation. @ Electrically tested and optically inspected dice for @ Can be operated in START-STOP or continuous the assemblers of hybrid products. conversion mode. FUNCTIONAL DESCRIPTION clock LOW-to-HIGH transition in order to guarantee correct t resetting. The Am2502, Am2503 and Am2504 are 8-bit and 12-bit TTL Suc- After the clock has gone HIGH resetting the register, the signal is cessive Approximation Registers. The registers contain all the digital removed, On the next clack LOW-to-HIGH transition the data on the contro! and storage necessary for successive approximation analog-to- D input is set into the Q7(11) register bit and the Qg{10) register bit is digital conversion. They can also be used in digital systems as the set to a LOW ready for the next clock cycle. On the next clock LOW- control and storage element in recursive digital routines. to-HIGH transition data enters the Qg(10) register bit and 5 (9) is set The registers consist of a set of master latches that act as the control toa LOW. This operation is repeated fos each register bit in turn until elements in the device and change state when the input clock is LOW, the register has been filled. When the data goes into Qp, the CC signal and a set of slave latches that hold the register data and change on the goes LOW, and the register is inhibited from frther change until reset input clock LOW-to-HIGH transition. Externally the device acts as a by a Start signal. special purpose serial-to-parallel converter that accepts 43ta at the D In order to allow complementary conversion the complementary input of the register and sends the data to the appropriate slave latch output of the most significant register bit is made available. An active to appear at the register output and the DO output on the Am2502 LOW enable input, E, on the Am2503 and Am2504 allows devices to and Am2504 when the clock goes from LOW-to-H!GH. There are no be connected together to form a longer register by connecting the restrictions on the data input; it can change state at any time except clock, D, and 5 inputs together and connecting the CE output of one during the set-up time just ptior to the clock transition. At the same device to the E input of the next less significant device. When the Start time that data enters the register bit the next less significant bit is set signal resets the register, the E signal goes HiGH, forcing the Q7(11] bit to a LOW ready for the next iteration. HIGH and inhibiting the device from accepting data until the previous The register is reset by holding the (Start) signal LOW during the device js full and its CC goes LOW. If only one device is used the E clock LOW-to-HIGH transition. The register synchronously resets to input should be held at a LOW logic level (Ground). if all the bits are the state Q5(11) LOW, (Note 2} and all the remaining register outputs not required, the register may be truncated and conversion time saved HIGH, The C (Conversion Complete] signai is also set HIGH at this by using a register output going LOW rather than the CC signal to time. The signal should not be brought back HIGH until after the indicate the end of conversion. LOGIC DIAGRAMS 90 #2402 7508 Oper Notes: 1. Cell logic is repeated for register stages. Qg to Q] Am2502/3, Qg to QO, Am2504. 2. Numbers in parentheses are for Am2504. Lic-224 LOGIC SYMBOLS CONNECTION DIAGRAMS - Top Views | l | i D-16, P-16 0-24, P-24 r 5 * eq 20 Yee 290% 1 OE ATORO? 7803 BOR 1 125021 iq on 2 afjan _t. on san ode et): nj xc , st aay oy of on nee ays whe FITTTITT I Or fe anasoe 8 D8 woah ros bat aE Pg og utfs 19 f7) or LiC-225 Qs Fo 16 [J S65, Voc = Pin 24 sae iB Vc = Pin 16 GND = Pin 12 eso [fe ator GND = Pin 8 NC = Pins 40, 15 22 Lic-227 Note: Pin 1 is marked for orientation. Lic-228 3-11 03920B-ANAAm2502/3/4 Family MAXIMUM RATINGS (Above which the useful life may be impaired) Storage Temperature 65 to +150C Supply Voltage to Ground Potential Continuous 0.5 to +7V DC Voltage Applied to Outputs for High Output State 0.5 to +Voc max DC Input Voltage 0.5 to +5.5V Output Current, Into Outputs 30mA DC Input Current 30 to +5.0mA ELECTRICAL CHARACTERISTICS over operating temperature and voltage ranges Am2502/3/4 Am25L02/L03/L04 Typ Typ Parameters Description Test Conditions Min |(Note 1)) Max | Min |(Note 1)} Max | Units Voc = MIN, lo = 0.48mA 24a | 36 oA Vou Output HIGH Voltage Vin = Vin or Vib z . ; 3.6 v Output LOW Voltage Voc = MIN, lo. = 9.6mA VoL (Note 2) VIN = Vin or Vit 0.2 04 0.15 0.3 Vv Guaranteed input logical HIGH Vu Input HIGH Level voltage for all inputs 2.0 2.0 v Guaranteed input logical LOW Vit input LOW Level voltage for all inputs 08 0.7 v Unit Load cp, D, -10 | -16 -0.25 | -04 Veco = =0. = Me input LOW Current co = MAX, Vin = 0.4V E -t5 | -2.4 0.4 | -0.6 mA Unit Load cP, D 6.0 | 40 2.0 | 20 Vee = =2. = ha Input HIGH Current Gc = MAX, Vin = 2.4V 6s 12.0 80 4.0 40 HA Input HIGH Current Voce = MAX, Vin = 5.5V 1.0 1.0 mA Isc Output Short Circuit Current Vec = MAX, Vout = 0.0V ~10 | -25 | -45 | -46 ) -15 | -35 mA XM 65 85 25 33 Am25(L)02 XC 65 95 25 35. I Pi Supply Ci vi MAX Am25(L)03 6 80 22 3 A ent = m m. ce ower Supply hurr ce Oy XC 60 | 90 22 | 33 XM 90 110 30 42 Am25(L}04 xc 390 124 30 45 Notes: 1. Typical Limits are at Voc = 5.0V, 25C ambient and maximum loading. 2. Vo_(MAX) = 0.4V with total device fanaut of less than 50 TTL Unit Loads (8O0mA). Otherwise, VoL (MAX) = 0.45V. SWITCHING CHARACTERISTICS Ta = 25C, Voc = +5.0V, CL = 15pF Am2502/3/4 Am25L02/3/4 Parameters Description Min Typ Max Min Typ Max | Units t Turn Off Delay CP to Output HIGH (except Q14, an) 10 239 45 75 10 ns pas Turn Off Delay CP to Qy; or Qy; HIGH 10 35 50 100 140 tog Turn On Detay CP to Output LOW 10 27 40 75 100 ns 1g{D) Setup Time Data Input -10 4.9 10 ~16 8.0 20 ns t,(S) Setup Time Start Input 0 9.0 16 20 25 ns toa+ (E) Turn Off Delay E to Q7(1t} HIGH Am2503/Am2504) 15 23 50 75 ns toa(E) Turn On Delay E ta Q7(11) LOW Cp=H,S=L 20 30 60 75 towL (CP) | Minimum LOW Clock Pulse Width 28 46 100 150 ns tpwH(CP) | Minimum HIGH Clock Pulse Width 12 20 70 100 ns fax Maximum Clock Frequency 15 25 3.5 5.0 MHzAm2502/3/4 Family ATLEAST yo ATLEAST SWITCHING TIME WAVEFORMS KEY TO TIMING DIAGRAM sy ae \ Loos i | ($1 MA bee} -| poses i ! } WAVEFGRM INPUTS OUTPUTS ! I ! i : s - HHH wot i se roo . i MUST BE WILL BE I : 1 STEADY STEADY ced ee usin yio Wax wy. MAX fae ae _ 7 me pede mis me iE MI \ may cHance MILE BE FROMHTOL = CHANGIN FROM H TOL meV + : maycHance WILL BE ' FROMLTOH CHANGING i Tye, MX. iy - FROM LTOH Loe yy . DON'T CARE; CHANGING: be ety MAX. toy Max ol ANY CHANGE STATE : m | PERMITTED UNKNOWN 20 a eee ee eee a we ee. es TAY 12802 2508 LIC-229 E - 2903 1504 fare ce fietig tf MAX bh wel a HE ax | LIC-230 DEFINITION OF TERMS SUBSCRIPT TERMS: H_ HIGH, applying to a HIGH logic level or when used with Vcc to indicate high Vec value. 1 Input L LOW, applying to LOW logic level or when used with Vcc to indicate low Vcc value. O Output FUNCTIONAL TERMS: Fan-Gut The logic HIGH or LOW output drive capability in terms of Input Unit Loads. Input Unit Load One T? L gate input load. In the HIGH state it is equal to ly and in the LOW state it is equal to ly. CP The ciock input of the register. CC The conversion complete output. This output remains HtGH during a conversion and goes LOW when a conversion is complete, D The serial data input of the register. E The register enable. This input is used to expand the length of the register and when HiGH forces the Q7(11} register output HIGH and inhibits conversion. When not used for expansion the enable is held at a LOW logic level (Graund). Q7(11) The true output of the MSB of the register. Q7{11) The complement output of the MSB of the register. Qj i = 7(11) to 0 The outputs of the register. S The start input. {f the start input is held LOW for at least a clock period the register will be reset to Q7(11) LOW and ail the remaining outputs HIGH. A start pulse that is LOW for a shorter period of time can be used if it meets the set-up time require- ments of the S input. DO The seriat data output. (The D input delayed one bit). OPERATIONAL TERMS: lL Forward input load current. boy Output HIGH current, forced out of output Voy, test. loi Output LOW current, forced into the output in Vo test. {14 Reverse input load current. Negative Current Current flowing out of the device. Positive Current Current flowing into the device. Vin Minimum logic HIGH input voltage. Vit Maximum logic LOW input voltage. Vou Minimum logic HIGH output voltage with output HIGH current Igy flowing out of output. Vor Maximum logic LOW output voltage with output LOW cur- rent Io. flowing into output. SWITCHING TERMS: ( Measured at the 1.5V logic level). tpg The propagation delay from the clock signal LOW-HIGH transition te an output signa! HiGH-LOW transition. tog+ The propagation delay from the clock signal LOW-HIGH transition to an output signal LOW-HIGH transition. toa (E) The prapagation delay from the Enable signal HtGH- LOW transition to the Q7(11} output signal HIGH-LOW trans- ition. toa+(E) The propagation delay from the Enable signal LOW- HIGH transition to Q7(11) output signal LOW-HIGH transition. t,(D) Set-up time required for the logic level to be present at the data input prior to the clock transition from LOW to HIGH in order for the register to respond. The data input should remain steady between t, max. and t, min, before the clock. t,(5) Set-up time required for a LOW level to be present at the S input prior to the clock transition from LOW to HIGH in order for the register to be reset, or time required for a HIGH level to be present on S before the HIGH to LOW clock transition to prevent resetting. tow(CP} The minimum clock pulse width (LOW or HIGH) required for proper register operation. o-12Am2502/3/4 Family USER NOTES FOR A/D CONVERSION Time Inputs Outputs 1. The register can be used with either current switches ee - that require a low voltage level to turn the switch on, th D S$ E Dg Q7 Og A Ay 23 Ay OQ, Ay CC or current switches that require a high voltage level to ye turn the current switch on. If current switches are used o XK LL X X X X XK X X K XX which turn on with a low logic level the resulting digital 1 Dp HL X LH H H H H H HH output from the register is active LOW. That is, a logic 2 Dg HL D7 OF LH H H H H H H "4" is represented as a low voltage level. If current swit- 3 D, HL Dg D7 Dg L H H H H HoH ches are ses that turn on wee high toate towel then e digital output is active sa logic 1 is repre- 4 Dg Ht 0g D7 Dg OF LH HH HON sented as a high voltage level. 5 Dg HL Dag D7 Dg Dg Dag L H H H H | . 1 6 D. HL Da Dy De De Dg D7 L H HH 2. Fora maximum digital error of +Y%LSB the comparator 2 3 7 6 5 4 73 must be biased. If current switches that require a high 7 D, HL Dy Dz Dg Og Dg D3 Dg L H H voltage level to turn on are used, the comparator should 8 Dg HL Dy Dz Dg Dg Dg D3 Pg BD, L oH be biased +%LSB and if the current switches require a 9 X HL Dg D7 Dg Dg Dg DZ Dg Dy Dg L high logic level to turn on then the comparator must be 10 xX XL X Dz Dg Dg Dy Dg Dg Dy Dg L biased %LSB. xX XH X H NC NC NC NC NC NC NC NC 3. The register, by suitable selection of resistor ladder net- work, can be used to perform either binary or BCD conversion. Additional data input gating should be used to eliminate the possibility of false BCD codes. H = HIGH Voltage Level 4. The register can be used to perform 2s complement L = LOW Vottage Level conversion by offsetting the comparator % full range X = Dont Care +% LSB and using the complement of the MSB Q7 NC = No Change (Q44) as the sign bit. Note: Truth Table for Am2504 is extended to include 5. If the register is truncated and operated in the continuous 12 outputs. conversion made a !ack-up condition may occur on power- on, This situation can be overcome by making the START input the OR function of CC and the appropriate register output. Am25(L)02/3 TIMING CHART iNPUTS: STORT GUTPUTS: Oy CONVERSION COMPLETE ee COT ee eT LIC-231Am2502/3/4 Family Am2502/3 LOADING RULES (IN UNIT LOADS) Am2504 LOADING RULES (IN UNIT LOADS) Input Fanout Input Fanout Pin Unit Load Output Output Pin Unit Load Output Output Input/Output No.s LOW HIGH HIGH LOW Input/Output No.s LOW HIGH HIGH LOW E (2503) 1 15 2 - ~ E 1 15 2 - - ___bO (2502) 1 - - 12 6 DO 2 - - 12 6 cc 2 = - 12 6 cc 3 - = 12 6 Qy 3 = - 2 6 Oy 4 - - 12 8 Q, 4 - - i2 6 a, 5 + 12 6 a5 5 = = 12 6 Q, 6 = = 12 6 - Q3 6 - 12 6 Q, 7 12 6 D 7 1 1 = = Q, 3 12 6 GND 8 _ _ _ _ Og 9 + 12 6 cP 9 i 1 = - NC 10 = = ~ = Ss 10 1 2 - - _ oD "1 1 1 = = OQ, 11 - 12 6 _ GND 12 _ - _ O, 12 = = 12 6 cP i3 1 1 = > Og 13 ~ - 12 6 s 4 2 = a, 14 ~ 12~6 NC 18 = = = a, 15 = ~ 12 6 _O6 160 - - 12 6 Vee ET _ = om 7 = 12 6 a 1 - MSi INTERFACING RULES 8 8 12 6 Equivalent QO, 19 _ 12 6 Input Unit Load _ _ 1 Interfacing Digital Family HiGH LOW 19 20 42 8 Q, 1 21 - _ 12 6 Advanced Micro Devices 9300/2500 Series 1 1 NC 2200~ = - FSC Series 9300 1 1 Q,, 23 _ _ 12 6 Advanced Micro Devices 54/7400 1 1 Veo 24 = = _ Ti Series 54/7400 1 1 . Signetics Series 8200 2.2 HIGH and 1 6mA mearured at 0.4 LOW. nS red 9 24V National Series DM 75/85 1 i DTL Series 930 12 1 NC = No Connection INPUT/OUTPUT INTERFACE CONDITIONS Voltage Interface Conditions LOW & HIGH 20- ge 28 MinIMUM LOGIC g 287 outage * 24 B22 Vit S 20h a MINIMUM LOGIC a br IMMUNITY HIGH" INPUT g 16 (High level) VOLTAGE Soak 3 Saab E z TO Mig = osh E08) waximuw Logie wanmuw vests > 06- arti & VOLTAGE LOW" iNPUT S04 a VOLTAGE 3 NOISE oe IMMUNITY 0.0 (Low levelt DRIVING DEVICE ORIVEN DEVICE You, Vida po OY -o You, Vitg ORIVING ORIVEN DEVICE DEVICE Current Interface Conditions LOW OUTPUT DRIVING INPUT LOAD DAIVEN LOW OUTPUT Ver vu | LOAD I I I OFF | { I | | ON | | eno = Flot Current Interface Conditions HIGH GUTPUT DRIVING INPUT LOAD HIGH | ORIVEN HIGH Voc 6 | | I I ON | 'ou lou, I | OFF, ore | | GNO = LIC-232 3-15Am2502/3/4 Family chock Am2502/3/4 APPLICATION 8 Am 2504 12 BIT SAR Og a ee 050, 0, Arn6012 6022 ANALGG INPUT Continuous Conversion Analog-to- Digital Converter SERIAL DATA OUT CONVERSION COMPLETE PARALLEL, DATA OUT COMPARATOR This shows how the 4m2502/3/4 registers are used with a Digital-to-Analog converter and a comparator to form a very high-speed con- tinuous conversion Analag-to-Digital converter. Canversion time is limited mainly by the speed of the D/A converter and comparator with typical conversion rates of 100,000 conversions per second. LIC-233 Am2502 Metallization and Pad Layouts DIE SIZE 0.087" X 0.105 Am2503 DIE SIZE 0.087" X 0.105" Am2504 DIE SIZE 0.087" X 0.135" ORDERING INFORMATION Order Order Package Temperature Number Number Type Range Bits Am2502DM Am25L02DM Hermetic DIP 55 to +125C 8 Am2503DM Am25L03DM Hermetic DIP 55 to +125C 8 Am2504DM Am25L04DM Hermetic DIP -55 to + 125C 12 Am2502FM Am25L02FM Flat Package ~ 55 to +125C 8 Am2503FM Am25L03FM Flat Package 55 to + 125C 8 Am2504FM AM25L04FM Flat Package 55 to +125C 12 Am2502XM Am25L02XM Dice 55 to + 125C 8 Am2503XM Am25L03XM Dice 55 to +125C 8 Am2504XM Am25L04KM Dice 55 to +125C 8 Am2502DC Am25L02DC Hermetic DIP 0 to +70C 8 Am2503DC Am25L030C Hermetic DIP Oto +70C 8 Am2504DC Am25L04DC Hermetic DIP Oto +70C 12 Am2502PC Am25L02PC Plastic Oto +70C 8 Am2503PC Am25L03PC Plastic Oto +70C 8 Am2504PC Am25L04PC Plastic Oto +70C 12 Am2502XC Am25L02XC Dice Oto +70C & Am2503XC Am25L03XC Dice Oto +70C a Am2504XC Am25L04XC. Dice 0 to +70C 12 *Also available with burn-in processing. To order add suffix B to part number.