1-197
H
0.5 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3150
Features
• 0.5 A Minimum Peak Output
Current
• 15 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1500 V
• 1.0 V Maximum Low Level
Output Voltage (VOL)
Eliminates Need for
Negative Gate Drive
• ICC = 5 mA Maximum Supply
Current
• Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
• Wide Operating VCC Range:
15 to 30 Volts
• 500 ns Maximum Switching
Speeds
• Industrial Temperature
Range:
-40°C to 100°C
• Safety and Regulatory
Approval:
UL Recognized
2500 Vrms for 1 min. per
UL1577
VDE 0884 Approved with
VIORM = 630 Vpeak
(Option 060 only)
CSA Approved
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
Applications
• Isolated IGBT/MOSFET
Gate Drive
• AC and Brushless DC Motor
Drives
• Industrial Inverters
• Switch Mode Power
Supplies (SMPS)
Description
The HCPL-3150 consists of a
GaAsP LED optically coupled to
an integrated circuit with a power
output stage. This optocoupler is
ideally suited for driving power
IGBTs and MOSFETs used in
motor control inverter applica-
tions. The high operating voltage
range of the output stage pro-
vides the drive voltages required
by gate controlled devices. The
voltage and current supplied by
this optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/50 A.
For IGBTs with higher ratings,
the HCPL-3120 can be used to
drive a discrete power stage
which drives the IGBT gate.
Truth Table
VCC - VEE VCC - VEE
“Positive Going” “Negative-Going”
LED (i.e., Turn-On) (i.e., Turn-Off) VO
OFF 0 - 30 V 0 - 30 V LOW
ON 0 - 11 V 0 - 9.5 V LOW
ON 11 - 13.5 V 9.5 - 12 V TRANSITION
ON 13.5 - 30 V 12 - 30 V HIGH
A 0.1
µ
F bypass capacitor must be connected between pins 5 and 8.
Functional Diagram
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
V
O
V
EE
5965-4780E
1-198
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-3150#XXX
No Option = Standard DIP package, 50 per tube.
060 = VDE 0884 VIORM = 630 Vpeak Option, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
Package Outline Drawings
Standard DIP Package
Gull-Wing Surface-Mount Option 300
9.40 (0.370)
9.90 (0.390)
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
HP 3150 Z
YYWW
DATE CODE
0.76 (0.030)
1.40 (0.055) 2.28 (0.090)
2.80 (0.110)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
6.10 (0.240)
6.60 (0.260)
0.20 (0.008)
0.33 (0.013)
5° TYP.
7.36 (0.290)
7.88 (0.310)
1
2
3
4
8
7
6
5
5678
4321
GND1
V
DD1
V
IN+
V
IN–
GND2
V
DD2
V
OUT+
V
OUT–
PIN DIAGRAM
PIN ONE
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
OPTION CODE*
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
0.20 (0.008)
0.33 (0.013)
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
MOLDED
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 ± 0.320
(0.043 ± 0.013)
4.19
(0.165)MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED):
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
xx.xx = 0.01
xx.xxx = 0.005
HP 3150 Z
YYWW
1-199
VDE 0884 Insulation Characteristics (Option 060 Only)
Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms I-IV
for rated mains voltage ≤ 600 Vrms I-III
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 630 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 Vpeak
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 945 Vpeak
Partial discharge < 5 pC
Highest Allowable Overvoltage* VIOTM 6000 Vpeak
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values – Maximum Values Allowed in the Event
of a Failure, Also See Figure 37, Thermal Derating Curve.
Case Temperature TS175 °C
Input Current IS, INPUT 230 mA
Output Power PS, OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS≥ 109Ω
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section, (VDE 0884) for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
Regulatory Information
The HCPL-3150 has been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
VDE (Option 060 only)
Approved under VDE 0884/06.92
with VIORM = 630 Vpeak.
Reflow Temperature Profile
240
∆T = 115°C, 0.3°C/SEC
0
∆T = 100°C, 1.5°C/SEC
∆T = 145°C, 1°C/SEC
TIME – MINUTES
TEMPERATURE – °C
220
200
180
160
140
120
100
80
60
40
20
0
260
123456789101112
MAXIMUM SOLDER REFLOW THERMAL PROFILE
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
1-200
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage (VCC - VEE) 15 30 Volts
Input Current (ON) IF(ON) 716mA
Input Voltage (OFF) VF(OFF) -3.0 0.8 V
Operating Temperature TA-40 100 °C
Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(101) 7.1 mm Measured from input terminals to output
(External Clearance) terminals, shortest distance through air.
Minimum External Tracking L(102) 7.4 mm Measured from input terminals to output
(External Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08 mm Through insulation distance conductor to
(Internal Clearance) conductor.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 µs pulse width, 300 pps)
Reverse Input Voltage VR5 Volts
“High” Peak Output Current IOH(PEAK) 0.6 A 2
“Low” Peak Output Current IOL(PEAK) 0.6 A 2
Supply Voltage (VCC - VEE) 0 35 Volts
Output Voltage VO(PEAK) 0V
CC Volts
Output Power Dissipation PO250 mW 3
Total Power Dissipation PT295 mW 4
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Package Outline Drawings Section
1-201
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
High Level IOH 0.1 0.4 A VO = (VCC - 4 V) 2, 3, 5
0.5 VO = (VCC - 15 V) 2
Low Level IOL 0.1 0.6 A VO = (VEE + 2.5 V) 5, 6 5
0.5 VO = (VEE + 15 V) 2
High Level Output VOH (VCC - 4) (VCC - 3) V IO = -100 mA 1, 3 6, 7
Voltage 19
Low Level Output VOL 0.4 1.0 V IO = 100 mA 4, 6
Voltage 20
High Level ICCH 2.5 5.0 mA Output Open, 7, 8
Supply Current IF = 7 to 16 mA
Low Level ICCL 2.7 5.0 mA Output Open,
Supply Current VF = -3.0 to +0.8 V
Threshold Input IFLH 2.2 5.0 mA IO = 0 mA, 9, 15,
Current Low to High VO > 5 V 21
Threshold Input VFHL 0.8 V
Voltage High to Low
Input Forward Voltage VF1.2 1.5 1.8 V IF = 10 mA 16
Temperature ∆VF/∆TA-1.6 mV/°CI
F
= 10 mA
Coefficient of
Forward Voltage
Input Reverse BVR5VI
R
= 10 µA
Breakdown Voltage
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V
UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VO > 5 V, 22,
VUVLO- 9.5 10.7 12.0
UVLO Hysteresis UVLOHYS 1.6 V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Output Current
17
18
Output Current
IF = 10 mA 36
1-202
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPLH 0.10 0.30 0.50 µs Rg = 47 Ω, 10, 11, 14
Time to High Cg = 3 nF, 12, 13
Output Level f = 10 kHz, 14, 23
Duty Cycle = 50%
Propagation Delay tPHL 0.10 0.27 0.50 µs
Time to Low
Output Level
Pulse Width PWD 0.3 µs15
Distortion
Propagation Delay PDD -0.35 0.35 µs 34,35 10
Difference Between (tPHL - tPLH)
Any Two Parts
Rise Time tr0.1 µs23
Fall Time tf0.1 µs
UVLO Turn On tUVLO ON 0.8 µsV
O
> 5 V, 22
Delay IF = 10 mA
UVLO Turn Off tUVLO OFF 0.6 µsV
O
< 5 V,
Delay IF = 10 mA
Output High Level |CMH| 15 30 kV/µsT
A
= 25°C, 24 11, 12
Common Mode IF = 10 to 16 mA,
Transient VCM = 1500 V,
Immunity VCC = 30 V
Output Low Level |CML| 15 30 kV/µsT
A
= 25°C, 11, 13
Common Mode VCM = 1500 V,
Transient VF = 0 V,
Immunity VCC = 30 V
Package Characteristics
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Input-Output VISO 2500 Vrms RH < 50%, 8, 9
Momentary t = 1 min.,
Withstand Voltage** TA = 25°C
Resistance RI-O 1012 ΩVI-O = 500 VDC 9
(Input - Output)
Capacitance CI-O 0.6 pF f = 1 MHz
(Input - Output)
LED-to-Case θLC 391 °C/W Thermocouple 28
Thermal Resistance
LED-to-Detector θLD 439 °C/W
Thermal Resistance
Detector-to-Case θDC 119 °C/W
Thermal Resistance
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074 entitled “Optocoupler Input-Output Endurance Voltage.”
located at center
underside of
package
1-203
Notes:
1. Derate linearly above 70°C free-air
temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with IO peak minimum = 0.5 A. See
Applications section for additional
details on limiting IOH peak.
3. Derate linearly above 70°C free-air
temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air
temperature at a rate of 5.4 mW/°C.
The maximum LED junction tempera-
ture should not exceed 125°C.
5. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
6. In this test V
OH is measured with a dc
load current. When driving capacitive
loads VOH will approach VCC as IOH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥3000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristics
Table, if applicable.
9. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
10. The difference between tPHL and tPLH
between any two HCPL-3150 parts
under the same test condition.
11. Pins 1 and 4 need to be connected to
LED common.
12. Common mode transient immunity in
the high state is the maximum
tolerable |dVCM/dt| of the common
mode pulse, VCM, to assure that the
output will remain in the high state
(i.e., VO> 15.0 V).
13. Common mode transient immunity in
a low state is the maximum tolerable
|dVCM/dt| of the common mode
pulse, VCM, to assure that the output
will remain in a low state (i.e.,
VO< 1.0 V).
14. This load condition approximates the
gate load of a 1200 V/25 A IGBT.
15. Pulse Width Distortion (PWD) is
defined as |tPHL-tPLH| for any given
device.
Figure 4. VOL vs. Temperature. Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.
I
OL
– OUTPUT LOW CURRENT – A
-40
0
T
A
– TEMPERATURE – °C
100
0.8
0.4
-20
1.0
02040
0.2
60 80
V
F(OFF)
= -3.0 to 0.8 V
V
OUT
= 2.5 V
V
CC
= 15 to 30 V
V
EE
= 0 V
0.6
V
OL
– OUTPUT LOW VOLTAGE – V
-40
0
T
A
– TEMPERATURE – °C
100
0.8
0.6
-20
1.0
02040
0.2
60 80
V
F(OFF)
= -3.0 to 0.8 V
I
OUT
= 100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
0.4
V
OL
– OUTPUT LOW VOLTAGE – V
0
0
I
OL
– OUTPUT LOW CURRENT – A
1.0
4
0.2
5
0.4 0.6
1
0.8
V
F(OFF)
= -3.0 to 0.8 V
V
CC
= 15 to 30 V
V
EE
= 0 V
2
100 °C
25 °C
-40 °C
3
Figure 1. VOH vs. Temperature. Figure 2. IOH vs. Temperature. Figure 3. VOH vs. IOH.
(V
OH
- V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-40
-4
T
A
– TEMPERATURE – °C
100
-1
-2
-20
0
02040
-3
60 80
I
F
= 7 to 16 mA
I
OUT
= -100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
I
OH
– OUTPUT HIGH CURRENT – A
-40
0.25
T
A
– TEMPERATURE – °C
100
0.45
0.40
-20
0.50
02040
0.30
60 80
I
F
= 7 to 16 mA
V
OUT
= V
CC
- 4 V
V
CC
= 15 to 30 V
V
EE
= 0 V
0.35
(V
OH
- V
CC
) – OUTPUT HIGH VOLTAGE DROP – V
0
-6
I
OH
– OUTPUT HIGH CURRENT – A
1.0
-2
-3
0.2
-1
0.4 0.6
-5
0.8
I
F
= 7 to 16 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
-4
100 °C
25 °C
-40 °C
1-204
V
O
– OUTPUT VOLTAGE – V
0
0
I
F
– FORWARD LED CURRENT – mA
5
25
15
1
30
2
5
34
20
10
Figure 15. Transfer Characteristics.Figure 14. Propagation Delay vs. Cg.Figure 13. Propagation Delay vs. Rg.
I
CC
– SUPPLY CURRENT – mA
-40
1.5
T
A
– TEMPERATURE – °C
100
3.0
2.5
-20
3.5
02040
2.0
60 80
V
CC
= 30 V
V
EE
= 0 V
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
I
CCH
I
CCL
I
CC
– SUPPLY CURRENT – mA
15
1.5
V
CC
– SUPPLY VOLTAGE – V
30
3.0
2.5
3.5
20
2.0
25
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
T
A
= 25 °C
V
EE
= 0 V
I
CCH
I
CCL
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-40
0
T
A
– TEMPERATURE – °C
100
3
2
-20
4
02040
1
60 80
5V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
Figure 10. Propagation Delay vs. VCC. Figure 11. Propagation Delay vs. IF. Figure 12. Propagation Delay vs.
Temperature.
Figure 7. ICC vs. Temperature. Figure 8. ICC vs. VCC. Figure 9. IFLH vs. Temperature.
T
p
– PROPAGATION DELAY – ns
15
100
V
CC
– SUPPLY VOLTAGE – V
30
400
300
500
20
200
25
I
F
= 10 mA
T
A
= 25 °C
Rg = 47 Ω
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
T
p
– PROPAGATION DELAY – ns
6
100
I
F
– FORWARD LED CURRENT – mA
16
400
300
500
10
200
12
V
CC
= 30 V, V
EE
= 0 V
Rg = 47 Ω, Cg = 3 nF
T
A
= 25 °C
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
148
T
p
– PROPAGATION DELAY – ns
-40
100
T
A
– TEMPERATURE – °C
100
400
300
-20
500
02040
200
60 80
T
PLH
T
PHL
I
F(ON)
= 10 mA
I
F(OFF)
= 0 mA
V
CC
= 30 V, V
EE
= 0 V
Rg = 47 Ω, Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
– PROPAGATION DELAY – ns
0
100
Rg – SERIES LOAD RESISTANCE – Ω
200
400
300
50
500
100
200
150
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
– PROPAGATION DELAY – ns
0
100
Cg – LOAD CAPACITANCE – nF
100
400
300
20
500
40
200
60 80
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Rg = 47 Ω
DUTY CYCLE = 50%
f = 10 kHz
1-205
Figure 16. Input Current vs. Forward
Voltage.
Figure 22. UVLO Test Circuit.
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 7 to
16 mA +
–
2
4
8
6
7
5
100 mA
V
OH
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
+
–
2
4
8
6
7
5
V
O
> 5 V
Figure 17. IOH Test Circuit.
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 7 to
16 mA +
–
2
4
8
6
7
5
+
–4 V
I
OH
Figure 18. IOL Test Circuit. Figure 19. VOH Test Circuit.
0.1 µF
V
CC
= 15
to 30 V
1
3
+
–
2
4
8
6
7
5
2.5 V
I
OL
+
–
0.1 µF
V
CC
= 15
to 30 V
1
3
+
–
2
4
8
6
7
5
100 mA
V
OL
Figure 20. VOL Test Circuit. Figure 21. IFLH Test Circuit.
I
F
– FORWARD CURRENT – mA
1.10
0.001
V
F
– FORWARD VOLTAGE – V
1.60
10
1.0
0.1
1.20
1000
1.30 1.40 1.50
T
A
= 25°C
I
F
V
F
+
–
0.01
100
0.1 µF
V
CC
1
3
I
F
= 10 mA +
–
2
4
8
6
7
5
V
O
> 5 V
1-206
Figure 25. Recommended LED Drive and Application Circuit.
Applications Information
Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the
HCPL-3150 has a very low
maximum VOL specification of
1.0 V. The HCPL-3150 realizes
this very low VOL by using a
DMOS transistor with 4 Ω
(typical) on resistance in its pull
down circuit. When the
HCPL-3150 is in the low state,
the IGBT gate is shorted to the
emitter by Rg + 4 Ω. Minimizing
Rg and the lead inductance from
the HCPL-3150 to the IGBT gate
and emitter (possibly by
mounting the HCPL-3150 on a
small PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in many
applications as shown in Figure
25. Care should be taken with
such a PC board design to avoid
routing the IGBT collector or
emitter traces close to the HCPL-
3150 input as this can result in
unwanted coupling of transient
signals into the HCPL-3150 and
degrade performance. (If the
IGBT drain must be routed near
the HCPL-3150 input, then the
LED should be reverse-biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from turning
on the HCPL-3150.)
Figure 24. CMR Test Circuit and Waveforms.
0.1 µF V
CC
= 15
to 30 V
47 Ω
1
3
I
F
= 7 to 16 mA
V
O
+
–
+
–
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
3 nF
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
0.1 µF
V
CC
= 30 V
1
3
I
F
V
O
+
–
+
–
2
4
8
6
7
5
A
+
–
B
V
CM
= 1500 V
5 V
V
CM
∆t
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
∆t
V
CM
δV
δt=
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 18 V
1
3
+
–
2
4
8
6
7
5
270 Ω
HCPL-3150
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
1-207
Figure 26. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses.
Step 1: Calculate Rg Minimum
From the IOL Peak Specifica-
tion. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3150.
(VCC – VEE - VOL)
Rg
≥
–––––––––––––––
IOLPEAK
(VCC – VEE - 1.7 V)
= ––––––––––––––––
IOLPEAK
(15 V + 5 V - 1.7 V)
= ––––––––––––––––––
0.6 A
= 30.5
Ω
The VOL value of 2 V in the pre-
vious equation is a conservative
value of VOL at the peak current
of 0.6 A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3150 is not an ideal
voltage step. This results in lower
peak currents (more margin)
than predicted by this analysis.
When negative gate drive is not
used VEE in the previous equation
is equal to zero volts.
Step 2: Check the HCPL-3150
Power Dissipation and
Increase Rg if Necessary. The
HCPL-3150 total power dissipa-
tion (PT) is equal to the sum of
the emitter power (PE) and the
output power (PO):
PT = PE + PO
PE = IF•V
F•Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= ICC•(V
CC - VEE)
+ ESW(RG, QG)•f
For the circuit in Figure 26 with IF
(worst case) = 16 mA, Rg =
30.5 Ω, Max Duty Cycle = 80%,
Qg = 500 nC, f = 20 kHz and TA
max = 90°C:
PE = 16 mA•1.8 V•0.8 = 23 mW
PO = 4.25 mA•20 V
+ 4.0
µ
J•20 kHz
= 85 mW + 80 mW
= 165 mW
> 154 mW (PO(MAX) @ 90°C
= 250 mW−20C•4.8 mW/C)
PO Parameter Description
ICC Supply Current
VCC Positive Supply Voltage
VEE Negative Supply Voltage
ESW(Rg,Qg) Energy Dissipated in the HCPL-3150 for each
IGBT Switching Cycle (See Figure 27)
f Switching Frequency
PE
Parameter Description
IFLED Current
VFLED On Voltage
Duty Cycle Maximum LED
Duty Cycle
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 15 V
1
3
+
–
2
4
8
6
7
5
HCPL-3150
Rg
Q1
Q2
V
EE
= -5 V
–
+
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
1-208
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40°C)
to ICC max at 90°C (see Figure 7).
Since PO for this case is greater
than PO(MAX), Rg must be
increased to reduce the HCPL-
3150 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 154 mW - 85 mW
= 69 mW
PO(SWITCHINGMAX)
ESW(MAX) = –––––––––––––––
f
69 mW
= ––––––– = 3.45
µ
J
20 kHz
For Qg = 500 nC, from Figure
27, a value of ESW = 3.45 µJ
gives a Rg = 41 Ω.
Thermal Model
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28. The thermal resistance
values given in this model can be
used to calculate the tempera-
tures at each node for a given
operating condition. As shown by
the model, all heat generated
flows through θCA which raises
the case temperature TC
accordingly. The value of θCA
depends on the conditions of the
board design and is, therefore,
determined by the designer. The
value of θCA = 83°C/W was
obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL-
3150 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a θCAvalue of 83°C/W.
Inserting the values for θLC and
θDC shown in Figure 28 gives:
TJE = P
E•(230°C/W + θCA)
+ P
D•(49°C/W + θCA) + TA
TJD = P
E•(49°C/W + θCA)
+ P
D•(104°C/W + θCA) + TA
For example, given PE = 45 mW,
PO = 250 mW, TA = 70°C and θCA
= 83°C/W:
shown in Figure 29. The HCPL-
3150 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capaci-
tively coupled current away from
the sensitive IC circuitry. How
ever, this shield does not
eliminate the capacitive coupling
between the LED and optocoup-
ler pins 5-8 as shown in
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
TJE = P
E •
(θLC||(θLD + θDC) + θCA)
θ
LC • θDC
+ PD•(–––––––––––––––– + θCA) + TA
θLC + θDC + θLD
θLC • θDC
TJD = PE (––––––––––––––– + θCA)
θLC + θDC + θLD
+ P
D•(θDC||(θLD + θLC) + θCA) + TA
TJE and TJD should be limited to
125°C based on the board layout
and part placement (θCA) specific
to the application.
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
TJE = PE•313°C/W + PD•132°C/W + TA
= 45 mW•313°C/W + 250 mW
•132°C/W + 70°C = 117°C
TJD = PE•132°C/W + PD•187°C/W + TA
= 45 mW•132C/W + 250 mW
•187°C/W + 70°C = 123°C
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
3
20
7
40
2
60 80
6Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
5
4
1
V
CC
= 19 V
V
EE
= -9 V
1-209
TJE = LED junction temperature
TJD = detector IC junction temperature
TC= case temperature measured at the center of the package bottom
θLC = LED-to-case thermal resistance
θLD = LED-to-detector thermal resistance
θDC = detector-to-case thermal resistance
θCA = case-to-ambient thermal resistance
∗θCA will depend on the board design and the placement of the part.
CMR with the LED On
(CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum IFLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMRL)
A high CMR LED drive circuit
must keep the LED off
(VF≤VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 31, the current flowing
through CLEDP also flows through
the RSAT and VSAT of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than VF(OFF), the
LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150
output is in the high state and the
supply voltage drops below the
HCPL-3150 VUVLO- threshold
(9.5 <VUVLO- <12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3150 output is in
the low state and the supply
voltage rises above the HCPL-
3150 VUVLO+ threshold
(11.0 < VUVLO+ < 13.5), the
optocoupler will go into the high
state (assuming LED is “ON”)
with a typical delay, UVLO TURN
On Delay, of 0.8 µs.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-3150 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
Figure 28. Thermal Model.
θ
LD
= 439°C/W
T
JE
T
JD
θ
LC
= 391°C/W θ
DC
= 119°C/W
θ
CA
= 83°C/W*
T
C
T
A
1-210
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this condi-
tions is equal to the maximum
value of the propagation delay
difference specification, PDDMAX,
which is specified to be 350 ns
over the operating temperature
range of -40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum propaga-
tion delay difference specifica-
tions as shown in Figure 35. The
maximum dead time for the
HCPL-3150 is 700 ns (= 350 ns -
(-350 ns)) over an operating
temperature range of -40°C to
100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers. Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
Figure 31. Equivalent Circuit for Figure 25 During
Common Mode Transient.
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
Figure 32. Not Recommended Open
Collector Drive Circuit.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
1-211
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHL MAX
-
t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
Figure 34. Minimum LED Skew for Zero Dead Time.
Figure 35. Waveforms for Dead Time.
Figure 36.Under Voltage Lock Out.
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1) (12.3, 0.1)
Figure 37. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
I
S
(mA)
125
100
300
500
700
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
-
t
PHL MIN
) + (t
PLH MAX
-
t
PLH MIN
)
= (t
PHL MAX
-
t
PLH MIN
) – (t
PHL MIN
-
t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MIN
t
PHL MAX
t
PLH MAX
= PDD* MAX
(t
PHL-
t
PLH
)
MAX