BUK9230-55A
N-channel TrenchMOS logic level FET
Rev. 04 — 15 June 2010 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Q101 compliant
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive and general purpose
power switching
Motors, lamps and soleno ids
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source
voltage Tj25 °C; Tj175°C --55V
IDdrain current VGS =5V; T
mb =2C;
see Figure 1; see Figure 3 --38A
Ptot total power
dissipation Tmb = 25 °C; see Figure 2 --88W
Static characteristics
RDSon drain-source
on-state
resistance
VGS =4.5V; I
D=15A;
Tj=2C --33m
VGS =10V; I
D=15A;
Tj=2C - 2327m
VGS =5V; I
D=15A;
Tj=2C;
see Figure 12; see Figure 13
- 2630m
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
ID=34A; V
sup 55 V;
RGS =50; VGS =5V;
Tj(init) = 25 °C; unclamped
--57.8mJ
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 2 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
2. Pinning information
3. Ordering information
Table 2. Pinning info rmation
Pin Symbol Description Simplified outline Graphi c sy mbol
1 G gate
SOT428 (DPAK)
2 D drain
3Ssource
mb D mounting base; connected to
drain
3
2
mb
1
S
D
G
mbb076
Table 3. Orderi ng information
Type number Package
Name Description Version
BUK9230-55A DPAK plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped) SOT428
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 3 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
4. Limiting values
[1] Peak drain current is limited by chip, not package.
Table 4. Limiting values
In accordance with the Absolute Maxi mum Rating System (IEC 60134).
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj25 °C; Tj175°C --55V
VDGR drain-gate voltage RGS =20--55V
VGS gate-source voltage -10 - 10 V
IDdrain current Tmb =2C; V
GS =5V; see Figure 1;
see Figure 3 --38A
Tmb =10C; V
GS =5V; see Figure 1 --27A
IDM peak drain current Tmb =2C; t
p10 µs; pu lsed;
see Figure 3 [1] - - 154 A
Ptot total power dissipation Tmb =2C; see Figure 2 --88W
Tstg storage temperature -55 - 175 °C
Tjjunction temperature -55 - 175 °C
VGSM peak gate-source
voltage pulsed; tp50 µs -15 - 15 V
Source-drain diode
ISsource current Tmb =25°C --38A
ISM peak source current tp10 µs; pulsed; Tmb = 25 °C - - 154 A
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
ID=34A; V
sup 55 V; RGS =50;
VGS =5V; T
j(init) = 25 ° C; unclamped - - 57.8 mJ
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 4 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
Fig 1. Normalized continuous drain current as a
function of mounting base temperature Fig 2. Normalized total po we r dissi pa tio n as a
function of mounting ba s e te mp e rature
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
Tmb (°C)
0 20015050 100
03aa24
40
80
120
Ider
(%)
0
Tmb (°C)
0 20015050 100
03aa16
40
80
120
Pder
(%)
0
03na89
1
10
102
103
1 10 102
VDS (V)
ID
(A)
D.C.
100 ms
10 ms
RDSon = VDS / ID
1 ms
tp = 10 μs
100 μs
tp
tp
T
P
t
T
δ =
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 5 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance
from junction to
mounting base
--1.7K/W
Rth(j-a) thermal resistance
from junction to
ambient
see Figure 4 - 71.4 - K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
03na90
Single Shot
0.2
0.1
0.05
0.02
102
101
1
10
106105104103102101 1
tp (s)
Zth(j-mb)
(K/W)
δ = 0.5
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 6 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=0.25mA; V
GS =0V; T
j=25°C 55--V
ID=0.25mA; V
GS =0V; T
j= -55 °C 50 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS =V
GS; Tj=-5C;
see Figure 11 --2.3V
ID=1mA; V
DS =V
GS; Tj=2C;
see Figure 11 11.52V
ID=1mA; V
DS =V
GS; Tj= 175 °C;
see Figure 11 0.5--V
IDSS drain leakage current VDS =55V; V
GS =0V; T
j= 175 °C - - 500 µA
VDS =55V; V
GS =0V; T
j= 25 °C - 0.05 10 µA
IGSS gate leakage current VDS =0V; V
GS =10V; T
j= 25 °C - 2 100 nA
VDS =0V; V
GS =-10V; T
j= 25 °C - 2 100 nA
RDSon drain-source on-state
resistance VGS =4.5V; I
D=15A; T
j=25°C --33m
VGS =10V; I
D=15A; T
j= 25 °C - 23 27 m
VGS =5V; I
D=15A; T
j= 175 °C;
see Figure 12 ; see Figure 13 --60m
VGS =5V; I
D=15A; T
j=2C;
see Figure 12 ; see Figure 13 - 2630m
Dynamic characteristics
Ciss input capacitance VGS =0V; V
DS =25V; f=1MHz;
Tj=2C; see Figure 14 - 1294 1725 pF
Coss output capacitance - 210 252 pF
Crss reverse transfer
capacitance - 142 195 pF
td(on) turn-on delay time VDS =30V; R
L=1.2; VGS =5V;
RG(ext) =10; Tj=2C -14-ns
trrise time - 125 - ns
td(off) turn-off delay time - 64 - ns
tffall time - 68 - ns
LDinternal drain
inductance measured from drain lead from package
to centre of die ; Tj=2C -2.5-nH
LSinternal source
inductance measured from source lead from
package to source bond pad ;
Tj=2C
-7.5-nH
Source-drain diode
VSD source-drain voltage IS=25A; V
GS =0V; T
j=2C;
see Figure 15 - 0.85 1.2 V
trr reverse recovery time IS=20A; dI
S/dt = -100 A/µs;
VGS =-10V; V
DS =30V; T
j=2C -35-ns
Qrrecovered charge - 70 - nC
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 7 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
Fig 5. Output characteristics: drain current as a
function of drain-source volta ge; typ ical values Fig 6. Drain-source on-state re sistance as a function
of gate-source voltage; typical value s
Fig 7. Sub-threshold drain current as a function of
gate-source voltage Fig 8. Forward transconductance as a function of
drain current; typical values
03na86
0
40
80
120
160
0246810
VDS (V)
ID
(A)
2.2
3
4
5
6
7
8
VGS (V) = 10 9
03na84
10
15
20
25
30
35
246810
VGS (V)
RDSon
(mΩ)
03aa36
10-6
10-5
10-4
10-3
10-2
10-1
0123
VGS (V)
ID
(A)
maxtypmin
03na85
0
5
10
15
20
25
30
35
020406080
ID (A)
gfs
(S)
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 8 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
Fig 9. Transfer characteristics: drain curre nt as a
function of gate-source voltage; typical values Fig 10. Gate-source voltage as a function of turn-on
gate charge; typical values
Fig 11. Gate-source threshold voltage as a function of
junction temperature Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
03na81
0
20
40
60
80
100
0123456
VGS (V)
ID
(A)
Tj = 175 °C
Tj = 25 °C
03na83
0
1
2
3
4
5
6
0102030
QG (nC)
VGS
(V)
VDD = 44 V
VDD = 14 V
03aa33
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
Tj (°C)
VGS(th)
(V)
max
typ
min
03na87
15
25
35
45
55
0 102030405060708090
ID (A)
RDSon
(mΩ)
5
3.2 3.4
3.6 3.8 4
VGS(V) = 3
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 9 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 15. Reverse diode curren t as a function of reverse diod e voltage; typical values
Tj (°C)
60 180120060
03aa28
1.2
0.6
1.8
2.4
a
0
03na88
0
500
1000
1500
2000
2500
3000
3500
102101 1 10 102
VDS (V)
C
(pF)
Crss
Coss
Ciss
03na82
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VSD (V)
IS
(A)
Tj = 175 °C
Tj = 25 °C
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 10 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
7. Package outline
Fig 16. Package outline SOT428 (DPAK)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT428 SC-63
TO-252
SOT428
06-02-14
06-03-16
DIMENSIONS (mm are the original dimensions)
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
A
2
13
E1
D2
D1HD
LL1
L2
e1
e
mounting
base
wA
M
b
E
b2
b1c
A1
y
0 5 10 mm
scale
UNIT
mm 0.93
0.46 5.46
5.00 0.56
0.20 6.22
5.98 6.73
6.47 10.4
9.6 2.95
2.55
A1
2.38
2.22
Ab
2
1.1
0.9
b1e1
0.89
0.71
bcD
1
0.9
0.5
L2
Ee
2.285 4.57
4.0
D2
min
4.45
E1
min
0.5
L1
min
HDLw
0.2
y
max
0.2
A
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 11 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BUK9230-55A v.4 20100615 Product data sheet - BUK9230-55A v.3
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
BUK9230-5 5A v.3
(9397 750 07741) 20010130 Product Specification - -
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 12 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The p r oduct status of device(s) described in this document may have changed since th is document w as published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specifica t io nThe information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is be lieved to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medica l, military, aircraft, space or life suppo rt equipment,
nor in applications where failure or malf unction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application /use or t he application/use of customer’s third par ty
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and t he
product. NXP Semiconductors does not accept any liability in this respect.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or mo re limiting values (as defin ed in the
Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
BUK9230-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 15 June 2010 13 of 14
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
Export control — This document as well as the item(s) d escribed herein may
be subject to export control regulat i ons. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All referenced brand s, product names, service names and trademarks
are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFAR E Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BUK9230-55A
N-channel TrenchMOS logic level FET
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 June 2010
Document identifier: BUK9230-55A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .1 2
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3
10 Contact information. . . . . . . . . . . . . . . . . . . . . .13