© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4 1Publication Order Number:
NCP81111/D
NCP81111
3 Phase VR12.56 High
Speed Digital Controller
with SVID and I2C
Interfaces for 5 MHz
Desktop, Notebook CPU
Applications
The NCP81111 is a high performance digital single output three
phase VR12.5−6 compatible buck solution optimized to operate at
frequencies up to 5 MHz for Intel CPU applications. The NCP81111
and can also work as a general purpose I2C controlled multiphase
voltage regulator. The NCP81111 is designed to support the
NCP81163 digital phase doubler IC which expands the capability of
the part to 6 phases for high current handling. The controller includes
true differential voltage sensing, differential current sensing, digital
input voltage feed−forward, DAC feed forward, and adaptive voltage
positioning. These features combine to provide an accurately
regulated dynamic voltage system. The control system makes use of
digital constant on time modulation and is combined with an analog
and digital current sensing system. This system provides the fastest
initial response to dynamic load events to reduced system cost. On
board user programmable memory is included for configuring the
controller’s parameters. User programmable voltage and droop
compensation is internally integrated to minimize the total board
space used. The NCP81111 is optimized for use with DRMOS.
Features
•Meets Intel®’s VR12.5 Specifications
•On Board EEPROM for User Configuration
•High Performance Digital Architecture
•Dynamic Reference Injection
•Fully Differential Voltage Current Sense Amplifiers
•“Lossless” DCR Current Sensing for Current Balancing
•Thermally Compensated Inductor Current Sensing for Droop
•User Adjustable Internal Compensation
•Switching Frequency Range of 250 kHz − 5.0 MHz
•Input Voltage Feed−forward
•Startup into Pre−Charged Loads
•Power Saving Phase Shedding
•Supports Lower Power Operation in PS3
•This is a Pb−Free Device
Applications
•Desktop, Notebook Processors, and General Purpose I2C Controlled
Multiphase Regulators.
MARKING
DIAGRAM
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QFN32
CASE 485CE
32
1NCP81111
zzRr
AWLYYWWG
G
1
NCP81111 = Specific Device Code
zz = Configuration Option
Rr = Revision Number
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
Device* Package Shipping†
ORDERING INFORMATION
NCP81111MNDFTXG QFN32
(Pb−Free) 2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(Note: Microdot may be in either location)
*zz = Configurable Option, please contact Sales fo
r
additional information.
NCP81111MNzzTXG QFN32
(Pb−Free) 2500 / Tape &
Reel
NCP81111
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3
CSP1
CSN1
6BIT FLASH
CSP
CSN
CSOUT<5:0>
PHASE MUX
+ CSP1
+ CSP2
+ CSP3
− CSN1
− CSN2
− CSN3
CSP
CSN
TON CONTROL
FREQ SETTING
CSOUT
TON1<>
TON2<>
TON3<>
PSx STATE
VFF_OUT<>
CSP2
CSN2
UVLO
VCCA
UVLO
VDIG
CSP3
DIGITAL INTEGRATOR
V1P3
DIFFOUT Ioffset
GAIN<>
STOP
DAC
ZCD COMPARE
CSP1
CSN1
ZCD_THRESHOLD<>
ZDC1
HIGH SPEED PROGRAMMABLE COMPENSATOR
COMP
DIFFOUT
COMPENSATION SETTINGS<>
VFB
−
+DAC
STOP CONTROL
V_THRESHOLD<>
COMP
STOP
AtoD
VFF MONITOR
VFF VFF_OUT<>
RAMP GENERATOR
Ramp Current<>
Ramp Cap<>
Ramp Reset Voltage <>
Phase Count<>
RAMP
RAMP_GO
PWM CONTROL
TRIGGER PWM_GO1
PWM_GO2
PWM_GO3FAULTS
PSx STATE
RAMP_GO
SMOD1
SMOD2
SMOD3
ZCD1
PHASE COUNT<>
5us Blanking
UVP MONITOR
DIFFOUT
0.85V
UVP
DUAL DAC
VID<>
OV_THRESHOLD<>
DAC
OV_TRSHLD
3V
AGND
OVP COMPARATOR
OV_TRSHLD
VSP
VSN
OVP
Av
IOUT GAIN CONTROL
CSP
CSN
IOUT_P
IOUT_N
GAIN<>
Av
DROOP GAIN CONTROL
CSP
CSN
DROOP_P
DROOP_N
GAIN<>
10BIT AtoD
IN_P
IN_N OUT<9:0>
Nonvolatile Memory
DIGITAL INTERFACE
SDA
SCLK
SETTINGS
ANALOG MONITORING
FAULT STATUS
DRVON
VR_RDY
VRHOT#
SCL
EN
ALERT#
SDIO
THERMAL COMPENSATION
TEMP_CONTROL<>
CSP
CSN
THERMAL COMPENSATION
TEMP_CONTROL<>
CSP
CSN
THERMAL COMPENSATION
TEMP_CONTROL<>
CSP
CSN
CSN3
PHASE MUX
+VSP
+T_SENSE
IOUT_P
− VSN
−T_SENSE
IOUT_N
AOUT_P
AOUT_N
CURRENT LIMIT CURRENT SUMMING AMP
+ CSP1
+ CSP2
+ CSP3
− CSN1
− CSN2
− CSN3
CSP
CSN
IOUT CURRENT SUMMING AMP
+ CSP1
+ CSP2
+ CSP3
− CSN1
− CSN2
− CSN3
CSP
CSN
DROOP CURRENT SUMMING AMP
+ CSP1
+ CSP2
+ CSP3
− CSN1
− CSN2
− CSN3
CSP
CSN 100MHz
ERROR AMP
VP
VN
COMP
SUMMING AMP
+ VSP
− VSN
− DAC
+ GND
+ V1P3
DIFFOUT
+ DROOP_P
− DROOP_N
Ton Timer
PWM_GO PWMTON<10:0>
CLK_800MHZ
Ton Timer
PWM_GO PWMTON<10:0>
CLK_800MHZ
Ton Timer
PWM_GO PWMTON<10:0>
CLK_800MHZ
DAC
CURRENT LIMIT
CSP
CSN
CURRENT LIMIT<>
OCP
PWM1
PWM2
PWM3
V1
1.3Vdc
0
5ns
RAMP COMPARATOR
RAMP
COMP
TRIGGER
Figure 2. Block Diagram
NCP81111
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4
PIN LIST DESCRIPTION
Pin No. Symbol Description
1 SDA Serial Data Configuration Port
2 SCL Serial Clock Configuration Port
3 EN Logic input. Logic high enables output.
4 TEST3/I2CCADR0 Debug and monitor port / I2C Programming Address Offset 0
5 VFF Input voltage monitor
6 VDIG Digital power filter pin. Internally regulated
7 VCCD 5V digital VCC
8 VCCA 5V analog VCC
9 VCCP 5V driver VCC
10 PWM1 Phase 1 PWM output.
11 SMOD1 Low side FET enable signal
12 DRON Gate driver enable
13 PWM2 Phase 2 PWM output
14 SMOD2 PWM 2 low side FET enable signal
15 PWM3 Phase 3 PWM output
16 SMOD3 PWM3 low side FET enable signal
17 CSN3 Inverting input to current balance sense amplifier for phase 2
18 CSP3 Non−Inverting input to current balance sense amplifier for phase 2
19 CSN2 Inverting input to current balance sense amplifier for phase 2
20 CSP2 Non−inverting input to current balance sense amplifier for phase 2
21 CSN1 Inverting input to current balance sense amplifier for phase 1
22 CSP1 Non−inverting input to current balance sense amplifier for phase 1
23 TEST2/ADDR1 Monitor port / I2C Programming Address Offset 1
24 TEST1 Debug and monitor port
25 VSP Non−inverting input to the core differential remote sense amplifier.
26 VSN Inverting input to the core differential remote sense amplifier.
27 T_SENSE Temp sense for the single phase converter
28 VR_HOT# Thermal logic output for over temperature.
29 VR_RDY Open drain output. High indicates that the core output is regulating.
30 SCLK Serial VID clock.
31 ALERT# Serial VID ALERT#.
32 SDIO Serial VID data interface.
FLAG GND Power supply return ( QFN Flag )
NCP81111
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5
Figure 3. Three Phase Application Control Circuit
R2 0.0
R161
1.0K
R162
130
C83
.015uF
U6
NCP81111
SCL
2
EN
3
VFF
5
VDIG
6
VCCD
7
VCCA
8
PWM1
10 VCCP
9
TEST3/I2CADDR0
4
SMOD3
16
CSN3 17
CSP3 18
CSP2 20
SDIO 32
ALERT# 31
SCLK 30
TEST1 24
TEST2/ADDR1 23
CSP1 22
CSN1 21
CSN2 19
PWM3
15
SMOD1
11
DRVON
12
VSP 25
VSN 26
VR_RDY 29
VR_HOT# 28
SDA
1
PWM2
13
T_SENSE 27
SMOD2
14
FLAG 33
C87
100pF
RT22
220K
R9
14.0K
R4 0.0
R155
130
R12
49.9
R24
10.0
R156
54.9
C92
DNP
J100
C80
.015uF
C84
0.01uF
C86
100pF
R40
1.0K C82
0.01uF
C85
.015uF
R3 0.0
C222
10uF
J94
C88
100pF
R45
1
J92
R22
10.0
C51
1000pF
C94
DNP
R10
14.0K
R157
75.0
R48 100
J131
2
C89
0.01uF R23
10.0
J99
J104
J131
USB−I2C_COMM_MODULE
GND
INPUT1
SCL
SCA
+5V
J29
R34 100
JP5
ETCH
1 2
J27
C93
DNP
R27
14.0K
V_1P05_VCCP
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
PWM3
PWM2
PWM1
VSS_SENSE
SMOD1
SCLK
SDIO
VDC
CSN1
VCCU
VCC_SENSE
VSN
VSP
CSP3
CSN3
CSP2
CSN2
CSP1
VR_HOT
SMOD3
SMOD2
ALERT
DRON
VR_RDY
ENABLE
V5_CONT
SDA
SCL
VR_RDY
ENABLE
VFF
ALERT_VR
SCLK
SDIO
SCL
SDA
R46
0k
Place Near J92 an J93
Place by phase 1 inductor
VSENSE
R47
0k
J95
J93
QFN 32, 5X5mm, 0P5
Figure 4. Three Phase Applications Power Stage Circuit
PWM2
GL2
PWM3
GL3
Place close
to DRMOS pins
NCP5338
U3
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND
16
PGND
17
PGND
18
PGND
19
PGND
20
VSWH 31
VSWH 32
VSWH 33
VSWH 34
VSWH 35
GL
36
CGND
37
DISB#
39
PWM
40
ZCD_EN#
1
VCIN
2
NC
3
BOOT 4
GH
6
PHASE 7
VIN 9
VIN 10
PGND
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
VSWH 29
VSWH 30
CGND
5CGND
41 VIN 42
VSWH 43
VIN 8
THWN 38
GH3
J134
R19
0.00
J119
C269
1uF
C52
4.7uF
R20
1.00
Place caps close to
DRMOS pins on top
Place close
to DRMOS pins
CSN3
SMOD3
SW3
VCCU
CSP3
JP21
ETCH
SW3 JP22
ETCH
R21
1.0
C147
470pF
L4
DNP
DRON
V5_DRMOS
L7 DNP
VDC
C277
1uF
C39
0.1uF
V5S
Place close
to DRMOS pins
C282
22uF
C283
22uF
C284
22uF
C285
22uF
NCP5338
U1
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND
16
PGND
17
PGND
18
PGND
19
PGND
20
VSWH 31
VSWH 32
VSWH 33
VSWH 34
VSWH 35
GL
36
CGND
37
DISB#
39
PWM
40
ZCD_EN#
1
VCIN
2
NC
3
BOOT 4
GH
6
PHASE 7
VIN 9
VIN 10
PGND
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
VSWH 29
VSWH 30
CGND
5CGND
41 VIN 42
VSWH 43
VIN 8
THWN 38
J132
GH2
R15
0.00
J117
C44
4.7uF
C267
1uF
R14
1.00
Place caps close to
DRMOS pins on top
Place close
to DRMOS pins
VDC
SMOD2
SW2 CSN2
VCCU
CSP2
SW2
R7
1.0
JP17
ETCH
C145
470pF
JP18
ETCH
L2
DNP
DRON
V5_DRMOS
PWM1
GL1
Place close
to DRMOS pins
J133
NCP5338
U2
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND
16
PGND
17
PGND
18
PGND
19
PGND
20
VSWH 31
VSWH 32
VSWH 33
VSWH 34
VSWH 35
GL
36
CGND
37
DISB#
39
PWM
40
ZCD_EN#
1
VCIN
2
NC
3
BOOT 4
GH
6
PHASE 7
VIN 9
VIN 10
PGND
21
PGND
22
PGND
23
PGND
24
PGND
25
PGND
26
PGND
27
PGND
28
VSWH 29
VSWH 30
CGND
5CGND
41 VIN 42
VSWH 43
VIN 8
THWN 38
GH1
R16
0.00
J118
L6 DNP
C50
4.7uF
C268
1uF
R18
1.00
Place caps close to
DRMOS pins on top
Place close
to DRMOS pins
SW1 CSN1
SMOD1
VCCU
CSP1
SW1
R8
1.0
JP19
ETCH
C146
470pF
JP20
ETCH
L3
DNP
DRON
V5_DRMOS
L5 DNP
VDC
VDC
C274
1uF
C272
1uF
C38
0.1uF
V5S
C37
0.1uF
C280
22uF
C281
22uF
V5S
NCP81111
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6
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol VMAX VMIN ISOURCE ISINK
VFF 30 V −0.3 V N/A N/A
VDIG 3.3 V
All Other Pins 6.5 V −0.3 V N/A N/A
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description Symbol Typ Unit
Thermal Characteristic, QFN Package (Note 1) RqJA 44 _C/W
Operating Junction Temperature Range (Note 2) TJ−10 to 125 _C
Operating Ambient Temperature Range −10 to 100 _C
Maximum Storage Temperature Range TSTG −40 to +150 _C
Moisture Sensitivity Level
QFN Package MSL 1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter Test Conditions Min Typ Max Unit
BIAS SUPPLY
VCC Quiescent Current EN = high 30 40 50 mA
EN = low 10 mA
PS3 40 mA
VCCA UVLO Threshold VCC rising 4.4 4.55 V
VCC falling 4.1 4.2 V
VCCA UVLO Hysteresis 200 mV
VDIG UVLO Threshold VDIG rising 1.65 1.8 V
VDIG falling 1.27 1.45 V
VDIG UVLO Hysteresis 200 mV
ENABLE INPUT
Enable High Input Leakage Current External 1k pull−up to 3.3 V 1.0 mA
Upper Threshold VUPPER 0.8 V
Lower Threshold VLOWER 0.4 V
Total Hysteresis VUPPER − VLOWER 100 mV
Enable Delay Time Measure time from Enable transitioning HI
to when DRON goes high, Vboot is not 0 V 1 ms
DIFFERENTIAL VOLTAGE SENSE
Input Bias Current −400 400 nA
VSP Input Voltage Range −0.3 3.0 V
VSN Input Voltage Range −0.3 0.3 V
NCP81111
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7
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter UnitMaxTypMinTest Conditions
DRVON
Output High Voltage Sourcing 500 mA3.5 V
Output Low Voltage Sinking 500 mA0.1 V
Rise/Fall Time CL (PCB) = 20 pF,
DVo = 10% to 90% 10 ns
Internal Pull Down Resistance EN = Low 70 kW
IOUT MONITOR
Analog Gain Accuracy −3% +3%
Analog Gain Range 16 1024
Analog Gain Step Size Binary
weigh
ted
Analog IOUT Offset Accuracy Gain = 64, CSx sum = 40 mV,
Digital Gain = 1 3 LSB
Digital Gain Step Size Digital gain is 2.8 format 0.4%
Digital Gain Range 0.004 4
ADC Voltage Range 0 2.56 V
ADC Total Unadjusted Error (TUE) Max % error of the ideal value −1 +1 %
ADC Differential Nonlinearity (DNL) Highest 8−bits 1 LSB
ADC Conversion Time 10 ms
ADC Conversion Rate Per Channel 33 kHz
INTERNAL RAMP
Ramp Slope Accuracy −5 5 %
Ramp Reset Voltage Step Size 8 mV
Maximum Ramp Reset Step 486 512 538 mV
Ramp Slope Maximum Single Phase Mode 4000 mV/ms
Ramp Slope Minimum Single Phase Mode 5.6 mV/ms
Ramp Slope Step Size Single Phase Mode Typical 5.3 5.6 5.88 mV/ms
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Set Point Accuracy Threshold is programmable −20 20 mV
Over Voltage Max Capability 3 V
Over Voltage Delay VSP(A) rising to PWMx low 400 ns
Under Voltage Threshold Below DAC−DROOP VSP(A) falling 415 450 475 mV
Under Voltage Hysteresis VSP(A) rising 100 mV
Under Voltage Delay 150 ns
DROOP
Gain Accuracy Guaranteed by Design −2 +2 %
Programmable Gain Range CSx sum to Diffout 0,0.3 16.5
Gain Step Size 1.2 %
Offset Accuracy CSx input referred from 1.0 V to 2.0 V −2.5 2.5 mV
Common Mode Rejection CSx input referred from 1.0 V to 2.0 V 60 80 db
OVERCURRENT PROTECTION
ILIM Threshold Accuracy Sum of CSx inputs −3.5 3.5 mV
NCP81111
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ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter UnitMaxTypMinTest Conditions
OVERCURRENT PROTECTION
Step Size 2 mV
Maximum Setting Sum of CSx inputs 126 mV
ILIM Delay 1000 ns
ZCD COMPARATOR
Offset Accuracy −1.5 1.5 mV
Offset Programmable Range Guaranteed by Design −6.2 6.2 mV
Offset Step Size Guaranteed by Design 0.2 mV
VR_HOT#
Output Low Resistance I_VRHOT = −10 mA 13 W
Output Leakage Current High Impedance State −1.0 1.0 mA
TSENSE
Temperature Accuracy (0°C and 125°C)
Using Murata thermistor
NCP18WM224J03RB (220 kW)
−4 4°C
Internal Resistance Hot Range 50°C to 125°C 9.8 11.5 13.2 kW
Internal Resistance Cold Range 0°C to 50°C 146 172.5 198 kW
Bias Current Hot Range 50°C to 125°C 49.3 58 66.7 mA
Bias Current Cold Range 0°C to 50°C 4.1 4.83 5.6 mA
6 BIT CURRENT SHARE ADC
Voltage Range −24 39 mV
Differential Nonlinearity (DNL) 2 LSB
Step Size 1 mV
Conversion Time 550 ns
Common Mode Range 0.5 2.5 V
VR_RDY (Power Good)
Output Low Saturation Voltage IVR_RDY(A) = 4 mA, 0.3 V
Rise Time External pull−up of 1 kW to 3.3 V, CTOT =
45 pF, DVo = 10% to 90% 100 ns
Fall Time External pull−up of 1 kW to 3.3V, CTOT =
45 pF, DVo = 90% to 10% 10 ns
Output Voltage at Power−up VR_RDY pulled up to 5 V via 2 kW1.0 V
Output Leakage Current when High VR_RDY = 5.0 V −1.0 1.0 mA
VR_RDY Delay (rising) DAC=TARGET to VR_RDY 5 6 ms
VR_RDY Delay (falling) UVP response time 5ms
VR_RDY Delay (falling) OCP response time 1000 ns
VR_RDY Delay (falling) OVP response time 250 ns
VR_RDY Delay (falling) SetVID 0 V if register 34h is set to respond 500 ns
VR_RDY Delay (falling) Time after Enable transitions low 1.3 1.5 ms
PWM
Output High Voltage No Load VCC V
Output Low Voltage No Load GND V
NCP81111
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9
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter UnitMaxTypMinTest Conditions
PWM
Rise and Fall Time CL (PCB) = 25 pF,
DVo = GND to VCC 1 ns
Ton Accuracy −5 5 %
Ton Step Size 1.25 ns
Ton Range 15 2559 ns
SMOD
Output High Voltage No Load VCC V
Output Low Voltage No Load GND V
Rise and Fall Time CL (PCB) = 25 pF,
DVo = GND to VCC 1 ns
VFF ADC / VFF UVLO
Note: UVLO threshold is programmable
Step Size 200 mV
Maximum Tracking Slew Rate 2.5 V/us
Maximum Input 25.5 V
General
The NCP81111 is a single output three phase digital controller designed to meet the Intel VR12.5 specifications with a serial
SVID control interface. The NCP81111 implements VR12.5 or VR12.6 depending on the device configuration.
NCP81111
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10
I2C USER COMMANDS
These commands operate on a subset range of address space and are primarily for use by end users during application
configuration.
USER_REG_READ
This command can read one or more bytes from the working register set. The address (USER_ADDR) specified with this
command is a working set address from the user address range (refer to the USER column in the Register Map). Only registers
which have read access (shown as (R) or (RW) in the USER column) can be read with this command. If the command is
specified with an address that does not have read access the device will respond with NA (not−acknowledge).
However, if a block of registers are read which start from a valid address, then via the auto−incrementing address point to
an address that does not have read access, then for those invalid registers the return value will be 00h (zeros). The invalid
registers do not stop the command, and the device will respond with an A (acknowledge). This allows a single
USER_REG_READ command to read a contiguous block of data even if it spans addresses that are not valid. Note that this
command requires a repeated START sequence to change the data direction. Also, for the final byte received by the master it
must signal end of data to the device by responding with a NA (not−acknowledge). This allows the device to release the data
line so the master can send the ST OP sequence. If a long sequence of data is read, which due to the auto−incrementing address
exceeds the allowable address range, then the device will return zero values (00h) for bytes beyond the address boundary.
For a single−byte read the sequence is as follows:
S I2C_ADDR+W A USER_REG_READ A USER_ADDR A Sr I2C_ADDR+R A D0 NA P
This will read the data from the working register map as shown:
Working Registers
Data Address
D0 USER_ADDR
For a multi−byte read command the sequence is as follows:
S I2C_ADDR+W A USER_REG_READ A USER_ADDR A Sr I2C_ADDR+R A D0 A
D1 A D2 A ... NA P
This will read the data from the working registers as shown:
Working Registers
Data Address
D0 USER_ADDR
D1 USER_ADDR+1
D2 USER_ADDR+2
... ...
USER_REG_WRITE
This command will write one or more bytes into the working register set. The address (USER_ADDR) specified with this
command is a working set address from the user address range (refer to the USER column in the Register Map). Only registers
which have write access (shown as (RW) in the USER column) can be written with this command. If the command is specified
with an address that does not have write access the device will respond with NA (not−acknowledge). However, if a block of
registers are written which start from a valid address, then via the auto−incrementing address point to an address that does not
have write access, then for those invalid registers the input data will be ignored. The invalid registers do not stop the command,
and the device will respond with an A (acknowledge). This allows a single USER_REG_WRITE command to write a
contiguous block of data even if it spans addresses that are not valid. If a long sequence of data is written which exceeds the
allowable address range then the command will automatically terminate when the end of the address range is reached.
Attempting to write past this point will result in NA (not−acknowledge) responses from the device.
NCP81111
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11
For a single−byte write the sequence is as follows:
S I2C_ADDR+W A USER_REG_WRITE A USER_ADDR A D0 A P
This will insert data into the register as shown:
Working Registers
Data Address
D0 USER_ADDR
For a multi−byte write command the sequence is as follows:
S I2C_ADDR+W A USER_REG_WRITE A USER_ADDR A D0 A D1 A D2 A ... A P
This will insert a block of data into the registers as shown:
Working Registers
Data Address
D0 USER_ADDR
D1 USER_ADDR+1
D2 USER_ADDR+2
... ...
USER_NVM_RELOAD
This command will reload the User NVM settings from the NVM into the working registers.
The sequence is as follows:
S I2C_ADDR+W A USER_NVM_RELOAD A P
The command will reload all the registers at once and should complete in less than 50 ms (worst case). This can be used to
restore User settings after altering the working registers via the I2C interface. The reload is forced and does not require the
settings to be configured.
USER_NVM_WRITE
This is the primary method for writing the User NVM settings into the NVM.
The sequence is as follows:
S I2C_ADDR+W A USER_NVM_WRITE A P
The command will write all the current User settings from the working registers into the NVM. It should complete in less
than 988 ms (worst case, 380 ms typical case).
I2C USER_POWER CONTROL
Due to the internal construction of the device, when the EN pin goes low the internal regulators will turn off and the device
will lose its working state. Subsequently if the EN pin goes high the device will reinitialize its state from the NVM
configuration. For purposes of test and application configuration it is useful to power cycle the device without necessarily
losing state. In addition, preserving state allows the device to optionally skip NVM load and/or auto−calibration sequences
resulting in a faster startup time. To accomplish this, the USER_POWER command was added which allows the user to
Enable/Disable the device without power−cycling the part. It also allows the NVM, working registers, and auto−calibration
behavior to be modified when exiting the DISABLED state. The key to this command is the concept of a “Virtual Enable”
signal. This virtual−EN signal can be controlled via the USER_POWER command and will behave in a similar way to the actual
EN−pin, however when the virtual−EN is set low it will not completely power of f the device. The internal regulators and clocks
will continue running in order to preserve device state. Note, the EN−pin must remain high at all times when using the device
in this way.
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The command sequence is as follows:
S I2C_ADDR+W A USER_POWER A POWER_SETTING A P
Where the POWER_SETTING byte is mapped as follows:
POWER_SETTING:
0 0 0 RESET_TEST RESET_MEM RESET_AUTOCAL RESTART ENABLE
−ENABLE − This bit is the “Virtual Enable” signal. When the device is in the DISABLED state, sending the
USER_POWER command with this bit set to “1” will cause the device to exit the DISABLED state and begin the
power−up sequence. The exact power−up sequence followed will depend on the other bit settings. If the device is in an
operational state (not DISABLED) and the command is issued with this bit set to “0” then the device will stop operation
and enter the DISABLED state.
−RESTART − This bit is used in conjunction with the ENABLE bit. It is used to immediately restart the device when the
DISABLED state has been entered. So when the device is in an operational state, if the USER_POWER command is
issued with this bit set to “1” and the ENABLE bit set to “0”, the device will stop operation, enter the DISABLED state,
and then immediately power−up again. It is in essence a fast toggle on the Virtual Enable signal, used to quickly cycle
the device through its power−up sequence.
−RESET_AUTOCAL − When this bit is set to “1”, upon exiting the DISABLED state, the device will reset its
auto−calibration state and proceed to recalibrate during power−up. Normally auto−calibration is only required if the
device has lost its state (thus it will occur anytime the actual EN−pin is toggled), however the procedure takes a few
milliseconds to complete. Since the device can retain state using this command, if this bit is set to “0”, the
auto−calibration settings will be retained and the procedure will be skipped. A “0” setting will allow the device to
power−up several milliseconds faster than normal.
−RESET_MEM − This bit controls the behavior of the working registers and the NVM during power−up. If the bit is set
to “1” then upon exiting the DISABLED state the working registers will be reinitialized − first the POR settings will be
applied, then the NVM will be read and those settings will be applied. Any changes to the working registers that were
not programmed to the NVM will be lost. If the bit is instead set to “0” then the device will retain all the settings that are
currently in the working registers. A “0” setting is useful for testing minor changes to device settings without needing to
program them to NVM.
−RESET_TEST − If the bit is set to “1” then upon exiting the DISABLED state, the test registers will be reset to their
POR defaults. A “1” setting is useful for quickly clearing all test modes when cycling through a power−up sequence. If
the bit is set to “0” then the test registers will be unaffected by the power−up sequence.
Example command sequences:
Starting from a normal operational state, issuing the following command:
S I2C_ADDR+W A USER_POWER A 00000000b A P
W ill cause the part to exit to the DISABLED state and remain there. The test interface can then be used to modify the working
registers and adjust settings prior to re−enabling the part.
Starting from the DISABLED state, issuing the following command:
S I2C_ADDR+W A USER_POWER A 00000001b A P
Will cause the part to exit the DISABLED state and begin power−up. The working registers will not be affected during
power−up, and auto−calibration will be skipped (Note: this is only true if auto−cal has completed its sequence at least once.
Starting from any state, issuing the following command:
S I2C_ADDR+W A USER_POWER A 00000110b A P
Will cause the part to exit to the DISABLED state, then immediately begin power−up. The working registers will not be affected
during power−up, however the part will recalibrate.
Starting from any state, issuing the following command:
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S I2C_ADDR+W A USER_POWER A 00011010b A P
Will cause the part to exit to the DISABLED state, then immediately power−up again. On power−up it will clear the test
registers and reload the NVM into the working registers. It will skip the auto−calibration sequence. This is very similar to
toggling the EN−pin, but with a faster powerup time.
Starting from any state, issuing the following command:
S I2C_ADDR+W A USER_POWER A 00011110b A P
Will cause the part to exit to the DISABLED state, then immediately power−up again. On power−up the controller will clear
the test registers and reload the NVM into the working registers. It will recalibrate during power−up. This is exactly the same
as toggling the EN−pin, but with a slightly faster power−up time (due to regulators and clocks already being powered up and
running).
DEVICE CONFIGURATION
The following sections describe the configuration of certain device register groups based on function.
External Address Offset
There is a n external address of fset circuit which can be used to allow otherwise identically programmed devices to be placed
on a common bus. The address that the devices will respond to can be altered via an external resistor network. The address offset
circuit can offset both the I2C and SVID addresses by an offset range of +0 to +15. The address system is controlled by the
following registers:
Table 1. I2C / SVID ADDRESS REGISTERS
Register
(I2C Addr) R/W Purpose Description
43 Bits<2:0> RW Address Offset
Configuration
This register has bit flags as follows:
0 0 0 0 0 apply_svid_
addr_offset apply_i2c_
addr_offset en_addr_offset
These bit flags control whether the External Address Offset function is enabled, and if
so how the offset is applied.
apply_svid_addr_offset = When set the address offset will be applied to the SVID
Address (Default enabled)
apply_i2c_addr_offset = When set, the address offset will be applied to the I2C
Address (Default enabled)
en_addr_offset = Controls if the address offset circuit is enabled (Default enabled)
50 Bits<6:0> RW I2C Address
This settings holds the base I2C address. The value should be between 8 to 119.
Default is 68 (44h).
0−7 = Invalid (I2C reserved)
8−119 = Valid (08h − 77h)
120−127 = Invalid (I2C reserved)
51 Bits<3:0> RW SVID Address This setting holds the base SVID address. The value can be between 0 to 15 (0h −
Fh). Default is 0 (0h).
The address offset circuit is enabled by default on an unprogrammed device. It can be disabled by writing a zero into
en_addr_offset (Register 43, Bit 0) when programming the device. When enabled, the device will sense resistors attached t o
the TEST2 and TEST3 pins during powerup and will add the resulting offset to the SVID and I2C base addresses as defined
by the bit flag settings above.
Addresses that exceed the maximum address will wrap around. For instance:
The address offset that is generated is determined by the resistors placed between the TEST2/TEST3 pins and GND. The
system uses 20 kW increments per step, and both the highest and lowest settings will give an address of fset of zero (this is to
allow the TEST pins to be either shorted or open on a single−VR application or during device evaluation).
The following tables list the resultant offsets versus resistance for the TEST2 and TEST3 pins. The individual offsets are
added to give a total offset.
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Table 2. TEST2 ADDRESS OFFSET
Address Offset Resistance (kW)
00−60
+8 80−140
0 >160
Table 3. TEST3 ADDRESS OFFSET
Address Offset Resistance (kW)
0 0
+1 20
+2 40
+3 60
+4 80
+5 100
+6 120
+7 140
0 >160
The address offset value is latched during power−up as part of NVM initialization. It will be retained for the duration of
device operation. Enabling/Disabling the device via USER_POWER commands will not cause the address offset value to be
relatched. The only way to relatch the address offset value is to either power cycle the device or use a USER_POWER command
with the RESET_MEM flag set. After power−up the resulting address offset value can be read via I2C (Note: if I2C address
offset is enabled, this requires knowing the offset in advance, if this is not the case, then the hardwired addressing mode can
be used):
Table 4. ADDRESS OFFSET READBACK
Register
(I2C Addr) R/W Purpose Description
219 Bits<3:0> RAddress Offset Readback of the latched address offset
DAC FEED FORWARD
A DAC Feed Forward (abbreviated DACFF) function has been added to the device. The purpose of this circuit is to
counteract the transient response of the output pole given by the droop resistance and the output load capacitance. In order to
do this the DACFF circuit adds a counteracting zero which cancels the pole.
This is illustrated below, where ωz = ω = 1/RC, with R = droop resistance and C = output load capacitance:
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DAC
DACFF
VSP
C
R
w
mag(dB)
0
w
mag(dB)
0
w
mag(dB)
0
DACFF(s) +s
wz
G(s) +1)s
wzH(s) +1
1)s
w
VSP
DAC +ǒ1)s
wzǓǒ1
1)s
wǓ+1
wz+1ńRC wz+1ńRC
Figure 5.
There are some important things to note about the DACFF system:
•This effect is only applied in the VID UP direction, and allows the DAC to closely follow the ideal ramp slope
behavior. The effect is not applied in the VID DOWN direction to prevent potential voltage undershoot.
•For the effect to work properly the internal DACFF coefficients (given below) must be set properly with respect to the
actual droop resistance and output load capacitance. Improperly setting the coefficients may yield a lagging voltage
response (under−compensated) or overshoot artifacts (over−compensated). For this reason the feature is disabled by
default and must be explicitly enabled via end−user configuration.
•The above representation is a theoretical idealized model. In practice due to the digital nature and internal clock
frequency of the VID controller an additional high−frequency pole is introduced. The actual transfer function of the
DACFF circuit is given below. From a transient perspective this pole will have an effect on the leading and trailing
response of the DACFF function (the transition from VID up to VID stable, or vice−versa), and it’s effect will be
discussed more in the coefficient calculation section below.
DACFF(s) +
s
wz
1)s
wp
(eq. 1)
There are two DACFF coefficients, a 16−bit A−coefficient and an 8−bit B−coefficient. They can be calculated with the
following equations and procedure.
A[15 : 0] +
2
T@wz
ǒ1)2
T@wpǓ@128 B[7 : 0] +ǒ2
T@wp*1Ǔ
ǒ1)2
T@wpǓ@256 (eq. 2)
where:
wz+1
RC
wp+2p@fpwhere fpt3.18 MHz
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T = 100 ns = 1 • 10−7
R = droop resistance
C = output load capacitance
Calculation procedure:
1. Calculate ωz and choose initial ωp. Use those parameters to calculate A/B−coefficients.
2. Program the device with the coefficients, and enable the DACFF function. Observe the transient behavior.
3. Adjust A/B−coefficients directly as needed to modify the transient behavior as shown below.
4. Program the new coefficients and iterate as needed until satisfactory transients are obtained.
To the first−order the magnitude of the DACFF function will be controlled by the A−coefficient and the frequency response
will be controlled by the B−coef ficient. This is illustrated below and can be used as a guideline when adjusting the coefficients
to obtain the desired response.
VSP (DACFF disabled)
DAC
VSP (DACFF enabled)
A−coeff controls
magnitude
DAC
B−coeff controls speed
of trailing−edge
transient roll−off
Figure 6.
IOUT Gain Programming
The NCP8111 1 has a high accuracy 10 bit A/D to monitor the total output current. The IOUT gain and the ICCMAX register
are user programmed and stored in the nonvolatile memory. The IOUT gain consists of two analog gain stages and one digital
gain stage for fine gain adjustment. When setting the IOUT gain the user must be care not to exceed the maximum input A/D
signal capability using the analog gain. Set the digital gain to unity and then adjust the analog gain to get the maximum signal
into the A/D without exceeding FFh at ICCMAX load in the IOUT register. Then fine tune the digital gain to achieve FFh in
the IOUT register under the ICCMAX load condition. IOUT Offset can be adjusted after the A/D conversion via register 84d.
Av=16
IMON SUMMING AMP
+ CSP1
+ CSP2
+ CSP3
− CSN1
− CSN2
− CSN3
CSP
CSN
Av
IOUT 2nd Gain Stage
CSP
CSN
IOUT_P
IOUT_N
Gain<>
Av
IOUT 3d Gain Stage
CSP
CSN
IOUT_P
IOUT_N
Gain<>
10BIT A/D
IN_P
IN_N
OUT<9:0>
81d<1:0> 81d<2:3>
84d<7:0>
IOUT<7:0>
82d<7:0>
SUM Av
700Hz
Digital Adjust
GAIN<7:0>
OUT<7:0>
OFFSET<7:0>
IOUT<9:0>
Figure 7. IOUT Signal Chain
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IOUT CONFIGURATION TABLE
Function Register Value
Stage2 IOUT Gain
Stage3 IOUT Gain 81d<1:0>
81d<3:2> 0: 1
1: 2
2: 4
3: 8
Digital Gain 82d<7:0> absolute 2.8 format (2 integer, 8 fractional), 0.00390625 per step
Example 100h = 256d ≥ Gain = 1
Iout Offset PS0 84d<7:0> 2’s complement format
Imon Offset PS1 115d<7:0> 2’s complement format
Imon Offset PS23 116d<7:0> 2’s complement format
Imon Settling time 110d<1:0> 99% Settle in => 00b=840 ms, 01b=1.68 ms, 10b=3.36 ms, 11b:6.72 ms
The equation for Iout tuning is as follows.
2.5 V +G1@G2@DCR @0.75 @GDigital @ICC_MAX (eq. 3)
When tuning the Iout Analog gain G1 and G1 need to be set such that the Iout is between 80h and FFh but the voltage at the
A/D should not exceed 2.5V at Icc_max or the Iout signal will saturate the A/D converter. The offset can also be adjusted.
A/D Range
FFh
80h
ICC_MAX
Analog Gain Target
Window
Digital Gain =1
Offset=0
Figure 8.
The internal offset of the Iout signal chain is auto−calibrated and has very low offset. The current sense RC filter itself has
some nonlinear behavior when using thick film resistors. This creates a positive offset on Iout that can be observed to follow
the input supply voltage, Vout, and phase count. Using physically larger thick film 0805 resistors or two 0603 resistors in series
can reduce but not eliminate this effect. The system provides the IOUT of fset adjust registers to help compensate for this ef fect.
For best performance using a metal film resistor is required in the cs filter network.
OCP Current Limit Programming
The NCP81111 uses a latching total current limit function. If the current limit is exceeded the controller will tri−state the
output stage. There is an adjustable filter speed for the OCP function. The filter can be disabled for the fastest response. The
OCP has three user settings to accommodate different current limits in separate power states.
The current limit is a total current limit and is digitally programmable in 2 mV steps to a maximum of 126 mV referred to
the total CS input sum.
Table 5. OCP CONFIGURATION TABLE
Function Register Value
OCP PS0 85d<5:0> 2 mV per step 0d = 0 mV to 63d = 126 mV
OCP PS1 86d<5:0> 2 mV per step 0d = 0 mV to 63d = 126 mV
OCP PS23 87d<5:0> 2 mV per step 0d = 0 mV to 63d = 126 mV
OCP Filter Bandwidth 85d<7:6> 00b:250 kHz , 01b:125 kHz, 10b:75 kHz, 11b:50 kHz
OCP Filter Enable 86d<6> 0:Use Filter, 1:No Filter
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Compensator Tuning
The NCP81111 uses a hybrid compensator. The high frequency performance is provided by a 100 MHz BW op−amp. The
digital integrator allows better control of the low frequency transient response. R1 and can be adjusted for power states PS0
and PS1,2,3 to optimize the loop gain based on the number of phases running.
Figure 9. Hybrid Compensator Diagram
+
−
Digital
Integrator
Sum
VSP
VSN
DAC
GND
1.3V
1.3V
Diffout
1.3V
C1 R3
C2
R1
Droop_p
Droop_n
50k 50k
Comp
Equation 4 − Compensator Transfer Function
Comp(s)
Diffout(s) +
−ǒAi@gm
2@Ccap@Divisor@Vramp@s)1
R3)1
C3@s
)1
100kǓ
1
R1 )C2 @s
(eq. 4)
ANALOG COMPENSATION CONFIGURATION TABLE
Function Register Value
R1 (PS0)
R1 (PS123) 95d<3:0>
95d<7:4> 0:33k, 1:50k, 2:75k, 3:100k, 4:150k, 5:200k, 6:250k, 7:300k, 8:350k, 9:400k, 10:450k
R3 96d<5:3> 0:10k, 1:20k, 2:30k, 3:40k, 4−7:50k
C1 96d<2:0> 0:0pF, 1:1.23pF, 2:3.48pF, 3:8.02pF, 4:17.12pF, 5:35.8pF, 6−7:24.3pF
C2 97d<2:0> 0:0fF, 1:185fF, 2:90fF,3:522fF,4−7:1.373pF
Digital Integrator
The digital integrator allows for independent tuning of the load step and load release response time and allows the user to
change the offset during power state changes to smooth the transition of the power state changes. The current DAC step size
controls the working range/ resolution of the digital integrator.
gm
OSC Up
Down
Divisor
Divisor
Counter
+
offset
Current
DAC
Step Size
1.3V
Diffout
Power state
step size
Figure 10.
The digital integrator is a voltage to current function. The gm is approximately 180 ms, Vramp is ~50 mVm and Ccap in the
oscillator is 2 pF. The step size Ai for the current DAC is user adjustable. The digital integrator transfer function can be
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approximated with the following equation below. The current gain Ai is the integrator current step multiplied by the size
multiplier.
I(s)
Verror(s) +Ai @gm
Divisor @Vramp @Ccap @s(eq. 5)
The digital integrator also includes a stop function that can be adjusted to improve some aspects of the dynamic response
such as load release. If the output of the error amplifier falls below the integrator stop threshold the digital integrator counter
will be stopped to limit the integrator windup effect. In some cases the range of the integrator is sufficient to stop the windup
effect.
Figure 11. Example Compensator Gain Transfer Function with Mismatched Increment and Decrement Gains
DIGITAL INTEGRATOR CONFIGURATION TABLE
Function Register Value
Integrator Step Size Multiplier
Integrator Current Step 88d:<7>
89d:<4:3> 0: 100% step size 1: 75% step size
0: 5nA, 1:10nA, 2:15nA, 3:20nA
Integrator Decrement Divisor
PS0
PS1
PS23
90d<5:3>
91d<5:3>
92d<5:3>
0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128
Integrator Increment Divisor
PS0
PS1
PS23
90d<2:0>
91d<2:0>
92d<2:0>
0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128
Integrator Offset PS1 Step 93d<7:0> 2’s compliment format
Integrator Offset PS23 Step 94d<7:0> 2’s compliment format
Integrator Stop Threshold
PS0
PS1
PS23
88d<0:2>
88d<5:3>
89d<2:0>
0:0.90V, 1:0.95V, 2:1.00V, 3:1.05V, 4:1.10V, 5:1.15V, 6:1.20V, 7:1.25V
Phase Shedding Threshold
When a power state command alters the phase count the controller will automatically reduce the current in the phases that
are to be shed to the threshold level set by the user and then shutdown the phase. This allows the controller to minimize the
voltage deviation during phase shedding operation.
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PHASE SHED THRESHOLD CONFIGURATION TABLE
Function Register Value
Phase Shed Threshold 73d<5:0> LSB = 1 mV 2’s complement format
VBOOT Voltage Programming
The NCP8111 1 has a Vboot voltage register that can be configured to any valid VID value. If Vboot is configured to zero,
the controller will wait for an initial SVID voltage command to begin soft start.
DAC Offset Voltage Programming
The NCP81111 has a user fine trim for the output voltage that is adjustable for each power state.
ZDC Offset Programming
The NCP81111 is optimized to work with the ON’s HFVR high performance DRMOS drive stage. The ZCD detector is
located in the controller and the o ffset is adjustable for optimization by the user. This allows for timing variations in the design
ZCD OFFSET CONFIGURATION TABLE
Function Register Value
ZDC Offset Trim 114d<5:0> 0.2 mV per LSB Sign magnitude format.
VFF Under-Voltage Protection Programming
The controller is protected against under−voltage on the VFF input pin. The threshold is user programmable.
VFF Under−Voltage Configuration Table
Function Register Value
VFF UVLO Threshold 93d<6:0> 200 mV per LSB Example 14h = 4.0 V
Programming the Phase Count
The phase count must be configured buy the user and stored in NVM before enabling the output.
PHASE COUNT CONFIGURATION TABLE
Function Register Value
VR Phase Count 64d<7:6> 1: 1phase
2: 2phase
3: 3phase
Programming the Minimum ON, Minimum OFF, and SMOD Skew Timing
The controller is designed to guarantee the timing in certain cases to protect the gate driver from very rapid signal changes
that could potentially result is shoot though of the power stage. The user may select the setting for this based on the application
selection of the power stage. The recommended values for the HFVR DRMOS are noted in the table.
MINIMUM ON AND OFF TIME AND SMOD SKEW CONFIGURATION TABLE
Function Register Value
Minimum On Time Phases 1 65d<5:0> Minimum On time 1.25 ns per LSB Example 1Ah = 32.5 ns
Minimum On Time Phases 2 and 3 64d<5:0> Minimum On time 1.25 ns per LSB Example 1Ah = 32.5 ns
Minimum Off Time 66d<4:0> LSB = 2.5 ns Example 0Dh = 32.5 ns
SMOD Skew Time 69d<4:0> LSB = 2.5 ns Example 06h = 15 ns
Programming the Period of Operation
The NCP81111 is designed to maintain a constant frequency in as many operating cases as possible. The On time of the
controller varies based on many factors including VID setting, input voltage feed forward, load and power state. The frequency
in continuous mode operations is controlled by the user period setting. Under some conditions including low VID and high
Vin the frequency of operation may reduce due to reaching the minimum on time limits. The period setting is based on the
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individual phase frequency desired. Example 134h = 770 ns for 1.3 MHz For this case the registers would be configured as
follows. 72d = 34h with 73d<3:0> = 001b.
PERIOD CONFIGURATION TABLE
Function Register Value
USER Period low byte 71d<7:0> 2.5 ns per LSB
USER Period high byte 72d<3:0>
Programming the Boost Cap Functions
Due to the high voltage operation of the output under some conditions the gate driver floating boost cap voltage may
discharge to unacceptable levels, this is especially likely to occur when using 5 V gate drivers. The NCP81111 has several
functions to maintain the charge on the boost capacitors such that the gate driver is ready to use when needed. These timers
are user adjustable for custom optimization. The Tboost Period sets the time between recharge events for the phases that are
shed. The Tboost T ime sets the amount of time the switch node is pulled low to charge the boost cap. The Boost Loop Count
is used at soft−start and sets the number of times the boost cap is charged before soft−start occurs.
BOOST CAP CONFIGURATION TABLE
Function Register Value
Tboost Period 67<7:4> Default 1h = 81.92 ms
Tboost Time 68d<7:0> 2.5 ns per LSB Default 33h = 127.5 ns
Boost Loop Count 70d<3:0> Default 8h for 8 loops.
Programming the Ramp Function
The ramp signal is user adjustable. This allows the user to maximize the performance of the controller. The ramp provides
a synchronization functio n f or th e c ontrolle r a nd s tabilizes t h e l oop g ain as w ell as t he p hase a ngles . T he r am p h a s a reset vo ltage
for each phase and the slope automatically adjusts for the phase count during phase shedding. To achieve a wide verity of
accurate settings both the current and the ramp capacitor are adjustable. The adjustable ramp reset voltage allow for fine tuning
of the phase angles if the ripple feedback is not well balanced. The ramp descends to 1.3 V and remains there until reset again.
Use the equation I = Cdv/dt the ramp current setting is based on single phase ramp operation. Figure x shows how to select
the ramp cap and ramp slope. The design should target the trigger point near 1.31 V just above were the ramp goes flat at 1.3 V.
If the ramp intersects comp at high levels the load release response will be less aggressive and transitions into and out of DCM
mode operation will be less smooth. If the ramp is too steep the comp will trigger on a flat ramp and the system will be less
stable.
Figure 12.
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Figure 13. Multiphase Ramp Function
Modulator Gain Analysis
The NCP81111 modulator has an inherent non−linear transient response that varies depending on the ramp settings. The
small signal modulator gain can be found by taking the derivative of the non linear curve at the operating point. The result is
the equation for Am.
Am:+Mc @Ton
N@ǒVreset *compopp )Mc @TresetǓ2compopp :+
Mc@Ton
D*N@Vreset *N@Mc @Treset
−N (eq. 6)
0 0.05 0.1 0.15 0.2
0
0.2
0.4
0.6
0.8
Dcomp()
Amcomp compopp
*
()
@Dcomp
opp
()
+
comp
Figure 14. Modulator Gain Function
RAMP CONFIGURATION TABLE
Function Register Value
Ramp Cap Setting 77d<3:0> 0: 0 pF
1: 1 pF
2: 2 pF
3: 3 pF
4: 4 pF
5: 5 pF
6: 6 pF
7: 7 pF
8: 8 pF
9: 9 pF
10: 10 pF
11: 11 pF
12-15: 12 pF
Ramp Current Setting 78d<7:0> 0 to 4.2291 uA 33.3 nA per LSB
Phase 1 Reset Voltage 74d<7:0> 4 mV per LSB Example 3Fh = 63d = 1.556 V
Phase 2 Reset Voltage 75d<7:0> 4 mV per LSB
NCP81111
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24
Control Loop Analysis
The NCP8111 control loop diagram can be modeled as shown below. The NCP81111 system is best described as voltage
mode control with AVP. AVP does create a current feedback loop but the compensation signal does not directly control the
current.
Figure 15. NCP81111 Control Loop
Figure 16. Current Loop Closed
Using the Test Ports for Debug
This controller has dedicated test ports for monitoring internal signals for debug purposes. Some of the more useful settings
include a cces s t o t h e i nternal droop, IOUT, and comp signals. The test pins have some impedance. For proper monitoring please
use 1 MQ or higher impedance probes.
Analog Application Notes Section
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense that phase current for current balance. Resistor RCSN must be
14 kW to work correctly with the internal thermal compensation. It is also recommended that the voltage sense element be no
less than 0.5 mW for accurate current monitor and balance. The internal CS pin resistance forms a divider with the external
CS filter resistor . Only 14 kW may be used for the external resistor. Fine tuning of the CS filter must be done by adjusting the
capacitor values. Two parallel capacitors should be placed on each phase to allow for fine tuning of the time constant of the
CS filter. The effective R in the RC time constant c alc ula tion will always be 10 kW. Select the C based on the L/(DCR * 10k)
= CCSN. The internal thermal compensation resistor attenuates the signal from the inductor DCR. The thermal gain is
approximately 0.75 at 25C for the inductor current sensing inputs. When calculating the droop gain the thermal gain ef fect must
be included. For best droop and IMON offset performance RCSN should be of the metal film type resistor. Using a lar ger thick
film 14 kW 0805 case size or two thick film 0603 case size resistors in series can offer improved current sense offset
performance over a standard 0603 case size.
Equation 7 − Initial Estimate Equation for Ccs Total
L
DCR @10k +Ccs_total (eq. 7)
NCP81111
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25
DRMOS SWN
CSP
CSN
Rcs =14k
Ccs 1
Vout
Rinternal Ccs 2
Rhf =10
Chf =100 pF
DCRL
Figure 17. Phase Current Sense Network
TSENSE
One temperature sense input is provided which monitors both VR_HOT and Inductor temperature for thermal compensation.
A precision current is sourced out the output of the TSENSE pin to generate a voltage on the temperature sense network. There
are two internal networks that c onnect to t he NTC depending o n the measured t emperature to extend t he accuracy o f the
thermal m easurement across a g reater temperature range. The h ot and c old range l imits are c ontrolled by the i nternal user
registers. The voltage on the temperature sense input is sampled by the internal A/D converter and then digitally converted
to temperature and stored in SVID register. A 220k NTC similar to the Murata NCP18WM224J03RB should be used.
Tsense
Internal IC
A/D
11.5k172.5k
58uA4.83uA
HotCold
220k
NTC
Place by
phase 1
inductor
Board
3x
Figure 18. Thermal Sense Diagram
Equation 8 − Tsense Voltage Calculation
VADC +3@Ibias @ǒRNTC @RinternalǓ
ǒRNTC )RinternalǓ(eq. 8)
NCP81111
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26
A/D Result
Bias
Current
temp_adc_hot
temp_adc_cold
58uA
4.38uA
Figure 19. Thermal Bias Current Selection Function
The onboard A/D converter has 10 bits and the maximum DAC voltage is 2.56 V with 2.5 mV per step. The user enters two
constants 1/M and C for both the thermal ranges this adjusts the temperature calculation reported for the temperature registers
and for VR_HOT activation. C has an offset ef fect and M adjusts a slope ef fect. This allows the user to adjust the thermal gain.
The conversion equation form the ADC result to the reported temperature is shown below.
Equation 9 − A/D Temperature Conversion Equation
Temperature +C*ResultADC
M+C*3@VTsense
M(eq. 9)
Figure 20. Example Results of the Thermal Sense Circuit
TSENSE CONFIGURATION TABLE
Function Register Notes
temp_adc_cold_low 100d<7:0> Default value = DEh = 222d => 57C
temp_adc_cold_high 101d<1:0> Default value = 0h
temp_adc_hot_low 105d<7:0> Default value = A2h
temp_adc_hot_high 106d<1:0> Default value = 2h 2A2h = 674 => 54C
temp_inv_m_cold 102d<7:0> 1/M used for the cold range temperature calculation. Default value = 18h = 24d
temp_inv_m_hot 107d<1:0> 1/M used for the hot range temperature calculation. Default value = 28h = 40d
Temp_c_cold_low 103d<7:0> Default value = 3Ch
Temp_c_cold_high 104d<1:0> Default value = 03h note 33Ch = 828d
Temp_c_hot_low 108d<7:0> Default value = FDh
Temp_c_hot_high 109d<1:0> Default value= 03h note 3Fdh = 1021d
NCP81111
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27
VR_HOT Operation
The VR_HOT thresholds are controlled by the user setting for the Temp Max register. Calculate the voltage thresholds on
the Tsense pin using the user settings for C and 1/M . See the equations below.
Tsense_VR_HOT_Assert_Threshold +ǒCHOT *MHOT @Temp_MaxǓ@2.56 V
10243 (eq. 10)
Tsense_VR_HOT_Deassert_Threshold +ƪCHOT *MHOT @(Temp_ThermAlert)ƫ@2.56 V
10243 (eq. 11)
TEMP_MAX CONFIGURATION TABLE
Function Register Notes
vr_temp_max 18d<7:0> 1degC per LSB
INPUT UNDER-VOLTAGE PROTECTION
Under Voltage Protection
Under voltage protection will shut off the output similar to OCP to protect against short circuits. The threshold is specified
in the parametric spec tables and is not adjustable. The controller is protected against under−voltage on the VCC and VFF pins.
Function Register Notes
disable_vff_uvlo 52d<2> 0:VFF UVLO Enabled 1: VFF UVLO Disabled
Vff_threshold 98d<6:0> LSB = 200 mV Default = 0
Assigning Unused PWM and CS Pins
When using lower phase count arrangements always connect unused CSN and CSP pins together and to the nearest CSN
signal. Unused PWM pins should be left floating.
Phase Count PWM1 PWM2 PWM3 CSP1 CSN1 CSP2 CSN2 CSP3 CSN3
3 Used Used Used Used Used Used Used Used Used
2 Used Used No Connect Used Used Used Used Connect to
CSN2 Connect to
CSN2
1 Used No Connect No Connect Used Used Connect to
CSN1 Connect to
CSN1 Connect to
CSN1 Connect to
CSN1
Layout Notes
The NCP81111 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues
related t o l a you t fo r e as y de si gn us e. To insure proper function there are some general rules to follow. Always place the inductor
current sense RC filters as close to the CSN and CSP pins on the controller as possible. Place the VCC decoupling caps as close
as possible to the controller VCC pin.
NCP81111
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28
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485CE
ISSUE O
ÉÉÉ
ÉÉÉ
ÉÉÉ
SEATING
NOTE 4
K
0.15 C
(A3)
A
A1
D2
b
1
17
32
E2
32X
8
24 L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.15 C
PIN ONE
REFERENCE
0.10 C
0.08 C
C
25
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 −−− 0.05
A3 0.20 REF
b0.20 0.30
D5.00 BSC
D2 3.40 3.60
E5.00 BSC
E2
e0.50 BSC
L0.30 0.50
3.40 3.60
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.70
0.30
3.70
32X
0.62
32X
5.30
5.30
NOTE 3
DIMENSIONS: MILLIMETERS
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
ÉÉ
ÇÇ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DET AIL A
e/2 A-B
M
0.10 BC
M
0.05 C
K0.20 −−−
L1 −−− 0.15
PITCH
RECOMMENDED
NCP81111/D
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