FUJITSU SEMICONDUCTOR DATA SHEET DS04-29146-4E ASSP Spread Spectrum Clock Generator MB88R157A DESCRIPTION MB88R157A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. This product has a built-in non-volatile memory, so its frequency setting can memorize each system or application. Also the product has a built-in oscillation stabilization circuit, so it is not necessary to use the external oscillation stabilization capacitance. FEATURES * Input frequency * Output frequency : 10 MHz to 50 MHz : 1 MHz to 134 MHz Programmable of the parameter of N divider, M divider, K divider (N divider : 11-bit, M divider : 12-bit, K divider : 7-bit) : no modulation, 0.125%, 0.25%, 0.5%, 0.75%, 1.0%, 1.25%, 1.5%, 1.75% * Modulation rate * Variable function pin It is possible to switch the VF pin function by setting to a non-volatile memory. Modulation enabled: It is possible to turn on/off the modulation operation. Power down control Output setting selection: It is possible to save two types of frequency setting into a non-volatile memory, and to select the type to operate. * Equipped with a crystal oscillation circuit * Built-in oscillation stabilization capacitance : 5 pF to 10 pF (0.039 pF step range) * Clock output Duty : 40% to 60% (Load capacitance 15 pF or less) * Clock Cycle-Cycle Jitter : Less than 100 ps (Output clock is over 3 MHz) * Low power consumption by CMOS process 5 mA (24 MHz, Typ-sample, no load) [Target value] (Input frequency : 24 MHz, N divider parameter : 200, M divider parameter : 200, K divider parameter : 1) * At power down: 5 A (Power supply voltage = 3.3 V, at room temperature) [Target value] * Non-volatile memory : FRAM (data retention : 10 years ( + 85 C)) * Power supply voltage : 2.7 V to 3.6 V * Operating temperature -20 C to + 85 C * Package : 8-pin plastic TSSOP Copyright(c)2010-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.9 MB88R157A PIN ASSIGNMENT TOP VIEW XOUT 1 8 XIN OE 2 7 VDD SP 3 6 VF VSS 4 5 OUT (FPT-8P-M07) PIN DESCRIPTION 2 Pin name I/O Pin no. Description XOUT O 1 Crystal oscillator connection pin OE I 2 Clock output enable pin L : output disable, H : output enable SP I/O 3 Serial program pin VSS 4 GND pin OUT O 5 Clock output pin VF I 6 Variable function pin It is possible to set the pin function to one of the followings by setting to a memory. <Modulation enable> L : Modulation disable, H: Modulation enable <Power down control> Power down by the "L" input <Output setting select> L : 1 setting, H : 2 setting VDD 7 Power supply voltage pin XIN I 8 Crystal oscillator connection pin/clock input pin DS04-29146-4E MB88R157A I/O CIRCUIT TYPE Pin name OE Circuit type Remarks * CMOS hysteresis input * With pull-up resistor (50 k) VF CMOS hysteresis input SP With pull-up resistor (50 k) In input mode * CMOS hysteresis input In serial output mode * CMOS output * IOL = 12 mA OUT * CMOS output * IOL = 4 mA/8 mA selectable (Selectable by Output driver setting bit) * Hi-Z or "L" output at OE pin = "L" input (Selectable by OUT pin setting bit) Note: About XIN and XOUT pins, please refer to " CRYSTAL OSCILLATION CIRCUIT". DS04-29146-4E 3 MB88R157A HANDLING DEVICES 1. Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower than GND is applied to an input or output pin or (b) a voltage higher than the rating is applied between power supply and GND. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. 2. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. When SP pin is not in use, please connect it to VDD power supply. Handle by other unused pins, using a pull-up or pull-down resistor. 3. Notes for when the external clock is used To use an external clock signal, input the clock signal to the XIN pin and the XOUT pin set open. 4. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between power supply and GND near the device, as a bypass capacitor. 5. Crystal Oscillation circuit Noise near the XIN pin and XOUT pin may cause the device to malfunction. Design printed circuit boards so that electric wiring of the XIN pin or the XOUT pin and the crystal oscillator do not intersect other wiring. Design the printed circuit board that surrounds the XIN pin and XOUT pin with ground in order to stabilize operation. 4 DS04-29146-4E MB88R157A BLOCK DIAGRAM VDD Output control OE N div. OSC XIN XOUT Frequency phase comparison Charge Pump Loop Filter VCO K div. OUT M div PLL block Non-volatile memory Modulation control circuit Serial-I/F VF Serial data SP VSS IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. DS04-29146-4E 5 MB88R157A MEMORY MAP Address Setting 1 Function Remarks bit0, bit1 VF pin function setting The function for the VF pin (pin 6) is selectable. 00 : No modulation, 01 : Output selection function, 10 : Modulation control, 11 : Power down control bit2 to bit8 XIN oscillation stabilization capacitance setting (7-bit) Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step bit9 to bit15 XOUT oscillation stabilization capacitance setting (7-bit) Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step bit16 to bit27 M divider setting 1 (12-bit) Selectable in the range of 2 to 4095 bit28 to bit38 N divider setting 1 (11-bit) Selectable in the range of 2 to 2047 bit39 to bit45 K divider setting 1 (7-bit) Selectable in the range of 1 to 128 bit46 to bit48 L divider setting 1 (3-bit) Modulation frequency setting (the value is due to the input frequency) bit49 to bit52 Charge Pump setting 1 (4-bit) Charge pump current setting due to VCO oscillation frequency bit53 to bit57 VCO Gain setting 1 (5-bit) VCO gain setting due to VCO oscillation frequency bit58 to bit61 Modulation rate setting 1 (4-bit) No modulation, 0.125%, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75% are selectable bit62 Output drive ability setting 1 0: Ability small, 1: Ability large bit63 Output slew rate ability setting 1 0 : Slew rate low, 1 : Slew rate high bit64 OUT pin setting 1 Selectable OUT pin status at OE pin = L and power down 0 : L output, 1 : Hi-Z output bit65 Source clock dividing mode 1 Source clock for K divider is selectable. 0 : VCO output , 1 : Source clock bit66 PLL mode 1 0 : Normal mode, 1 : PLL mode bit67 Input clock setting 1 0 : External clock input, 1 : Crystal oscillator bit68 to bit71 Reserve (Continued) 6 DS04-29146-4E MB88R157A (Continued) Address Setting 2 Function Remarks bit72 to bit83 M divider setting 2 (12-bit) Selectable in the range of 2 to 4095 bit84 to bit94 N divider setting 2 (11-bit) Selectable in the range of 2 to 2047 bit95 to bit101 K divider setting 2 (7-bit) Selectable in the range of 1 to 128 bit102 to bit104 L divider setting 2 (3-bit) Modulation frequency setting (the value is due to the input frequency) bit105 to bit108 Charge Pump setting 2 (4-bit) Charge pump current setting due to VCO oscillation frequency bit109 to bit113 VCO Gain setting 2 (5-bit) VCO gain setting due to VCO oscillation frequency bit114 to bit117 Modulation rate setting 2 (4-bit) No modulation, 0.125%, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50%, 1.75% are selectable bit118 Output drive ability setting 2 0: Ability small, 1: Ability large bit119 Output slew rate ability setting 2 0 : Slew rate low, 1 : Slew rate high bit120 OUT pin setting 2 Selectable OUT pin status at OE pin = L and power down 0 : L output, 1 : Hi-Z output bit121 Source clock dividing mode 2 Source clock for K divider is selectable. 0 : VCO output , 1 : Source clock bit122 PLL mode 2 0 : Normal mode, 1 : PLL mode bit123 Input clock setting 2 0 : External clock input, 1 : Crystal oscillator bit124 to bit127 DS04-29146-4E Reserve 7 MB88R157A OPERATION SETTING * Frequency setting Output frequency can be set by writing the internal memory to each divider parameter in the PLL block. Internal oscillation frequency and output frequency can be calculated by the following expressions : Internal oscillation frequency (fvco*) = Input frequency (fin) x (M+1) / (N+1) * : Please set the fvco range from 20 MHz to 134 MHz. Output frequency (fOUT*) = Input frequency (fin) x (M+1) / ( (N+1) x K) * : Please set the fOUT range from 1 MHz to 134 MHz. (Setting example) fin = 27 MHz, fOUT = 60 MHz M divider parameter : 339 ( = 153H) , N divider parameter : 152 ( = 98H) , K divider parameter : 1 ( = 01H) 27 x (339 + 1)/ ((152 + 1) x 1) = 60 [MHz], (fvco: 27 x (339 + 1) / (152 + 1) 60 [MHz]) Note: Recommended value of each divider parameter is different at PLL mode and normal mode. Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * Modulation frequency setting Modulation frequency can be set by writing L divider parameter to the internal memory. The average of modulation frequency can be calculated by the following expressions : Input frequency 532 x (L+1) (L = 0, 1, 2, 3, 4, 5, 6, 7) Note: Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. * Modulation rate setting Modulation rate can be selectable from no modulation, 0.125%, 0.25%, 0.50%, 0.75%, 1.00%, 1.25%, 1.50% and 1.75% * Charge Pump setting, VCO gain setting Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. 8 DS04-29146-4E MB88R157A * Output drive ability setting The output drive ability of the OUT pin can be selected. bit62, bit118 OUT pin drive ability 0 Small (IOL = 4 mA) 1 Large (IOL = 8 mA) * Output slew rate ability setting The output slew rate ability of the OUT pin can be selected. bit63, bit119 OUT pin slew rate ability 0 Slew rate low 1 Slew rate high * OUT pin setting The OUT pin status can be selected at OE pin "L" input and power down. bit64, bit120 OUT pin status 0 "L" output 1 "Hi-Z" output Note: Internal oscillation circuit has been operating even if the OE pin is inputting "L". * Source clock dividing setting Source clock for K divider can be selected. When "input frequency" is selected, source clock or its divided clock can be output. But modulation setting is not enabled. bit65, bit121 Source clock for K divider 0 VCO output clock 1 Input clock (Source clock) * PLL mode setting It can be selected from normal mode and PLL mode by bit48 setting in the memory map. PLL mode is good jitter specification at non modulation. When the mode is selected, it becomes non modulation setting, the resistance and capacitance value of the loop filter is changed, so oscillation specification will change. These changing do not depend on the modulation level setting. bit66, bit122 Operation mode 0 SSCG mode 1 PLL mode When PLL mode is selected, the recommended value of M, N, K divider is changed. Please refer and confirm the recommended value by our support tool. Contact the sales representatives for details on the support tools. DS04-29146-4E 9 MB88R157A * Input clock setting The input type of the source clock is selectable. bit67, bit123 Input clock 0 External clock input 1 Crystal oscillator * VF pin function setting The function for the VF pin (pin6) is selectable. bit1 bit0 VF pin (pin6) function 0 0 No function 0 1 Output selection function 1 0 Modulation control 1 1 Power down control When setting the output select function, either setting 1 or setting 2 is selected to operate at the input level of pin6 while turning the power on. Even if the input level of pin6 is changed during the operation, the operation cannot be changed. When setting the output select function, it is recommended to connect pin6 to Pull-up or Pull-down. Setting 1 is selected to operate when the mode other than the output select function is set. pin6 Operation at selection function setting L Operation in setting 1 H Operation in setting 2 When setting the modulation control, the modulation function is turned on and off at the input level of pin6. pin6 Operation at modulation control setting L No modulation H Execute the modulation operation according to the modulation rate setting When setting the power down control, the power down control for the whole device is performed at the input level of pin6. pin6 Operation at power down control setting 10 L Power down H Clock output operation DS04-29146-4E MB88R157A * Oscillation stabilization capacitance setting The capacitance connected to the XIN and the XOUT pins can change from 5 pF to 10 pF by setting bit2 to bit8 and bit9 to bit15 in the memory map (set "1" to bit67 or bit123). Also, it is possible to cancel the connection whose capacitance is 5 pF for the XIN pin and the XOUT pin by setting bit67 or bit123. When using the external clock to the clock input, connections for all capacitance need to be cancelled. XIN bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit67, bit123 XOUT bit15 bit14 bit13 bit12 bit11 bit10 bit9 Capacitance [pF] 5.000 2.520 1.260 0.630 0.315 0.157 0.079 0.039 Capacitance [pF] 0 0 0 0 0 0 0 0 0.000 1 0 0 0 0 0 0 0 5.000 1 0 0 0 0 0 0 1 5.039 1 0 0 0 0 0 1 0 5.079 1 0 0 0 0 0 1 1 5.118 1 0 0 0 0 1 0 0 5.157 *** 1 0 0 0 0 1 1 1 5.275 1 0 0 0 1 0 0 0 5.315 *** 1 0 0 0 1 1 1 1 5.590 1 0 0 1 0 0 0 0 5.630 *** 1 0 0 1 1 1 1 1 6.220 1 0 1 0 0 0 0 0 6.260 *** 1 0 1 1 1 1 1 1 7.480 1 1 0 0 0 0 0 0 7.520 *** 1 1 1 1 1 XIN 1 1 1 XOUT 5 pF 5 pF bit8 bit67 (bit123) DS04-29146-4E 10.000 bit6 bit7 bit4 bit5 bit2 bit3 bit9 bit11 bit10 bit13 bit12 bit14 bit15 bit67 (bit123) 11 MB88R157A MEMORY ACCESS pa The non-volatile memory contained in this device can read/write using the serial communication that the SP pin works as the I/O pin. The communication protocol needs to set LSB first, NRZ format, 8-bit length, no parity and stop bit length 1-bit in the UART asynchronous transfer mode. The transfer speed needs to be set to 1/512 of the device source oscillation. * Transfer sequence 50 ms 2.5 V VDD SP Memory access mode signal (internal) OUT Source clock output 1. More than 50 ms after this device is turned on, input a command from the SP pin and set MB88R157A into memory access mode.(When a command is input by serial communication, data of "FDH" is sent.) Note: When memory access is available, source clock can be output from the OUT pin. Fix the SP pin to "H" or "L" until command input. 2. At writing, "00H" is sent serially, and at reading, "40H" is sent serially. Note: This device needs to stop outputting to the SP pin of the transferred device within 9 s after transferring "40H" serially at the reading state and place it to a receivable state. 3. At writing : Send 16-byte data blocks from the lower address of the memory map in turn with more than or equal to 30 s between each data block. At reading : This device outputs 16-byte data blocks from the lower address of the memory map in turn. Note: 16-byte is required to transfer data even if setting 2 is not used. 4. Repeat the operations of 2. and 3. for re-writing and re-reading. To operate the device using the written data, turn on the power again. However, the oscillation stabilization capacitance is set simultaneously with writing to memory. When the oscillation stabilization capacitance and the crystal oscillation frequency are adjusted, change the oscillation stabilization capacitance value so that the clock output from the OUT pin is set to the desired frequency. 12 DS04-29146-4E MB88R157A * Interconnection example *1 UO SP UI MB88R157A UCK Microcontroller with built-in UART etc. 2 Clock * Generator *1: Set the UO pin to Hi-Z to read from memory, as the SP pin serves for serial I/O. UO : UART serial data output pin UI : UART serial data input pin UCK : UART serial synchronous clock I/O pin *2: Because the transfer rate is set to 1/512 of source oscillation in MB88R157A, the clock generator is used as shown in the figure above. However, the clock generator is not needed if the transfer speed can be maintained from an internal clock of the baud rate generator of the UART. DS04-29146-4E 13 MB88R157A ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max VDD - 0.5 + 4.0 V VI VSS - 0.5 VDD + 0.5 V VO VSS - 0.5 VDD + 0.5 V Storage temperature*2 TST - 55 + 125 C Operation junction temperature*2 TJ - 40 + 125 C Output current IO - 10 + 10 mA Overshoot VIOVER VDD + 1.0 (tOVER 50 ns) V Undershoot VIUNDER VSS - 1.0 (tUNDER 50 ns) V Power supply voltage*1 1 Input voltage* Output voltage* 1 *1: This parameter is based on VSS = 0.0 V *2: Even if the maximum ratings for storage temperature and operation junction temperature are within the temperature conditions, saved data in FRAM is not necessarily guaranteed. Contact the sales representatives for details on data's guarantee outside of the recommended operating conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER 50 ns VIOVER VDD + 1.0 V VDD Input pin VSS tOVER 50 ns 14 VIUNDER VSS - 1.0 V DS04-29146-4E MB88R157A RECOMMENDED OPERATING CONDITONS Parameter Symbol Pin name Conditions Power supply voltage VDD VDD "H" level input voltage VIH "L" level input voltage VIL OE, SP, VP Input clock duty cycle tDCI XIN 10 MHz to 50 MHz Write to the internal non-volatile memory Operating temperature Tj First access after the re-flow Other than those above Value Unit Min Typ Max 2.7 3.3 3.6 V VDD x 0.8 VDD + 0.3 V VSS - 0.3 VDD x 0.2 V 40 50 60 % 0 + 50 C -20 + 85 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI = tb / ta) ta tb VDD/2 XIN DS04-29146-4E 15 MB88R157A ELECTRICAL CHARACTERISTICS * DC Characteristics (Ta = - 20 C to + 85 C, VDD = 2.7 V to 3.6 V) Parameter Symbol Pin name Conditions Unit Min Typ Max 24 MHz input (Crystal) , 24 MHz internal oscillation, 24 MHz output no load capacitance 5 7 mA ICC2 Source oscillation 50 MHz input clock, 134 MHz internal oscillation, 134 MHz output 15 pF load capacitance 23 mA ICCH At power down 5 60 A VOH "H" level output Driving voltage (low) IOH = -4 mA, Driving voltage (high) IOH = -8 mA VDD - 0.5 VDD V VSS 0.4 V 20 50 150 k 10 pF 15 pF ICC Power supply current VDD OUT Output voltage VOL "L" level output Driving voltage (low) IOL = 4 mA, Driving voltage (high) IOL = 8 mA Pull-up resistance RPU OE, SP Input capacitance CIN XIN, Ta = + 25 C, OE, SP, VDD = VI = 0.0 V, VF f = 1 MHz Load capacitance CL 16 Value OUT DS04-29146-4E MB88R157A * AC characteristics (1) (Ta = - 20 C to + 85 C, VDD = 2.7 V to 3.6 V) Parameter SymPin bol name Conditions Value Min Typ Max Unit Crystal oscillation frequency fx XIN, XOUT Fundamental oscillation 10 40 3rd over-tone 40 48 Input frequency fin XIN 10 50 MHz Internal oscillation frequency fVCO 20 134 MHz Output frequency fOUT 1 134 MHz Slewing rate low, Driving ability small, Load capacitance 15pF 0.44 Slewing rate high, Driving ability small, Load capacitance 15pF 0.47 Slewing rate low, Driving ability large, Load capacitance 15pF 0.79 Slewing rate high, Driving ability large, Load capacitance 15pF 0.90 Driving ability small 58 Driving ability large 29 VCO clock output 40 60 At reference clock output TDCI - 10* TDCI + 10*1 fin/(448 x (L + 1)) (448 x (L + 1)) fin/(532 x (L + 1)) (532 x (L + 1)) fin/(616 x (L + 1)) (616 x (L + 1)) kHz (clks) 0.2 V to 3.0 V 0.05 20 ms SSCG mode 400/fin+6 400/fin+10 PLL mode 400/fin+2 400/fin+3 SSCG mode 6 10 PLL mode 2 3 fOUT 3 MHz No load capacitance fOUT < 3 MHz 100 200 psrms Output slewing rate*2 SR OUT Output impedance ZO Output clock duty cycle tDCC Modulation frequency (number of input clocks per one modulation) FMOD (NMOD) Power supply time tR VDD At power on Lock-up time tLK At power down release OUT MHz V/ns 1 % ms Cycle-cycle jitter tJC Output stop time from OE exit. tOD ta = 1/ fOUT 2 x ta ns Output start time after OE entry tOE ta = 1/ fOUT 2 x ta ns (Continued) DS04-29146-4E 17 MB88R157A (Continued) *1: The REFOUT output duty cycle value depends on the duty cycle of input clock tDCI. Either case of A or B will be guaranteed. A. Crystal oscillator : Oscillating correctly with the crystal oscillator connected with XIN, XOUT B. External clock input : The input level is Full - swing (VSS - VDD). *2: The condition for slew rate measurement is the average value between 0.2 x VDD and 0.8 x VDD when the pin load is 15 pF. * AC characteristics (2) (tr/tf) (Ta = - 20 C to + 85 C, VDD = 3.3 V 0.3 V) Parameter Output clock rising time Output clock falling time Symbol tr tf Pin name OUT OUT Conditions Value Min Typ Max Slewing rate low, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 4.6 Slewing rate high, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 4.3 Slewing rate low, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.6 Slewing rate high, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.3 Slewing rate low, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 4.6 Slewing rate high, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 4.3 Slewing rate low, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.6 Slewing rate high, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.3 Unit ns ns (Ta = - 20 C to + 85 C, VDD = 2.7 V to 3.0 V) Parameter Output clock rising time Output clock falling time 18 Symbol tr tf Pin name OUT OUT Conditions Value Min Typ Max Slewing rate low, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 5.2 Slewing rate high, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 5.2 Slewing rate low, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.8 Slewing rate high, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.8 Slewing rate low, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 5.2 Slewing rate high, Driving ability small, Load capacitance 15 pF, 0.4 V to 2.4 V 5.2 Slewing rate low, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.8 Slewing rate high, Driving ability large, Load capacitance 15 pF, 0.4 V to 2.4 V 2.8 Unit ns ns DS04-29146-4E MB88R157A DEFINITION of MODULATION FREQUENCY and NUMBER of INPUT CLOCKS PER MODULATION f (Output frequency) Modulation wave form t FMOD(Min) FMOD(Max) V Input clock Clock count Clock count NMOD(Max) NMOD(Min) t This product contains the modulation period to realize the efficient EMI reduction. The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max). Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modulation period FMOD. TURNING ON POWER SUPPLY AND LOCK-UP TIME tR 3.0 V VDD 0.2 V Clock stabilization wait time tLK XIN OUT DS04-29146-4E 19 MB88R157A OUTPUT CLOCK DUTY CYCLE (tDCC = tb / ta) ta tb OUT VDD/2 RISE AND FALL TIME (tr/tf) 2.4 V OUT 0.4 V tr tf CYCLE-CYCLE JITTER (tJC = | tn - tn+1 | ) OUT tn 20 tn+1 DS04-29146-4E MB88R157A OUTPUT TIMING AT OE CHANGE * Output stop time from OE exit VDD x 0.2[V] OE ta tOD "Hi-Z" or "L" (depend on setting of bit64/bit120) OUT * Output start time after OE entry VDD x 0.8[V] OE tOE "Hi-Z" or "L" (depend on setting of bit64/bit120) OUT DS04-29146-4E 21 MB88R157A LOCK-UP TIME XIN VIH VIL VF tLK (lock-up time) OUT When the power down control by the VF pin is valid and the power down is controlled, the desired clock frequency can be gained once the lock up time tLK has elapsed up to its maximum after the VF pin gets to the H level. XIN VIH VF VIL tLK (lock-up time ) tLK (lock-up time) OUT When the modulation control by the VF pin is valid and the modulation is controlled, the frequency set by the OUT pin output can be set once the lock up time tLK has elapsed up to its maximum after the level for the VF pin is decided. Note: The output frequency, the output clock duty cycle, the modulation cycle and the cycle-cycle jitter cannot be guaranteed until the lock up time has fully elapsed. Therefore, it is recommended to cancel the late reset of the device or execute other means after the lock up time elapses. 22 DS04-29146-4E MB88R157A * AC characteristics (3) (Serial interface timing) (Ta = - 20 C to + 85 C, VDD = 2.7 V to 3.6 V) Parameter Symbol Cycle time of transfer and receiver Pin name Conditions Value Unit Min Typ Max tSCYC (tin x 512) x 0.95 tin x 512 (tin x 512) x 1.06 s Command / write data receiver interval tDD 30 s Read operation Read command receive SP pin read data output tRDO 9 s Read operation Final read data output SP pin input mode exchanged tOTI 60 s SP * Cycle of transfer and receiver VDD*0.8 SP D0 VDD*0.2 D1 D2 D3 D4 D5 D6 D7 tSCYC * Command / write data receiver interval D7 SP Start bit Stop bit D0 tDD * Read operation Output read data D7 SP Stop bit Hi-Z Start bit tRDO Read command received Received data OE pin output SP D7 D0 Hi-Z Stop bit tOTI DS04-29146-4E 23 MB88R157A INTERCONNECTION CIRCUIT EXAMPLE Xtal 1 8 2 7 3 4 MB88R157A 6 5 R1 C1 C2 C1 : Tantalum or electrolytic capacitor of 10 F or higher C2 : Capacitor of about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) R1 : Impedance matching resistor for board pattern 24 DS04-29146-4E MB88R157A CRYSTAL OSCILLATION CIRCUIT The left hand side figure below shows the connection example about general crystal oscillator. The oscillation circuit has the built-in feedback resistor (1 M) and oscillation stabilization capacitance (C1 and C2). C1 and C2 value can be changeable by setting bit2 to bit8 and bit9 to bit15 in memory. It is necessary to set suitable parameter for each crystal oscillator. The right hand side figure below shows the connection example for the 3rd overtone oscillation crystal. It is necessary to set the value for capacitance (C1,C2,C3) and inductance (L1) to suitable parameter for each crystal oscillator. To use an external clock signal (without using the crystal oscillator), input the clock signal to the XIN pin and XOUT pin set open. * When using a crystal oscillator Rf (1 M) Rf (1 M) C2 C1 C2 C1 MB88R157A LSI internal XIN pin XOUT pin XOUT pin XIN pin MB88R157A LSI external L1 C3 Normal crystal oscillator DS04-29146-4E 3rd over-tone crystal oscillator 25 MB88R157A ORDERING INFORMATION Part number MB88R157APFT-G-JNE1 MB88R157APFT-G-JN-ERE1 MB88R157APFT-G-JN-EFE1 MB88R157APFT-G-XXX-JNE1 MB88R157APFT-G-XXXJNERE1 MB88R157APFT-G-XXXJNEFE1 26 Package Remarks 8-pin plastic TSSOP (FPT-8P-M07) DS04-29146-4E MB88R157A PACKAGE DIMENSION 8-pin plastic TSSOP Lead pitch 0.65 mm Package width x package length 4.40 mm x 3.10 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm Max (FPT-8P-M07) 8-pin plastic TSSOP (FPT-8P-M07) Note) Pins width and pins thickness include plating thickness. 0.1270.08 (.0050.003) 3.100.10(.122.004) 8 5 4.400.10 6.400.20 (.173.004) (.252.008) INDEX Details of "A" part 1.20(.047)MAX 4 1 "A" 0.65(.026) 0.220.10 (.009.004) TYP 0~8 0.50(.020) NOM 0.600.10 (.024.004) 0.100.05 (Stand off) (.004.002) 0.25(.010) 0.10(.004) 1.95(.077) REF C 2006-2010 FUJITSU SEMICONDUCTOR LIMITED F08015Sc-1-3 Dimensions in mm (inches). Note: The values in parentheses are reference values Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS04-29146-4E 27 MB88R157A MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results FEATURES 1 28 Corrected the following description : Non-volatile memory : FRAM (data retention : 10 years ( + 55 C)) Non-volatile memory : FRAM (data retention : 10 years ( + 85 C)) DS04-29146-4E MB88R157A MEMO DS04-29146-4E 29 MB88R157A MEMO 30 DS04-29146-4E MB88R157A MEMO DS04-29146-4E 31 MB88R157A FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. 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LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. 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