FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2010-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.9
ASSP
Spread Spectrum Clock Generator
MB88R157A
■DESCRIPTION
MB88R157A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary
radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate per iodically
with the internal modulator.
This product has a built-in non-volatile memory, so its frequency setting can memorize each system or
application.
Also the product has a built-in oscillation stabilization circuit, so it is not necessary to use the external
oscillation stabilization capacitance.
■FEATURES
• Input frequency : 10 MHz to 50 MHz
• Output frequency : 1 MHz to 134 MHz
Programmable of the parameter of N divider, M divider, K divider
(N divider : 11-bit, M divider : 12-bit, K divider : 7-bit)
• Modulation rate : no modulation, ±0.125%, ±0.25%, ±0.5%, ±0.75%, ±1.0%, ±1.25%, ±1.5%, ±1.75%
• Variable function pin
It is possible to switch the VF pin function by setting to a non-volatile memor y.
Modulation enabled: It is possible to turn on/off the modulation operation.
Power down control
Output setting selection: It is possible to save two types of frequency setting into a non-volatile memory,
and to select the type to operate.
• Equipped with a crystal oscillation circuit
• Built-in oscillation stabilization capacitance : 5 pF to 10 pF (0.039 pF step range)
• Clock output Duty : 40% to 60% (Load capacitance 15 pF or less)
• Clock Cycle-Cycle Jitter : Less than 100 ps (Output clock is over 3 MHz)
• Low power consumption by CMOS process 5 mA (24 MHz, Typ-sample, no load) [Target value]
(Input frequency : 24 MHz, N divider parameter : 200, M divider parameter : 200, K divider parameter : 1)
• At power down: 5 μA (Power supply voltage = 3.3 V, at room temperature) [Target value]
• Non-volatile memory : FRAM (data retention : 10 years ( + 85 °C))
• Po wer supply voltage : 2.7 V to 3.6 V
• Operating temperature −20 °C to + 85 °C
• Package : 8-pin plastic TSSOP
DS04–29146–4E
MB88R157A
2DS04–29146–4E
■PIN ASSIGNMENT
■PIN DESCRIPTION
Pin name I/O Pin no. Description
XOUT O 1 Crystal oscillator connection pin
OE I 2 Clock output enable pin
L : output disable, H : output enable
SP I/O 3 Serial program pin
VSS ⎯4GND pin
OUT O 5 Clock output pin
VF I 6
Variable function pin
It is possible to set the pin function to one of the followings by
setting to a memory.
<Modulation enable>
L : Modulation disable, H: Modulation enable
<Power down control>
Power down by the “L” input
<Output setting select>
L : 1 setting, H : 2 setting
VDD ⎯7 Power supply voltage pin
XIN I 8 Crystal oscillator connection pin/clock input pin
XOUT
OE
SP
VSS
1
2
3
4
8
7
6
5
XIN
VDD
VF
OUT
TOP VIEW
(FPT-8P-M07)
MB88R157A
DS04–29146–4E 3
■I/O CIRCUIT TYPE
Note: About XIN and XOUT pins, please refer to “■ CRYSTAL OSCILLATION CIRCUIT”.
Pin
name Circuit type Remarks
OE • CMOS hysteresis input
• With pull-up resistor (50 kΩ)
VF CMOS hysteresis input
SP With pull-up resistor (50 kΩ)
In input mode
• CMOS hysteresis input
In serial output mode
• CMOS output
•I
OL = 12 mA
OUT • CMOS output
•I
OL = 4 mA/8 mA selectable
(Selectable by Output driver setting
bit)
• Hi-Z or “L” output at OE pin = “L” input
(Selectable by OUT pin setting bit)
MB88R157A
4DS04–29146–4E
■HANDLING DEVICES
1. Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower
than GND is applied to an input or output pin or (b) a voltage higher than the rating is applied between power
supply and GND. The latch-up, if it occurs, significantly increases the po wer supply current and may cause
thermal destr uction of an element. When you use this device, be very careful not to exceed the maximum
rating.
2. Handling unused pins
Do not leave an unused input pin open, since it may cause a malfunction.
When SP pin is not in use, please connect it to VDD power supply. Handle by other unused pins, using a
pull-up or pull-down resistor.
3. Notes for when the external clock is used
To use an external clock signal, input the clock signal to the XIN pin and the XOUT pin set open.
4. Power supply pins
Please design connecting the power supply pin of this device by as low impedance as possible from the
current supply source.
We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in
parallel between power supply and GND near the device, as a bypass capacitor.
5. Crystal Oscillation circuit
Noise near the XIN pin and XOUT pin may cause the device to malfunction. Design printed circuit boards
so that electric wiring of the XIN pin or the XOUT pin and the crystal oscillator do not intersect other wiring.
Design the printed circuit board that surrounds the XIN pin and XOUT pin with ground in order to stabilize
operation.
MB88R157A
DS04–29146–4E 5
■BLOCK DIAGRAM
Charge
Pump Loop
Filter VCO
VDD
VSS
OE
XIN
XOUT
SP
OUT
VF
N div.
M div
K
div.
PLL block
Non-volatile memory
Serial-I/F Modulation control
circuit
OSC
Output control
Serial data
IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI.
Frequency
phase
comparison
MB88R157A
6DS04–29146–4E
■MEMORY MAP
(Continued)
Address Function Remarks
bit0, bit1 VF pin function setting
The function for the VF pin (pin 6) is selectable.
00 : No modulation, 01 : Output selection func-
tion,
10 : Modulation control, 11 : Power down control
bit2 to bit8 XIN oscillation stabilization
capacitance setting (7-bit) Capacitance is selectable from 5 pF to 10 pF by
0.039 pF Step
bit9 to bit15 XOUT oscillation stabilization
capacitance setting (7-bit) Capacitance is selectable from 5 pF to 10 pF by
0.039 pF Step
Setting
1
bit16 to bit27 M divider setting 1 (12-bit) Selectable in the range of 2 to 4095
bit28 to bit38 N divider setting 1 (11-bit) Selectable in the range of 2 to 2047
bit39 to bit45 K divider setting 1 (7-bit) Selectable in the range of 1 to 128
bit46 to bit48 L divider setting 1 (3-bit) Modulation frequency setting
(the value is due to the input frequency)
bit49 to bit52 Charge Pump setting 1 (4-bit) Charge pump current setting due to VCO oscilla-
tion frequency
bit53 to bit57 VCO Gain setting 1 (5-bit) VCO gain setting due to VCO oscillation frequency
bit58 to bit61 Modulation rate setting 1
(4-bit)
No modulation, ±0.125%, ±0.25%, ±0.50%,
±0.75%, ±1.00%, ±1.25%, ±1.50%, ±1.75% are
selectable
bit62 Output drive ability setting 1 0: Ability small, 1: Ability large
bit63 Output slew rate ability setting 1 0 : Slew rate low, 1 : Slew rate high
bit64 OUT pin setting 1 Selectable OUT pin status at OE pin = L and pow-
er down
0 : L output, 1 : Hi-Z output
bit65 Source clock dividing mode 1 Source clock for K divider is selectable.
0 : VCO output , 1 : Source clock
bit66 PLL mode 1 0 : Normal mode, 1 : PLL mode
bit67 Input clock setting 1 0 : External clock input, 1 : Crystal oscillator
bit68 to bit71 Reserve ⎯
MB88R157A
DS04–29146–4E 7
(Continued)
Address Function Remarks
Setting
2
bit72 to bit83 M divider setting 2 (12-bit) Selectable in the range of 2 to 4095
bit84 to bit94 N divider setting 2 (11-bit) Selectable in the range of 2 to 2047
bit95 to bit101 K divider setting 2 (7-bit) Selectable in the range of 1 to 128
bit102 to bit104 L divider setting 2 (3-bit) Modulation frequency setting (the value is due to
the input frequency)
bit105 to bit108 Charge Pump setting 2 (4-bit) Charge pump current setting due to VCO oscilla-
tion frequency
bit109 to bit113 VCO Gain setting 2 (5-bit) VCO gain setting due to VCO oscillation frequency
bit114 to bit117 Modulation rate setting 2
(4-bit)
No modulation, ±0.125%, ±0.25%, ±0.50%,
±0.75%, ±1.00%, ±1.25%, ±1.50%, ±1.75% are
selectable
bit118 Output drive ability setting 2 0: Ability small, 1: Ability large
bit119 Output slew rate ability setting 2 0 : Slew rate low, 1 : Slew rate high
bit120 OUT pin setting 2 Selectable OUT pin status at OE pin = L and pow-
er down
0 : L output, 1 : Hi-Z output
bit121 Source clock dividing mode 2 Source clock for K divider is selectable.
0 : VCO output , 1 : Source clock
bit122 PLL mode 2 0 : Normal mode, 1 : PLL mode
bit123 Input clock setting 2 0 : External clock input, 1 : Crystal oscillator
bit124 to bit127 Reserve ⎯
MB88R157A
8DS04–29146–4E
■OPERATION SETTING
• Frequency setting
Output frequency can be set by writing the internal memory to each divider parameter in the PLL block.
Internal oscillation frequency and output frequency can be calculated by the following expressions :
Internal oscillation frequency (fvco*) = Input frequency (fin) × (M+1) / (N+1)
* : Please set the fvco range from 20 MHz to 134 MHz.
Output frequency (fOUT*) = Input frequency (fin) × (M+1) / ( (N+1) × K)
* : Please set the fOUT range from 1 MHz to 134 MHz.
(Setting example)
fin = 27 MHz, fOUT = 60 MHz
M divider parameter : 339 ( = 153H) , N divider parameter : 152 ( = 98H) , K divider parameter : 1 ( = 01H)
27 × (339 + 1)/ ((152 + 1) × 1) = 60 [MHz], (fvco: 27 × (339 + 1) / (152 + 1) 60 [MHz])
Note: Recommended v alue of each divider parameter is diff erent at PLL mode and normal mode. Please ref er
and confirm the recommended value by our support tool. Contact the sales representatives for details
on the support tools.
• Modulation frequency setting
Modulation frequency can be set by writing L divider parameter to the internal memory.
The average of modulation frequency can be calculated by the following expressions :
Note: Please ref er and confirm the recommended value b y our support tool. Contact the sales representatives
for details on the support tools.
• Modulation rate setting
Modulation rate can be selectable from no modulation, ±0.125%, ±0.25%, ±0.50%, ±0.75%, ±1.00%, ±1.25%,
±1.50% and ±1.75%
• Charge Pump setting, VCO gain setting
Please ref er and confirm the recommended value b y our support tool. Contact the sales representatives f or
details on the support tools.
Input frequency
532 × (L+1) (L = 0, 1, 2, 3, 4, 5, 6, 7)
MB88R157A
DS04–29146–4E 9
• Output drive ability setting
The output drive ability of the OUT pin can be selected.
• Output slew rate ability setting
The output slew rate ability of the OUT pin can be selected.
• OUT pin setting
The OUT pin status can be selected at OE pin “L” input and power down.
Note: Internal oscillation circuit has been operating even if the OE pin is inputting “L”.
• Source clock dividing setting
Source clock for K divider can be selected.
When “input frequency” is selected, source clock or its divided clock can be output. But modulation setting
is not enabled.
• PLL mode setting
It can be selected from normal mode and PLL mode by bit48 setting in the memory map . PLL mode is good
jitter specification at non modulation. When the mode is selected, it becomes non modulation setting, the
resistance and capacitance value of the loop filter is changed, so oscillation specification will change. These
changing do not depend on the modulation level setting.
When PLL mode is selected, the recommended value of M, N, K divider is changed. Please refer and confirm
the recommended value by our support tool. Contact the sales representatives for details on the support tools.
bit62, bit118 OUT pin drive ability
0 Small (IOL = 4 mA)
1 Large (IOL = 8 mA)
bit63, bit119 OUT pin slew rate ability
0 Slew rate low
1Slew rate high
bit64, bit120 OUT pin status
0 “L” output
1 “Hi-Z” output
bit65, bit121 Source clock for K divider
0 VCO output clock
1 Input clock (Source clock)
bit66, bit122 Operation mode
0 SSCG mode
1 PLL mode
MB88R157A
10 DS04–29146–4E
• Input clock setting
The input type of the source clock is selectable.
• VF pin function setting
The function for the VF pin (pin6) is selectable.
When setting the output select function, either setting 1 or setting 2 is selected to operate at the input level
of pin6 while turning the power on. Even if the input level of pin6 is changed during the operation, the operation
cannot be changed.
When setting the output select function, it is recommended to connect pin6 to Pull-up or Pull-down.
Setting 1 is selected to operate when the mode other than the output select function is set.
When setting the modulation control, the modulation function is turned on and off at the input lev el of pin6.
When setting the pow er down control, the pow er down control f or the whole de vice is perf ormed at the input
level of pin6.
bit67, bit123 Input clock
0 External clock input
1 Crystal oscillator
bit1 bit0 VF pin (pin6) function
0 0 No function
0 1 Output selection function
1 0 Modulation control
1 1 Power down control
pin6 Operation at selection function setting
L Operation in setting 1
H Operation in setting 2
pin6 Operation at modulation control setting
L No modulation
HExecute the modulation operation according to
the modulation rate setting
pin6 Operation at power down control setting
L Power down
H Clock output operation
MB88R157A
DS04–29146–4E 11
• Oscillation stabilization capacitance setting
The capacitance connected to the XIN and the XOUT pins can change from 5 pF to 10 pF by setting bit2 to
bit8 and bit9 to bit15 in the memory map (set “1” to bit67 or bit123).
Also , it is possib le to cancel the connection whose c apacitance is 5 pF f or the XIN pin and the XOUT pin b y
setting bit67 or bit123.
When using the external clock to the clock input, connections for all capacitance need to be cancelled.
XIN bit67,
bit123 bit8 bit7 bit6 bit5 bit4 bit3 bit2
XOUT bit15 bit14 bit13 bit12 bit11 bit10 bit9
Capacitance
[pF] 5.000 2.520 1.260 0.630 0.315 0.157 0.079 0.039 Capacitance
[pF]
00000000 0.000
10000000 5.000
10000001 5.039
10000010 5.079
10000011 5.118
10000100 5.157
• • •⎯
10000111 5.275
10001000 5.315
• • •⎯
10001111 5.590
10010000 5.630
• • •⎯
10011111 6.220
10100000 6.260
• • •⎯
10111111 7.480
11000000 7.520
• • •⎯
11111111 10.000
XOUTXIN
5 pF5 pF
bit2
bit3
bit4
bit5
bit6
bit7
bit8
bit67
(bit123) bit67
(bit123)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
MB88R157A
12 DS04–29146–4E
pa
■MEMORY ACCESS
The non-v olatile memory contained in this device can read/write using the serial communication that the SP
pin works as the I/O pin.
The communication protocol needs to set LSB first, NRZ for mat, 8-bit length, no parity and stop bit length
1-bit in the UART asynchronous transfer mode. The transfer speed needs to be set to 1/512 of the device
source oscillation.
1. More than 50 ms after this device is turned on, input a command from the SP pin and set MB88R157A into
memory access mode.(When a command is input by serial communication, data of “FDH” is sent.)
Note: When memory access is available, source clock can be output from the OUT pin.
Fix the SP pin to “H” or “L” until command input.
2. At writing, “00H” is sent serially, and at reading, “40H” is sent serially.
Note: This de vice needs to stop outputting to the SP pin of the tr ansf erred device within 9 μs after transferring
“40H” serially at the reading state and place it to a receivable state.
3. At writing : Send 16-byte data blocks from the lower address of the memory map in turn with more than
or equal to 30 μs between each data block.
At reading : This device outputs 16-byte data blocks from the lower address of the memory map in turn.
Note: 16-byte is required to transfer data even if setting 2 is not used.
4. Repeat the operations of 2. and 3. for re-writing and re-reading.
To operate the device using the written data, turn on the power again.
However, the oscillation stabilization capacitance is set simultaneously with writing to memory. When the
oscillation stabilization capacitance and the crystal oscillation frequency are adjusted, change the oscillation
stabilization capacitance value so that the clock output from the OUT pin is set to the desired frequency.
VDD
SP
50 ms
2.5 V
OUT
Memory access
mode signal
(internal)
Source clock output
• Transfer sequence
MB88R157A
DS04–29146–4E 13
*1: Set the UO pin to Hi-Z to read from memory, as the SP pin serves for serial I/O.
UO : UART serial data output pin
UI : UART serial data input pin
UCK : UART serial synchronous clock I/O pin
*2: Because the transfer rate is set to 1/512 of source oscillation in MB88R157A, the clock generator is used
as shown in the figure above. However, the clock generator is not needed if the transfer speed can be
maintained from an internal clock of the baud rate generator of the UART.
MB88R157A
SP
UO
UI
UCK
Clock
Generator
*
1
*
2
Microcontroller with
built-in UART etc.
• Interconnection example
MB88R157A
14 DS04–29146–4E
■ABSOLUTE MAXIMUM RATINGS
*1: This parameter is based on VSS = 0.0 V
*2: Even if the maximum ratings for storage temperature and operation junction temperature are within the
temperature conditions , sav e d data in FRAM is not necessarily guaranteed. Contact the sales representa-
tives for details on data's guarantee outside of the recommended operating conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit
Min Max
Power supply voltage*1VDD − 0.5 + 4.0 V
Input voltage*1VIVSS − 0.5 VDD + 0.5 V
Output voltage*1VOVSS − 0.5 VDD + 0.5 V
Storage temperature*2TST − 55 + 125 °C
Operation junction temperature*2TJ − 40 + 125 °C
Output current IO − 10 + 10 mA
Overshoot VIOVER ⎯VDD + 1.0 (tOVER ≤ 50 ns) V
Undershoot VIUNDER VSS − 1.0 (tUNDER ≤ 50 ns) ⎯V
V
DD
VSS
Input pin
Overshoot/Undershoot
tUNDER ≤ 50 ns
VIOVER ≤ VDD + 1.0 V
tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V
MB88R157A
DS04–29146–4E 15
■RECOMMENDED OPERATING CONDITONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Pin
name Conditions Value Unit
Min Typ Max
Power supply voltage VDD VDD ⎯2.7 3.3 3.6 V
“H” level input voltage VIH OE,
SP, VP ⎯VDD × 0.8 ⎯VDD + 0.3 V
“L” level input voltage VIL VSS − 0.3 ⎯VDD × 0.2 V
Input clock duty cycle tDCI XIN 10 MHz to 50 MHz 40 50 60 %
Operating temperature Tj⎯
Write to the internal
non-volatile memory 0⎯ + 50 °C
First access after
the re-flow
Other than those
above −20 ⎯ + 85
XINVDD/2
ta
tb
Input clock duty cycle (tDCI = tb / ta)
MB88R157A
16 DS04–29146–4E
■ELECTRICAL CHARACTERISTICS
• DC Characteristics (Ta = − 20 °C to + 85 °C, VDD = 2.7 V to 3.6 V)
Parameter Symbol Pin
name Conditions Value Unit
Min Typ Max
Power supply
current
ICC
VDD
24 MHz input (Crystal) ,
24 MHz internal oscillation,
24 MHz output
no load capacitance
⎯57mA
ICC2
Source oscillation 50 MHz input
clock, 134 MHz internal oscillation,
134 MHz output
15 pF load capacitance
⎯⎯23 mA
ICCH At power down ⎯560μA
Output voltage
VOH
OUT
“H” level output
Driving voltage (low) IOH = −4 mA,
Driving voltage (high) IOH = −8 mA
VDD −
0.5 ⎯VDD V
VOL “L” level output
Driving voltage (low) IOL = 4 mA,
Driving voltage (high) IOL = 8 mA VSS ⎯0.4 V
Pull-up resistance RPU OE, SP ⎯20 50 150 kΩ
Input capacitance CIN XIN,
OE, SP,
VF
Ta = + 25 °C,
VDD = VI = 0.0 V,
f = 1 MHz ⎯⎯10 pF
Load capacitance CLOUT ⎯⎯⎯15 pF
MB88R157A
DS04–29146–4E 17
• AC characteristics (1) (Ta = − 20 °C to + 85 °C, VDD = 2.7 V to 3.6 V)
(Continued)
Parameter Sym-
bol Pin
name Conditions Value Unit
Min Typ Max
Crystal oscillation
frequency fx XIN,
XOUT Fundamental oscillation 10 ⎯40 MHz
3rd over-tone 40 ⎯48
Input frequency fin XIN ⎯10 ⎯50 MHz
Internal oscillation
frequency fVCO ⎯⎯ 20 ⎯134 MHz
Output frequency fOUT
OUT
⎯1⎯134 MHz
Output slewing
rate*2SR
Slewing rate low,
Driving ability small,
Load capacitance 15pF 0.44 ⎯⎯
V/ns
Slewing rate high,
Driving ability small,
Load capacitance 15pF 0.47 ⎯⎯
Slewing rate low,
Driving ability large,
Load capacitance 15pF 0.79 ⎯⎯
Slewing rate high,
Driving ability large,
Load capacitance 15pF 0.90 ⎯⎯
Output impedance ZODriving ability small ⎯58 ⎯Ω
Driving ability large ⎯29 ⎯
Output clock duty
cycle tDCC VCO clock output 40 ⎯60 %
At reference clock output TDCI − 10*1⎯TDCI + 10*1
Modulation
frequency
(number of input
clocks per one
modulation)
FMOD
(NMOD)⎯
fin/(448 ×
(L + 1))
(448 ×
(L + 1))
fin/(532 ×
(L + 1))
(532 ×
(L + 1))
fin/(616 ×
(L + 1))
(616 ×
(L + 1))
kHz
(clks)
Power supply time tRVDD 0.2 V to 3.0 V 0.05 ⎯20 ms
Lock-up time tLK
OUT
At power on SSCG mode ⎯400/fin+6 400/fin+10
ms
PLL mode ⎯400/fin+2 400/fin+3
At power
down re-
lease
SSCG mode ⎯610
PLL mode ⎯23
Cycle-cycle jitter tJC No load
capacitance fOUT ≥ 3 MHz ⎯⎯100 ps-
rms
fOUT < 3 MHz ⎯⎯200
Output stop time
from OE exit. tOD ta = 1/ fOUT ⎯⎯2 × tans
Output start time
after OE entry tOE ta = 1/ fOUT ⎯⎯2 × tans
MB88R157A
18 DS04–29146–4E
(Continued)
*1: The REFOUT output duty cycle value depends on the duty cycle of input clock tDCI. Either case of A or B
will be guaranteed.
A. Crystal oscillator : Oscillating correctly with the crystal oscillator connected with XIN, XOUT
B. External clock input : The input level is Full - swing (VSS - VDD).
*2: The condition for slew rate measurement is the aver age value between 0.2 × VDD and 0.8 × VDD when the
pin load is 15 pF.
• AC characteristics (2) (tr/tf)(Ta = − 20 °C to + 85 °C, VDD = 3.3 V ± 0.3 V)
(Ta = − 20 °C to + 85 °C, VDD = 2.7 V to 3.0 V)
Parameter Symbol Pin
name Conditions Value Unit
Min Typ Max
Output clock
rising time trOUT
Slewing rate low, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯4.6
ns
Slewing rate high, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯4.3
Slewing rate low, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.6
Slewing rate high, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.3
Output clock
falling time tfOUT
Slewing rate low, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯4.6
ns
Slewing rate high, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯4.3
Slewing rate low, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.6
Slewing rate high, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.3
Parameter Symbol Pin
name Conditions Value Unit
Min Typ Max
Output clock
rising time trOUT
Slewing rate low, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯5.2
ns
Slewing rate high, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯5.2
Slewing rate low, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.8
Slewing rate high, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.8
Output clock
falling time tfOUT
Slewing rate low, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯5.2
ns
Slewing rate high, Driving ability small,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯5.2
Slewing rate low, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.8
Slewing rate high, Driving ability large,
Load capacitance 15 pF, 0.4 V to 2.4 V ⎯⎯2.8
MB88R157A
DS04–29146–4E 19
■DEFINITION of MODULATION FREQUENCY and NUMBER of INPUT CLOCKS PER
MODULATION
This product contains the modulation period to realize the efficient EMI reduction.
The modulation period FMOD depends on the input frequency and changes between FMOD (Min) and FMOD (Max).
Furthermore, the typical value of the electrical characteristics is equivalent to the average value of the modu-
lation period FMOD.
■TURNING ON POWER SUPPLY AND LOCK-UP TIME
t
F
MOD
(Min) F
MOD
(Max)
N
MOD
(Max) N
MOD
(Min)
t
V
f (Output frequency)
Modulation wave form
Input clock
Clock count Clock count
tR
VDD 3.0 V
0.2 V
XIN
OUT
tLK
Clock stabilization
wait time
MB88R157A
20 DS04–29146–4E
■OUTPUT CLOCK DUTY CYCLE (tDCC = tb / ta)
■RISE AND FALL TIME (tr/tf)
■CYCLE-CYCLE JITTER (tJC = | tn − tn+1 | )
OUT VDD/2
ta
tb
t
f
t
r
2.4 V
0.4 V
OUT
t
n+1
t
n
OUT
MB88R157A
DS04–29146–4E 21
■OUTPUT TIMING AT OE CHANGE
t
OD
t
a
OE
OUT
V
DD
× 0.2[V]
• Output stop time from OE e xit
“Hi-Z” or “L”
(depend on setting of bit64/bit120)
tOE
OE
OUT
V
DD
× 0.8[V]
• Output start time after OE entry
“Hi-Z” or “L”
(depend on setting of bit64/bit120)
MB88R157A
22 DS04–29146–4E
■LOCK-UP TIME
When the power down control by the VF pin is valid and the power down is controlled, the desired clock
frequency can be gained once the lock up time tLK has elapsed up to its maximum after the VF pin gets to
the H level.
When the modulation control by the VF pin is valid and the modulation is controlled, the frequency set by
the OUT pin output can be set once the lock up time tLK has elapsed up to its maximum after the level for
the VF pin is decided.
Note: The output frequency, the output clock duty cycle , the modulation cycle and the cycle-cycle jitter cannot
be guaranteed until the lock up time has fully elapsed. Therefore, it is recommended to cancel the late
reset of the device or execute other means after the lock up time elapses.
V
IH
V
IL
XIN
VF
OUT
tLK
(lock-up time)
V
IH
V
IL
XIN
VF
OUT
tLK
(lock-up time ) tLK
(lock-up time)
MB88R157A
DS04–29146–4E 23
• AC characteristics (3) (Serial interface timing) (Ta = − 20 °C to + 85 °C, VDD = 2.7 V to 3.6 V)
Parameter Symbol Pin
name Condi-
tions Value Unit
Min Typ Max
Cycle time of transfer and receiver tSCYC
SP ⎯
(tin × 512)
× 0.95 tin × 512 (tin × 512)
× 1.06 μs
Command / write data receiver
interval tDD 30 ⎯⎯μs
Read operation
Read command receive →
SP pin read data output tRDO 9⎯⎯μs
Read operation
Final read data output →
SP pin input mode exchanged tOTI ⎯⎯60 μs
D0 D1 D2 D3 D4 D5 D6 D7
t
SCYC
VDD*0.2
SP
VDD*0.8
SP D7 Stop bit
t
DD
t
OTI
Start bit
D7 Stop bit Hi-Z
D0
SP
SP
D7 Stop bit Hi-Z
t
RDO
Start bit D0
• Command / write data receiver interval
• Read operation Output read data
Read command
received
OE pin output Received data
• Cycle of transfer and receiver
MB88R157A
24 DS04–29146–4E
■INTERCONNECTION CIRCUIT EXAMPLE
1
2
3
4
8
7
6
5
X
tal
MB88R157A
C
1
C
2
R
1
C1 : Tantalum or electrolytic capacitor of 10 μF or higher
C2 : Capacitor of about 0.01 μF (connect a capacitor of good high frequency property
(ex. laminated ceramic capacitor) to close to this device)
R1 : Impedance matching resistor for board pattern
MB88R157A
DS04–29146–4E 25
■CRYSTAL OSCILLATION CIRCUIT
The left hand side figure below shows the connection example about general crystal oscillator. The oscillation
circuit has the built-in feedback resistor (1 MΩ) and oscillation stabilization capacitance (C1 and C2).
C1 and C2 v alue can be changeab le by setting bit2 to bit8 and bit9 to bit15 in memory. It is necessary to set
suitable parameter for each crystal oscillator.
The right hand side figure below shows the connection e xample for the 3rd overtone oscillation crystal. It is
necessary to set the value for capacitance (C1,C2,C3) and inductance (L1) to suitable parameter for each
crystal oscillator.
To use an external clock signal (without using the crystal oscillator), input the clock signal to the XIN pin and
XOUT pin set open.
Rf (1 MΩ) Rf (1 MΩ)
C3
L1
C1C2C1C2
XIN pin XOUT pin
MB88R157A
LSI internal
MB88R157A
LSI external
XIN pin XOUT pin
3rd over-tone
crystal oscillator
• When using a crystal oscillator
Normal crystal oscillator
MB88R157A
26 DS04–29146–4E
■ORDERING INFORMATION
Part number Package Remarks
MB88R157APFT-G-JNE1
MB88R157APFT-G-JN-ERE1
MB88R157APFT-G-JN-EFE1
MB88R157APFT-G-XXX-JNE1
MB88R157APFT-G-XXXJNERE1
MB88R157APFT-G-XXXJNEFE1
8-pin plastic TSSOP
(FPT-8P-M07)
MB88R157A
DS04–29146–4E 27
■PACKAGE DIMENSION
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
8-pin plastic TSSOP Lead pitch 0.65 mm
Package width ×
package length 4.40 mm × 3.10 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.20 mm Max
8-pin plastic TSSOP
(FPT-8P-M07)
(FPT-8P-M07)
C
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F08015Sc-1-3
3.10±0.10(.122±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
INDEX
0.65(.026)
14
5
8
0.22±0.10
(.009±.004)
0.127±0.08
(.0050±.003)
"A"
1.95(.077)
0.50(.020)
NOM
0.60±0.10
(.024±.004)
0~8°
Details of "A" part
(.004±.002) (Stand off)
0.10±0.05
1.20(.047)MAX
TYP
REF
0.10(.004)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note) Pins width and pins thickness include plating thickness.
MB88R157A
28 DS04–29146–4E
■MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page Section Change Results
1■ FEATURES Corrected the following description :
Non-volatile memory : FRAM (data retention : 10 years ( + 55 °C))
→ Non-volatile memory : FRAM (data retention : 10 years ( + 85 °C))
MB88R157A
DS04–29146–4E 29
MB88R157A
30 DS04–29146–4E
MB88R157A
DS04–29146–4E 31
MB88R157A
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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FUJITSU SEMICONDUCTOR AMERICA, INC.
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
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http://kr.fujitsu.com/fsk/
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department