Intermediate Frequency Receiver,
800 MHz to 4000 MHz
Data Sheet
HMC8100LP6JE
Rev. B Document Feedback
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FEATURES
High linearity: supports modulations to 1024 QAM
Rx IF range: 80 MHz to 200 MHz
Rx RF range: 800 MHz to 4000 MHz
Rx power control: 80 dB
SPI programmable bandpass filters
SPI controlled interface
40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
Point to point communications
Satellite communications
Wireless microwave backhaul systems
GENERAL DESCRIPTION
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
input signals ranging from 800 MHz to 4000 MHz down to a
single-ended intermediate frequency (IF) signal of 140 MHz at its
output.
The IF receiver chip is housed in a compact 6 mm × 6 mm
LFCSP package and supports complex modulations up to
1024 QAM. The HMC8100LP6JE device includes two variable
gain amplifiers (VGAs), three power detectors, a programmable
automatic gain control (AGC) block, and selected integrated
band-pass filters with 14 MHz, 28 MHz, 56 MHz, and 112 MHz
bandwidth. The HMC8100LP6JE also supports baseband IQ
interfaces after the mixer so that the chips can be used in the
full outdoor units (ODU) configuration. The HMC8100LP6JE
supports all standard microwave frequency bands from 6 GHz
to 42 GHz.
FUNCTIONAL BLOCK DIAGRAM
22
2
1
4
5
3
12
11
AMP2_P
DVDD
AMP2_N
VCC_FILTER
FILTER2P
6
7
VCC_AMP3
GND1
8
VCC_BB
9
10
GND2
VGA_EXT_CAP
AMP1
GND21
23 VCC_AMP1
24 FILTER1P
25 VCC_VGA1
26 VCC_VGA1_BALUN
27 VCC_IRM
28 IRM_I_P
29 IRM_I_N
30 VDD
VCC_VGA3
RX_OUT
15
PD3_OUT_RSSI
14
PD3_IN
13
AUX_OUT
16VC_VGA_IF_CAP
17
VC_VGA_RF_CAP
18
VCC_PD1
19
20
PD1_OUT
RFIN
32
31
IRM_Q_N
IRM_Q_P
33 LOP
34 LON
35 SEN
36 SCLK
37 SDI
38 SDO
39
40
RST
REF_CLK_P
PACKAGE
BASE
GND
AGC
FILTER
14MHz
28MHz
56MHz
112MHz
SPI OTP
HMC8100
13867-001
Figure 1.
HMC8100LP6JE Data Sheet
Rev. B | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics: 800 MHz to 1800 MHz RF
Frequency Range .......................................................................... 3
Electrical Characteristics: 1800 MHz to 2800 MHz RF
Frequency Range .......................................................................... 4
Electrical Characteristics: 2800 MHz to 4000 MHz RF
Frequency Range .......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................9
External AGC Configuration.......................................................9
Internal AGC Configuration .................................................... 16
Theory of Operation ...................................................................... 18
Register Array Assignments and Serial Interface .................. 18
Register Descriptions ..................................................................... 20
Register Array Assignments...................................................... 20
Applications Information .............................................................. 24
Schematic/Typical Application Circuit ................................... 24
Evaluation Printed Circuit Board (PCB)................................. 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
9/2017—Rev. A to Reb. B
Changes to Figure 1 .......................................................................... 1
Changes to Figure 2 and Table 5 ..................................................... 7
Changes to Theory of Operation Section and Register Array
Assignment and Serial Interface Section ..................................... 18
Changes to Figure 50 and Figure 51 ............................................. 19
Changes to Figure 52 ...................................................................... 25
Changes to Ordering Guide .......................................................... 27
5/2016—v00.0416 to Rev. A
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Updated Format .................................................................. Universal
Added Pin Configuration Diagram, Renumbered
Sequentially ....................................................................................... 7
Added Ordering Guide .................................................................. 22
04/2016—v00.0416: Initial Version
Data Sheet HMC8100LP6JE
Rev. B | Page 3 of 27
SPECIFICATIONS
TA = 25°C, IF frequency = 140 MHz, local oscillator (LO) input signal level = 0 dBm, RF input signal level = −80 dBm per tone, filter
bandwidth = 56 MHz, IF gain limit (decimal) = 7, sideband select = lower sideband, AGC select = external AGC, unless otherwise noted,
see the Typical Performance Characteristics section.
ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE
Table 1.
Parameter
Min
Typ
Unit
OPERATING CONDITIONS
LO Frequency Range 600 2000 MHz
IF Frequency Range 80 200 MHz
RF INPUT INTERFACE
Input Impedance
50
Ω
Return Loss 10 dB
IF OUTPUT INTERFACE
Input Impedance 50 Ω
Return Loss 8 13 dB
LO INPUT INTERFACE
Input Impedance 50 Ω
Return Loss 2 9 dB
DYNAMIC PERFORMANCE
Power Conversion Gain 81 86 dB
RF VGA Dynamic Range 40 52 dB
IF VGA Dynamic Range 49 dB
Image Rejection 30 36 dBc
Noise Figure at PIN (One Tone) 5 8 dB
Output Third-Order Intercept (OIP3)
11
16
dBm
Output 1 dB Compression Point (OP1dB) 7 11 dBm
LO Leakage at the IF Input −48 −26 dBm
LO Leakage at the RF Input −75 −70 dBm
RF Leakage at the IF Output −68 −60 dBm
POWER SUPPLY
Supply Voltage
VCCX 3.3 V
VCC − VGA1 3.3 V
Supply Current
VCCX 600 mA
VCC − VGA1 11 μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
HMC8100LP6JE Data Sheet
Rev. B | Page 4 of 27
ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE
Table 2.
Parameter Min Typ Max Unit
OPERATING CONDITIONS
LO Frequency Range 1600 3000 MHz
IF Frequency Range 80 200 MHz
RF INPUT INTERFACE
Input Impedance 50 Ω
Return Loss 12 dB
IF OUTPUT INTERFACE
Input Impedance 50 Ω
Return Loss 8 13 dB
LO INPUT INTERFACE
Input Impedance 50 Ω
Return Loss 7 15 dB
DYNAMIC PERFORMANCE
Power Conversion Gain 77 85 dB
RF VGA Dynamic Range 40 47 dB
IF VGA Dynamic Range 40 49 dB
Image Rejection 30 36 dBc
Noise Figure at PIN (One Tone) 5 7 dB
Output Third-Order Intercept (OIP3) 11 18 dBm
Output 1 dB Compression Point (OP1dB) 7 11 dBm
LO Leakage at the IF Input −55 −45 dBm
LO Leakage at the RF Input −73 −66 dBm
RF Leakage at the IF Output −73 −65 dBm
POWER SUPPLY
Supply Voltage
V
CCX
3.3
V
VCC − VGA1 3.3 V
Supply Current
VCCX 600 mA
VCC − VGA1 11 μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
Data Sheet HMC8100LP6JE
Rev. B | Page 5 of 27
ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE
Table 3.
Parameter Min Typ Max Unit
OPERATING CONDITIONS
LO Frequency Range 2600 4200 MHz
IF Frequency Range 80 200 MHz
RF INPUT INTERFACE
Input Impedance 50 Ω
Return Loss 13 dB
IF OUTPUT INTERFACE
Input Impedance 50 Ω
Return Loss 8 13 dB
LO INPUT INTERFACE
Input Impedance 50 Ω
Return Loss 7 14 dB
DYNAMIC PERFORMANCE
Power Conversion Gain 72 82 dB
RF VGA Dynamic Range 35 47 dB
IF VGA Dynamic Range 49 dB
Image Rejection 30 38 dBc
Noise Figure at PIN (One Tone) 5 8 dB
Output Third-Order Intercept (OIP3) 12 22 dBm
Output 1 dB Compression Point (OP1dB) 7 12 dBm
LO Leakage at the IF Input
−65
−48
dBm
LO Leakage at the RF Input −66 −62 dBm
RF Leakage at the IF Output −72 −65 dBm
POWER SUPPLY
Supply Voltage
VCCX 3.3 V
VCC − VGA1 3.3 V
Supply Current
VCCX 600 mA
VCC − VGA1 11 μA
1 VCC – VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to 0 V (maximum ATTEN) to control the IF and RF VGA in external AGC mode.
HMC8100LP6JE Data Sheet
Rev. B | Page 6 of 27
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
RF Input 10 dBm
LO Input 10 dBm
VCCX −0.5 V to +5.5 V
−0.3 V to +3.6 V
Maximum Junction Temperature to
Maintain 1 Million Hour MTTF
150°C
Thermal Resistance (RTH), Junction to
Ground Paddle
10.5°C/W
Temperature
Operating −40°C to +85°C
Storage −65°C to +150°C
Maximum Peak Reflow Temperature
(MSL3)
260°C
ESD Sensitivity (Human Body Model) 2000 V (Class 2)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC8100LP6JE
Rev. B | Page 7 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AMP2_P
DVDD
AMP2_N
VCC_FILTER
FILTER2P
VCC_AMP3
GND1
VCC_BB
GND2
V
GA_EXT_CAP AMP1
GND
VCC_AMP1
FILTER1P
VCC_VGA1
VCC_VGA1_BALUN
VCC_IRM
IRM_I_P
IRM_I_N
VDD
VCC_VGA3
RX_OUT
PD3_OUT_RSSI
PD3_IN
AUX_OUT
VC_VGA_IF_CAP
VC_VGA_RF_CAP
VCC_PD1
PD1_OUT
RFIN IRM_Q_N
IRM_Q_P
LOP
LON
SEN
SCLK
SDI
SDO
RST
REF_CLK_P
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
HMC8100
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW
IM P EDANCE T HE RMAL AND E LECTRICAL GROUND PL ANE.
13867-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 DVDD SPI Digital Power Supply (3.3 V dc). See Figure 52 for the required components.
2 AMPT2_P Second Differential Amplifier Output (Positive).
3 AMP2_N Second Differential Amplifier Output (Negative).
4 VCC_FILTER Power Supply for the Filter (3.3 V dc). See Figure 52 for the required components.
5 FILTER2P Input of the Third External Filter Amplifier.
6 VCC_AMP3 Power Supply for the Third External Filter Amplifier (3.3 V dc). See Figure 52 for the required components.
7, 9, 21 GND1, GND2, GND3 Ground Connect.
8 VCC_BB Power Supply for the Baseband Blocks (3.3 V dc). See Figure 52 for the required components.
10 VGA_EXT_CAP External Capacitor for VGA3. See Figure 52 for the required components.
11 RX_OUT Receiver Output.
12 VCC_VGA3 Power Supply for VGA3 (3.3 V dc). See Figure 52 for the required components.
13 AUX_OUT Receiver Auxiliary Output.
14 PD3_IN Receive AGC Loop Input.
15 PD3_OUT/RSSI Third Power Detector Output.
16 VC_VGA_IF/CAP− Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
17 VC_VGA_RF/CAP+ Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 52 for the required components.
18 VCC_PD1 Power Supply for the First Power Detector (3.3 V dc). See Figure 52 for the required components.
19 PD1_OUT First Power Detector Output.
20 RFIN Radio Frequency Input. This pin is matched to 50 Ω.
22 AMP1 Single-Ended Output of Amplifier 1 (3.3 V dc). See Figure 52 for the required components.
23 VCC_AMP1 Power Supply for AMP1 (3.3 V dc). See Figure 52 for the required components.
24 FILTER1P RFVGA Input.
25 VCC_VGA1 Power Supply for the RFVGA (3.3 V dc). See Figure 52 for the required components.
26 VCC_VGA1_BALUN Power Supply for RFVGA Balun(3.3 V dc). See Figure 52 for the required components.
27 VCC_IRM Power Supply for the Image Reject Mixer (3.3 V dc). See Figure 52 for the required components.
28 IRM_I_P Positive In-Phase IF Output for the Image Reject Mixer.
29 IRM_I_N Negative In-Phase IF Output for the Image Reject Mixer.
30 VDD Power Supply for Logic Circuitry (3.3 V dc). See Figure 52 for the required components.
31 IRM_Q_P Positive Quadrature IF Output for the Image Reject Mixer.
32 IRM_Q_N Negative Quadrature IF Output for the Image Reject Mixer.
33 LOP Local Oscillator Input (Positive). This pin is ac-coupled and matched to 50 Ω.
HMC8100LP6JE Data Sheet
Rev. B | Page 8 of 27
34 LON Local Oscillator Input (Negative). This pin is ac-coupled and matched to 50 Ω.
35 SEN SPI Serial Enable.
36 SCLK SPI Clock Digital Input.
37
SDI
SPI Serial Data Input.
38 SDO SPI Serial Data Output.
39 RST SPI Reset. RESET must be held low (Logic 0) during power on. This is critical for proper programming and
reliable operation. Refer to the Theory of Operation section.
40 REF_CLK_P Filter Calibration Clock.
EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane.
Data Sheet HMC8100LP6JE
Rev. B | Page 9 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
EXTERNAL AGC CONFIGURATION
Lower sideband selected, maximum gain.
90
600.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
CONVE RSI ON GAI N (dB)
RF F RE QUENCY (GHz)
65
70
75
80
85
14MHz
28MHz
56MHz
112MHz
EXT
13867-003
Figure 3. Conversion Gain vs. RF Frequency
over Internal and External Filters
90
600.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
CONVE RSI ON GAI N (dB)
RF F RE QUENCY (GHz)
65
70
75
80
85
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
13867-004
Figure 4. Conversion Gain vs. RF Frequency at Various Local
Oscillator (LO) Powers, 56 MHz Filter
45
35
25
15
5
–5
–15
–253.3 0
CONVE RS ION G AIN (d B)
VC_VGA_RF (V) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-005
Figure 5. Conversion Gain vs. VC_VGA_RF at RF = 1 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
90
600.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
CONVERSION GAIN (dB)
RF FREQ UE NCY ( GHz)
65
70
75
80
85
+85°C
+25°C
–40°C
13867-006
Figure 6. Conversion Gain vs. RF Frequency over Temperature, 56 MHz Filter
90
600.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
CONVERSION GAIN (dB)
RF FREQ UE NCY ( GHz)
65
70
75
80
85
3.63V
3.30V
2.97V
13867-007
Figure 7. Conversion Gain vs. RF Frequency at Various VCCx, 56 MHz Filter
45
35
25
15
5
–5
–15
–253.3 0
CONVERSION GAIN (dB)
VC_VGA_RF ( V) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-008
Figure 8. Conversion Gain vs. VC_VGA_RF at RF = 2 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
HMC8100LP6JE Data Sheet
Rev. B | Page 10 of 27
Lower sideband selected, maximum gain.
45
35
25
15
5
–5
–15
–253.3 0
CONVERSION GAIN ( d B)
VC_VGA_RF (V ) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-009
Figure 9. Conversion Gain vs. VC_VGA_RF at RF = 4 GHz, 56 MHz Filter
(RF Input Power = −40 dBm, VC_VGA_IF = 0 V)
90
80
70
60
50
40
30
203.3 0
CONVERSION GAIN ( d B)
VC_VGA _IF (V) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-010
Figure 10. Conversion Gain vs. VC_VGA_IF at RF = 2 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
10
0
NO ISE FIGU R E (dB)
1
2
3
4
5
6
7
8
9
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
14MHz
28MHz
56MHz
112MHz
13867-011
Figure 11. Noise Figure vs. RF Frequency over Internal Filters
90
80
70
60
50
40
30
203.3 0
CONVERSION GAIN ( d B)
VC_VGA _IF (V) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-012
Figure 12. Conversion Gain vs. VC_VGA_IF at RF = 1 GHz, 56 MHz Filter
(VC_VGA_RF = 3.3 V)
90
80
70
60
50
40
30
203.3 0
CONVERSION GAIN ( d B)
VC_VGA _IF (V) 0.30.60.91.21.51.82.12.42.73.0
+85°C
+25°C
–40°C
13867-013
Figure 13. Conversion Gain vs. VC_VGA_IF at RF = 4 GHz, 56 MHz Filter,
(VC_VGA_RF = 3.3 V)
10
0
NO ISE FIGU R E (dB)
1
2
3
4
5
6
7
8
9
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
+85°C
+25°C
–40°C
13867-014
Figure 14. Noise Figure vs. RF Frequency over Temperature, 56 MHz Filter
Data Sheet HMC8100LP6JE
Rev. B | Page 11 of 27
Lower sideband selected, maximum gain.
10
0
NO ISE FIGU R E (dB)
1
2
3
4
5
6
7
8
9
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
13867-015
Figure 15. Noise Figure vs. RF Frequency at Various LO Powers, 56 MHz Filter
50
0
IM AG E REJE CT ION (dBc)
5
10
15
20
25
30
35
40
45
14MHz
28MHz
56MHz
112MHz
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
13867-016
Figure 16. Image Rejection vs. RF Frequency over Internal Filters
50
0
IM AG E REJE CT ION (dBc)
5
10
15
20
25
30
35
40
45
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
13867-017
Figure 17. Image Rejection vs. RF Frequency at Various LO Powers,
56 MHz Filter
10
0
NO ISE FIGU R E (dB)
1
2
3
4
5
6
7
8
9
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
3.63V
3.30V
2.97V
13867-018
Figure 18. Noise Figure vs. RF Frequency at Various VCCx, 56 MHz Filter
50
0
IM AG E REJE CT ION (dBc)
5
10
15
20
25
30
35
40
45
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
+85°C
+25°C
–40°C
13867-019
Figure 19. Image Rejection vs. RF Frequency over Temperature, 56 MHz Filter
50
0
IM AG E REJE CT ION (dBc)
5
10
15
20
25
30
35
40
45
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
RF F RE QUENCY (GHz)
3.63V
3.30V
2.97V
13867-020
Figure 20. Image vs. RF Frequency at Various VCCx, 56 MHz Filter
HMC8100LP6JE Data Sheet
Rev. B | Page 12 of 27
Lower sideband selected, maximum gain.
32
0
8
20
28
16
4
12
24
IP3 (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY ( G Hz )
14MHz
28MHz
56MHz
112MHz
13867-021
Figure 21. Output IP3 vs. RF Frequency over Internal Filters
32
0
8
20
28
16
4
12
24
IP3 (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY ( G Hz )
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
13867-022
Figure 22. Output IP3 vs. RF Frequency at Various LO Powers, 56 MHz Filter
0
–350.4 1.20.8 1.6 2.0 2.4 2.8 3.2 3.6 4.84.0 4.4
RETURN L OSS (dB)
RF FREQ U E NCY ( G Hz )
+85°C
+25°C
–40°C
–30
–25
–20
–15
–10
–5
13867-023
Figure 23. RF Return Loss vs. RF Frequency over Temperature (Optimize RF
Return Loss by Adjusting Capacitor C12, see Figure 52)
32
0
8
20
28
16
4
12
24
IP3 (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY ( G Hz )
+85°C
+25°C
–40°C
13867-024
Figure 24. Output IP3 vs. RF Frequency over Temperature, 56 MHz Filter
32
0
8
20
28
16
4
12
24
IP3 (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY ( G Hz )
3.63V
3.30V
2.97V
13867-025
Figure 25. Output IP3 vs. RF Frequency at Various VCCx, 56 MHz Filter
0
–350.4 1.20.8 1.6 2.0 2.4 2.8 3.2 3.6 4.84.0 4.4
RETURN L OSS (dB)
LO FREQUENCY (GHz)
+85°C
+25°C
–40°C
–30
–25
–20
–15
–10
–5
13867-026
Figure 26. LO Return Loss vs. LO Frequency over Temperature
Data Sheet HMC8100LP6JE
Rev. B | Page 13 of 27
Lower sideband selected, maximum gain.
00.100.05 0.15 0.20 0.25 0.30 0.35 0.500.40 0.45
IF FREQUENCY ( GHz)
0
–35
RETURN L OSS ( d B)
+85°C
+25°C
–40°C
–30
–25
–20
–15
–10
–5
13867-027
Figure 27. IF Return Loss vs. IF Frequency over Temperature
0
–80
–60
–30
–10
–40
–70
–50
–20
LEAKAGE (d Bm)
0.81.21.62.02.42.83.23.64.0
RF F RE QUENC Y ( G Hz)
RF TO IF LEAKAGE
RF TO (AMP 2_ P + AMP 2_N ) LE A KAGE
13867-028
Figure 28. RF Leakage vs. RF Frequency at IF Port with 56 MHz Filter and at
(AMP2_P + AMP2_N) Pins
20
10
0
–10
–20
–30
–40
–50
CONV E RS ION GAIN ( dB)
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13867-029
Figure 29. 14 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
0
–80
–60
–30
–10
–40
–70
–50
–20
LEAKAG E (dB m)
0.81.21.62.02.42.83.23.6 4.44.0
LO FREQUENCY (GHz)
LO TO RF LEAKAGE
LO TO IF LEAKAGE
13867-030
Figure 30. LO Leakage vs. LO Frequency at RF and IF Ports with 56 MHz Filter
0
–80
–60
–30
–10
–40
–70
–50
–20
LE AK AGE ( dBm)
0.81.21.62.02.42.83.23.64.0
LO FREQUENCY (GHz)
LO TO (AMP2_P + AMP2_N) LEAKAGE
13867-031
Figure 31. LO Leakage vs. LO Frequency at (AMP2_P + AMP2_N) Pins
20
10
0
–10
–20
–30
–40
–50
CONV E RS IO N GAIN (dB)
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY (GHz )
+85°C
+25°C
–40°C
13867-032
Figure 32. 28 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
HMC8100LP6JE Data Sheet
Rev. B | Page 14 of 27
Lower sideband selected, maximum gain.
20
10
0
–10
–20
–30
–40
–50
CONVERSION GAIN (dB)
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQ UE NCY (GHz)
+85°C
+25°C
–40°C
13867-033
Figure 33. 56 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
(RF Input Power = −30 dBm, Adjusted VC_VGA_IF and VC_VGA_RF to
Achieve 10 dB of Gain)
2.0
1.0
–45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10
PD3 OUTPUT VOLTAGE (V)
IF OUT PUT POWE R ( dBm)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9 +85°C
+25°C
–40°C
13867-034
Figure 34. PD3 Output Voltage vs. IF Power Output at RF = 1 GHz,
56 MHz Filter
5
2.0
1.0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
PD3 OUTPUT VOLTAGE (V)
IF O UTPUT POWER (dBm)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9 +85°C
+25°C
–40°C
13867-035
Figure 35. PD3 Output Voltage vs. IF Power Output at RF = 4 GHz,
56 MHz Filter
20
10
0
–10
–20
–30
–40
–50
CONVE RS I ON GAI N ( d B)
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
IF FREQUENCY ( GHz)
+85°C
+25°C
–40°C
13867-036
Figure 36. 112 MHz Internal Filter Response vs. IF Frequency at RF = 1 GHz
105
2.0
1.0
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
PD3 OUT P UT V O LTAG E (V )
IF OUTPUT POWER ( dBm)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9 +85°C
+25°C
–40°C
13867-037
Figure 37. PD3 Output Voltage vs. IF Power Output at RF = 2 GHz,
56 MHz Filter
15
5
P1dB (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY (GHz )
+85°C
+25°C
–40°C
6
7
8
9
10
11
12
13
14
13867-038
Figure 38. Output P1dB vs. RF Frequency over Temperature, 56 MHz Filter
Data Sheet HMC8100LP6JE
Rev. B | Page 15 of 27
Lower sideband selected, maximum gain.
15
5
P1dB (dBm)
0.81.21.62.02.42.83.23.64.0
RF FREQ U E NCY (GHz)
6
7
8
9
10
11
12
13
14
4
5
6
7
13867-039
Figure 39. Output P1dB vs. RF Frequency over IF Gain Limit, 56 MHz Filter
HMC8100LP6JE Data Sheet
Rev. B | Page 16 of 27
INTERNAL AGC CONFIGURATION
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
80
0
–70 –50 –35 –20–25 –10–65 –60 –55 –45 –40 –30 –15 –5 0
IM3 (dBc)
INPUT POWER (dBm)
10
20
30
40
50
60
70
+85°C
+25°C
–40°C
13867-040
Figure 40. IM3 vs. Input Power over Temperature, RF = 1 GHz
80
0
–70 –50 –35 –20–25 –10–65 –60 –55 –45 –40 –30 –15 –5 0
IM3 (dBc)
INPUT POWER (dBm)
10
20
30
40
50
60
70
+85°C
+25°C
–40°C
13867-041
Figure 41. IM3 vs. Input Power over Temperature, RF = 4 GHz
70
60
50
40
30
20
10
0
NOISE FIGURE (dB)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
13867-042
Figure 42. Noise Figure vs. Input Power over Temperature, RF = 2 GHz
80
0
–70 –50 –35 –20–25 –10–65 –60 –55 –45 –40 –30 –15 –5 0
IM3 (dBc)
INPUT POWER (dBm)
10
20
30
40
50
60
70
+85°C
+25°C
–40°C
13867-043
Figure 43. IM3 vs. Input Power over Temperature, RF = 2 GHz
70
60
50
40
30
20
10
0
NOISE FIGURE (dB)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
13867-044
Figure 44. Noise Figure vs. Input Power over Temperature, RF = 1 GHz
70
60
50
40
30
20
10
0
NOISE FIGURE (dB)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
13867-045
Figure 45. Noise Figure vs. Input Power over Temperature, RF = 4 GHz
Data Sheet HMC8100LP6JE
Rev. B | Page 17 of 27
POUT = −9 dBm per tone, lower sideband, and 56 MHz filter selected.
–
4
–18
OUTPUT P OWE R (dBm)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
–16
–14
–12
–10
–8
–6
13867-046
Figure 46. Output Power vs. Input Power over Temperature, RF = 1 GHz
–
4
–18
OUTPUT P OWE R (dBm)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
–16
–14
–12
–10
–8
–6
13867-047
Figure 47. Output Power vs. Input Power over Temperature, RF = 4 GHz
–
4
–18
OUTPUT P OWE R (dBm)
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT POWER (dBm)
+85°C
+25°C
–40°C
–16
–14
–12
–10
–8
–6
13867-048
Figure 48. Output Power vs. Input Power over Temperature, RF = 2 GHz
HMC8100LP6JE Data Sheet
Rev. B | Page 18 of 27
THEORY OF OPERATION
The HMC8100LP6JE is a highly integrated intermediate
frequency (IF) receiver chip that converts radio frequency (RF)
to a single-ended IF signal at its output. The internal active gain
circuit (AGC) of the HMC8100LP6JE is able to actively level the
output power at the IF output via SPI control. The gain control of
the HMC8100LP6JE can be controlled externally as an
alternative option via the VC_VGA_RF and VC_VGA_IF pins
with voltages ranging from 3.3 V (minimum attenuation) to 0 V
(maximum attenuation).
The HMC8100LP6JE utilizes an input low noise amplifier
(LNA) cascaded with a variable gain amplifier (VGA), which
can either be controlled by the internal AGC or external
voltages, that feeds the RF signals to an image reject mixer. The
local oscillator port can either be driven single ended through
LON or differentially through the combination of LON and
L O P.
The radio frequency is then converted to intermediate
frequencies, which can either feed off chip via baseband
differential outputs or feed on chip into a programmable band-
pass filter. It is recommended during IF mode operation that
the baseband outputs be unconnected. The programmable
band-pass filter on chip has four programmable bandwidths
(14 MHz, 28 MHz, 56MHz, and 112 MHz). The programmable
band-pass filter has the capability to adjust the center frequency.
From the factory, a filter calibration is conducted and the center
frequency of the filter is set to 140 MHz. This calibration can be
recalled via SPI control or the customer can adjust the center
frequency, but the calibration value must be stored off chip (see
the Register Array Assignments section). An external filter
option can be utilized to allow the customer to select other filter
bandwidths/responses that are not available on chip. The
external filter path coming from the image reject mixer feeds
into an amplifier that has differential outputs. The output of the
external filter can be fed back into the chip, which is then
connected to another amplifier.
A VGA follows immediately after the band-pass filter. Control
the IF VGA either by the AGC or external voltages. The output
of the variable gain amplifier is the output of the device.
The SPI RESET pin on the HMC8100LP6JE must be held low
(Logic 0) during power on. This is critical for proper
programming and reliable operation. Apply a RESET low before
the bias voltage is applied to the device or use a pull-down
resistor on the RESET pin.
REGISTER ARRAY ASSIGNMENTS AND SERIAL
INTERFACE
The register arrays for the HMC8100LP6JE are organized into
nine registers of 16 bits. Using the serial interface, the arrays are
written or read one row at a time, as shown in Figure 50 and
Figure 51. Figure 50 shows the sequence of signals on the enable
(SEN), CLK, and data (SDI) lines to write one 16-bit array of data
to a single register. The enable line goes low, the first of 24 data
bits is placed on the data line, and the data is sampled on the
rising edge of the clock. The data line should remain stable for
at least 2 ns after the rising edge of CLK. The device supports a
serial interface running up to 10 MHz, the interface is 3.3 V
CMOS logic.
A write operation requires 24 data bits and 24 clock pulses, as
shown in Figure 50. The 24 data bits contain the 3-bit chip
address, followed by the 5-bit register array number, and finally
the 16-bit register data. After the 24th clock pulses of the write
operation, the enable line returns high to load the register array
on the IC.
A read operation requires 24 data bits and 48 clock pulses, as
shown in Figure 51. For every register read operation you must
first write to Register 7. The data written should contain the
3-bit chip address, followed by the 5-bit register number for
Register 7, and finally the 5-bit number of the register to be
read. The remaining 11 bits should be logic zeroes. When the
read operation is initiated, the data is available on the data
output (SDO) pin. The output data bits are placed on the data
line during the rising edge of the clock.
Read Example
If reading Register 2, the following 24 bits should be written to
initiate the read operation.
00000000000 00010 00111 110
ZERO BITS (11 BITS)
REGISTER 7 ADDRESS (5 BITS)
REGISTER TO BE READ (5 BITS)
CHIP ADDRESS (3 BITS)
13867-049
Figure 49. Sample Bits to Initiate Read
Data Sheet HMC8100LP6JE
Rev. B | Page 19 of 27
WRITE DATA REGISTER
ADDRESS
CHIP
ADDRESS
13867-050
01 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SEN
CLK
SDI
124
LSB
MSB
MSB
LSB
MSB
LSB
24 CLOCK CYCLES
Figure 50. Timing Diagram, SPI Register Write
24 CLOCK CYCLES 24 CLOCK CYCLES
READ DATA
READ
REGISTER
ADDRESS
REG 7
ADDRESS
CHIP
ADDRESS
13867-051
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SEN
CLK
SDI
124
ALL ZEROS
LSB
MSB
MSB
LSB
MSB
LSB
124
0123456 78910 11 12 13 14 15
SDO
LSB
MSB
LSB
MSB
Figure 51. Timing Diagram, SPI Register Read
HMC8100LP6JE Data Sheet
Rev. B | Page 20 of 27
REGISTER DESCRIPTIONS
REGISTER ARRAY ASSIGNMENTS
In the Access columns (Table 6 through Table 14), R means read, W means write, and R/W means read/write.
Enable Bits
Table 6. Enable Register, (Address 0x01)
Bit No. Bit Name Description Reset Access
15
PD2_EN
Power Detector 2 enable
0x1
R/W
0 = disable
1 = enable
14 Factory diagnostics Logic 0 for normal operation 0x0 R/W
13 PD3_AMP1_EN Auxiliary output (Pin 13) enable 0x1 R/W
0 = disable
1 = enable
12 Reserved Logic 1 for normal operation 0x1 R/W
11 AMP1_EN LNA enable 0x1 R/W
0 = disable
1 = enable
10 RF_VGA_EN RF VGA enable 0x1 R/W
0 = disable
1 = enable
9 IRM_EN Image reject mixer enable 0x1 R/W
0 = disable
1 = enable
8 FIL2_EN Filter 2 enable 0x1 R/W
0 = disable
1 = enable
7 IF_VGA_EN Filter 2 enable 0x1 R/W
0 = disable
1 = enable
6 Factory diagnostics Logic 0 for normal operation 0x0 R/W
5 PD1_EN Power Detector 1 enable 0x1
0 = disable
1 = enable
4 PD3_EN Power Detector 3 enable 0x1 R/W
0 = disable
1 = enable
3 AGC_EN Available gain control (AGC) enable 0x1 R/W
0 = enable
1 = disable
2 AMP3_PDWN Amplifier 3 power-down 0x1 R/W
0 = enable
1 = disable
1 AMP2_PDWN Amplifier 2 power-down 0x1 R/W
0 = enable
1 = disable
0 IQ_BUF_EN IQ buffer enable 0x0 R/W
0 = disable
1 = enable
Data Sheet HMC8100LP6JE
Rev. B | Page 21 of 27
Image Reject and Band-Pass Filter Bits
Table 7. Image Reject and Band-Pass Filter Register, (Address 0x02)
Bit No. Bit Name Description Reset Access
15 IRM_IS Image sideband select 0x1 R/W
0 = lower sideband
1 = upper sideband
[14:13] FIL2_SEL Internal band-pass filter select 0x2 R/W
00 = 14 MHz
01 = 28 MHz
10 = 56 MHz
11 = 112 MHz
12 SEL_EXT_FIL Select external filter 0x0 R/W
0 = internal
1 = external
11 Reserved Not used 0x0 R/W
10 FIL2_CAL_OVR Override on-chip calibration and use 8-bit word from SPI 0x1 R/W
0 = use on-chip calibration word
1 = use FIL2_FREQ_SET word from SPI
9 FIL2_CAL_EN Enable filter center frequency calibration 0x0 R/W
0 = disable
1 = enable (transition from 0 to 1)
8 Reserved Not used 0x1 R/W
[7:0] FIL2_FREQ_SET Internal band-pass filter center frequency setting 0x85 R/W
Band-Pass Filter Bits: OTP and SPI
Table 8. Band-Pass Filter Register, (Address 0x03)
Bit No. Bit Name Description Reset Access
[15:12] Reserved Logic 1000 for normal operation 0x8 R/W
11
FIL_OPT_MUX_SEL
Override SPI FIL2_FRQ_SET and use 8-bit word from OTP
0x0
R/W
0 = select OTP setting
1 = select SPI setting
[10:0] Reserved Logic 110 1001 1111 for normal operation 0x69F R/W
AGC
Table 9. AGC Register, (Address 0x04)
Bit No.
Bit Name
Description
Reset
Access
[15:12] AGC_SELECT Active gain control (AGC) select 0x3 R/W
0x3 = internal AGC mode
0xC = external AGC mode
11 AGC_EXT_CAP_SEL Active gain control external capacitor select 0x0 R/W
0 = no external capacitor
1 = external capacitor
[10:8]
AGC_BW
AGC bandwidth
0x4
R/W
000 = 17 Hz
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz (recommended setting)
110 = 167 Hz
111 = 333 Hz
HMC8100LP6JE Data Sheet
Rev. B | Page 22 of 27
Bit No. Bit Name Description Reset Access
[7:6] VGA3_GAIN VGA 3 attentuation 0x0 R/W
00 = 0 dB (recommended setting)
01 = 5 dB
10 = 10 dB
11 = 15 dB
[5:0] POUT_CTRL Power output control 0x30 R/W
0x0 = −54 dBm
0x1 = −53 dBm
0x2 = …
0x3E = +8 dBm
0x3F = +9 dBm
AGC: IF Gain Limit Bits
Table 10. AGC Register, (Address 0x05)
Bit No. Bit Name Description Reset Access
[15:12] Reserved Not used 0xA R/W
[11:9] IF_GAIN_LIMIT IF gain limit 0x4 R/W
000 = 0 dB
001 = 6 dB
010 = 12 dB
011 = 18 dB
100 = 24 dB
101 = 30 dB
110 = 36 dB
111 = 42 dB
[8:0] Reserved Logic 1 0000 0100 for normal operation 0x104 R/W
Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency
Table 11. Band-Pass Filter Register, (Address 0x06)
Bit No. Bit Name Description Reset Access
[15:10] Reserved Not used 0x0 R
9 FIL2_CAL_OVFL FIL2 calibration overflow signal 0x1 R
8
FIL2_VCAL_END
FIL2 calibration end signal
0x1
R
[7:0] FL2_FC_CAL FIL2 8-bit word frequency setting, read only 0x85 R
Data Sheet HMC8100LP6JE
Rev. B | Page 23 of 27
AGC: Blocker Power Detector Bits
Table 12. AGC Register, (Address 0x12)
Bit No. Bit Name Description Reset Access
[15:8] Reserved Not used 0xF0 R/W
7 Reserved Not used 0x0 R/W
6 AGC_BLOCKER_MODE_EN AGC blocker mode enable 0x01 R/W
0 = off
1 = on
[5:3] AGC_BLOCKER_PD2_REF AGC blocker power detector reference level 0x3 R/W
000 = −4 dBm
001 = −2 dBm
010 = 0 dBm
011 = 2 dBm
100 = 4 dBm
101 = 6 dBm
110 = 8 dBm
111 = 10 dBm
[2:0] AGC_BLOCKER_PD2_LOOP_BW AGC blocker power detector loop bandwidth control 0x4 R/W
000 = 17 Hz
001 = 22 Hz
010 = 33 Hz
011 = 67 Hz
100 = 83 Hz
101 = 111 Hz
110 = 167 Hz
111 = 333 Hz
Phase I Bits
Table 13. Phase I Register, (Address 0x14)
Bit No. Bit Name Description Reset Access
[15:12] Reserved Not used 0xF R/W
[11:9] Reserved Not used 0x0 R/W
[8:0] I_PHASE_ADJ I phase adjust 0x0 R/W
Phase Q Bits
Table 14. Phase Q Register, (Address 0x15)
Bit No. Bit Name Description Reset Access
[15:12] Reserved Not used 0xF R/W
[11:9] Reserved Not used 0x0 R/W
[8:0] Q_PHASE_ADJ Q phase adjust 0x0 R/W
HMC8100LP6JE Data Sheet
Rev. B | Page 24 of 27
APPLICATIONS INFORMATION
During operation at P1dB, the IF gain limit of the
HMC8100LP6JE, as described in the Register Array
Assignments and Serial Interface section, needs to be limited by
the radio frequency (RF), as listed in Table 15. There is a
recommended IF gain limit setting and maximum allowed IF
gain limit setting that is to be used.
SCHEMATIC/TYPICAL APPLICATION CIRCUIT
Table 15. Recommended IF Gain Limit Settings by RF
Frequency
RF Frequency
(GHz)
Maximum
Setting
Recommended
Setting
0.8 to 1.8 5 4
1.8 to 2.8 6 5
2.8 to 4.0 7 6
Data Sheet HMC8100LP6JE
Rev. B | Page 25 of 27
EVALUATION PRINTED CIRCUIT BOARD (PCB)
C24
1UF
J5
10uF
C54 C27
10nF
C28
100PF
1:4
T1
2 - 800 MHz
MABA ES0061
2
5
3
1
4
R5
160
R6
160
C29
1UF
10uF
C55
C30
10nF
C31
100PF
C32
100PF
C33
10nF
10uF
C56
C34
10nF
R7
49.9
F1
3059
140MHz
21
C35
100PF
C36
10nF
10uF
C57
C37
100PF
C38
10nF
10uF
C58
L2
2.2UH
R8
75
C39
10NF
J6
J3
SS W-116-22-F-D-VS
9
8
7
6
5
4
3231
30
3
29
2827
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J7
J8
1:4
T2
2 - 800 MHz
MABA ES0061
2
5
3
1
4J9
C42
1UF
1:4
T3
MABA ES0061
2 - 800 MHz
2
5
3
1
4J10
C43
1UF
10uF
C44
C1
10nF
C2
100PF
C3
100PF
C4
10nF 10uF
C45
10uF
C46
C5
10nF
C6
100PF
F2
LFCN-5000
DC - 5000 MHz
3
1
C7
100PF
C8
10nF 10uF
C47
C9
5PF
L1
15NH
C11
100PF
C12
5PF
J4
C13
10nF
C15
100PF
C16
10nF 10uF
C49
C22
100PF
C23
10nF 10uF
C52
J11
TSM-103-01-L-SV
3
2
1
J12
TSM-103-01-L-SV
3
2
1
R11
4.99
DVDD
DVDD
VCC_AMP2
VCC_AMP2
VCC_BB
VCC_VGA3
VCC_IRM
VCC_BALUN
VCC_VGA0
VCC_AMP1
VCC_AMP1
VCC_PD1
PD1_OUT
VC_VGA_EXT01
PD3_OUT
VC_VGA_EXT23
C63
100PF
C64
10nF
10uF
C67
VCC_AMP3
10uF
C68
C65
10nF
C66
100PF
VCC_OTP
VCC_3P3V
VCC_OTP
J13
J14
J15
J16
J17
J18
RFIN
IFOUT
LON
LOP
BB OUT_Q
BB OUT_I
REF_CLK _N
VCC_3P3V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
U1
30
31
32
29
20
19
10
9
35
40
34
27
33
26
17
18
16
15
14
13
12
11
21
22
28
25
23
24
36
37
38
39
8
7
6
1
5
4
3
2AMP2P
AMP2N
VCC_FI LTE R
FILTER2P
DVDD
VCC_AMP3
GND1
VCC_BB
RST
SDO
SDI
SCLK
FILTER1P
VCC_AMP1
VCC_VGA1
IRM2_IN
AMP1
RX_OUT
Vcc_VGA3
Aux _out
PD3_in
PD3_out/RSSI
Vc _VG A_IF/Cap-
VCC_PD1
Vc _VG A_RF/ Cap+
VCC_VGA1_BALUN
LOP
VCC_IRM2
LON
REF_CLK _P
SEN
GND2
VG A_ext_cap
PD1_OUT
RFIN
IRM2_IP
IRM2_QN
IRM2_QP
VDD5V
GND
HMC8100LP6JE
R15
49.9
VC_VGA_EXT01
VC_VGA_EXT23
C69
10nF
F3
6 2
RBP-140+
130-150HMz
49.9
R16
J19
9
11
1
3
5
7
2
4
6
8
10
12
87759-1250
87759-1250
12
10
8
6
4
2
7
5
3
1
11
9
J20 VCC_AMP2
VCC_AMP1
VCC_PD1
DVDD
VCC_AMP3
VCC_VGA0
C70
1NF
DEPOP
NC
VCC_BB
VCC_VGA3
NC
VCC_BALUN
VCC_IRM
PD1_OUT
NC
PD3_OUT
NC
13867-052
Figure 52. PCB Schematic/Typical Applications Circuit
HMC8100LP6JE Data Sheet
Rev. B | Page 26 of 27
13867-053
Figure 53. Evaluation PCB
Data Sheet HMC8100LP6JE
Rev. B | Page 27 of 27
OUTLINE DIMENSIONS
4.60
4.50 SQ
4.40
0.95
0.90
0.85
TOP VIEW BOTTOM VIEW
PKG-000000
0.45
0.40
0.35
SEATING
PLANE
0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO-220-VJJD-5.
6.10
6.00 SQ
5.90
04-20-2016-A
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
BSC
0.004
BSC
4
0
1
11
10
20
21
30
3
1
EXPOSED
PAD
SIDE VIEW
PIN 1
INDIC AT OR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
0.011
SQ
Figure 54. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.90 mm Package Height
(CP-40-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature
Range
MSL
Rating3 Package Description
Package
Option
Package
Marking4
HMC8100LP6JE
−40°C to +85°C
MSL3
40-Lead Lead Frame Chip Scale Package [LFCSP]
CP-40-22
XXXX
H8100
HMC8100LP6JETR −40°C to +85°C MSL3 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-22
XXXX
H8100
EK1HMC8100LP6J Evaluation Kit
1 All models are RoHS compliant.
2 The HMC8100LP6JE and HMC8100LP6JETR lead finishes are NiPdAu.
3 See the Absolute Maximum Ratings section.
4 XXXX is the 4-digit lot number.
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D13867-0-9/17(B)