MCU
TMP103A TMP103B TMP103C
SCL SCL SCL
SDA SDA SDA
Out
IO
V+V+
TMP103
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Low-Power, Digital Temperature Sensor
with Two-Wire Interface in WCSP
Check for Samples: TMP103
1FEATURES DESCRIPTION
The TMP103 is a digital output temperature sensor in
234Multiple Device Access (MDA): a four-ball wafer chip-scale package (WCSP). The
Global Read/Write Operations TMP103 is capable of reading temperatures to a
I2C-/ SMBus-Compatible Interface resolution of 1°C.
Resolution: 8 Bits The TMP103 features a two-wire interface that is
Accuracy: ±1°C Typ (10°C to +100°C) compatible with both I2C and SMBus interfaces. In
addition, the interface supports multiple device
Low Quiescent Current: access (MDA) commands that allow the master to
3μA Active IQat 0.25Hz communicate with multiple devices on the bus
1μA Shutdown simultaneously, eliminating the need to send
individual commands to each TMP103 on the bus.
Supply Range: 1.4V to 3.6V
Digital Output Up to eight TMP103s can be tied together in parallel
and easily read by the host. The TMP103 is
Package: 4-Ball WCSP (DSBGA) especially ideal for space-constrained,
power-sensitive applications with multiple
APPLICATIONS temperature measurement zones that must be
Handsets monitored.
Notebooks The TMP103 is specified for operation over a
temperature range of 40°C to +125°C.
TYPICAL APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SMBus is a trademark of Intel.
3I2C is a trademark of NXP Semiconductors.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMP103
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PACKAGE PACKAGE ORDERING
PRODUCT ADDRESS PACKAGE-LEAD DESIGNATOR MARKING NUMBER
TMP103AYFFR
TMP103A 1110000 DSBGA-4 YFF TA TMP103AYFFT
TMP103BYFFR
TMP103B 1110001 DSBGA-4 YFF TB TMP103BYFFT
TMP103CYFFR
TMP103C 1110010 DSBGA-4 YFF TC TMP103CYFFT
TMP103DYFFR
TMP103D 1110011 DSBGA-4 YFF TD TMP103DYFFT
TMP103EYFFR
TMP103E 1110100 DSBGA-4 YFF TE TMP103EYFFT
TMP103FYFFR
TMP103F 1110101 DSBGA-4 YFF TF TMP103FYFFT
TMP103GYFFR
TMP103G 1110110 DSBGA-4 YFF TG TMP103GYFFT
TMP103HYFFR
TMP103H 1110111 DSBGA-4 YFF TH TMP103HYFFT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device prodict folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
TMP103 UNIT
Supply Voltage 3.6 V
Input Voltage(2) 0.3 to (V+) + 0.3 V
Operating Temperature 55 to +150 °C
Storage Temperature 60 to +150 °C
Junction Temperature +150 °C
Human Body Model (HBM) 2000 V
ESD Rating Charged Device Model (CDM) 1000 V
Machine Model (MM) 200 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input voltage rating applies to all TMP103 input voltages.
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THERMAL INFORMATION TMP103
THERMAL METRIC(1) YFF UNITS
4
θJA Junction-to-ambient thermal resistance 160
θJCtop Junction-to-case (top) thermal resistance 75
θJB Junction-to-board thermal resistance 76 °C/W
ψJT Junction-to-top characterization parameter 3
ψJB Junction-to-board characterization parameter 74
θJCbot Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
At TA= +25°C and V+ = +1.4V to +3.6V, unless otherwise noted. TMP103
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE INPUT
Range 40 +125 °C
10°C to +100°C, V+ = 1.8V 0 ±2°C
Accuracy (Temperature Error) 40°C to +125°C, V+ = 1.8V ±1±3°C
vs Supply ±0.2 ±0.5 °C/V
Resolution 1.0 °C
DIGITAL INPUT/OUTPUT
VIH 0.7 (V+) V+ V
Input Logic Levels VIL 0.5 0.3 (V+) V
Input Current IIN 0<VIN <(V+) + 0.3V 1 μA
V+ >2V, IOL = 2mA 0 0.4 V
Output Logic Levels VOL SDA V+ <2V, IOL = 2mA 0 0.2 (V+) V
Resolution 8 Bit
Conversion Time 26 35 ms
CR1 = 0, CR0 = 0 (default) 0.25 Conv/s
CR1 = 0, CR0 = 1 1 Conv/s
Conversion Modes CR1 = 1, CR0 = 0 4 Conv/s
CR1 = 1, CR0 = 1 8 Conv/s
Timeout Time 30 40 ms
POWER SUPPLY
Operating Supply Range +1.4 +3.6 V
Serial Bus Inactive, CR1 = 0, CR0 = 0 (default), V+ = 1.8V 1.5 3 μA
Quiescent Current IQSerial Bus Active, SCL Frequency = 400kHz 15 μA
Serial Bus Active, SCL Frequency = 3.4MHz 85 μA
Serial Bus Inactive, V+ = 1.8V 0.5 1 μA
Shutdown Current ISD Serial Bus Active, SCL Frequency = 400kHz 10 μA
Serial Bus Active, SCL Frequency = 3.4MHz 80 μA
TEMPERATURE
Specified Range 40 +125 °C
Operating Range 55 +150 °C
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SDA
B2
A2
B1
A1
SCL
GND V+
TMP103
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PIN CONFIGURATION
YFF PACKAGE
WCSP-4 (DSBGA-4)
(TOP VIEW)
PIN DESCRIPTIONS
PIN
NO. NAME DESCRIPTION
A1 V+ Supply voltage
A2 GND Ground
B1 SDA Input/output data pin
B2 SCL Input clock pin
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10
9
8
7
6
5
4
3
2
1
0
Temperature( C)°
-60 -40 0 40 140 160
I (mA)
SD
3.6VSupply
1.4VSupply
-20 20 60 80 100 120
16
14
12
10
8
6
4
2
0
Temperature( C)°
-60 -20 40 60 160
IQ(mA)
-40 0 20 80 100 120 140
3.6VSupply
1.8VSupply
1.4VSupply
40
38
36
34
32
30
28
26
24
22
20
Temperature( C)°
-60 -20 40 60 140 160
ConversionTime(ms)
3.6VSupply
1.4VSupply
-40 200 80 100 120
100
90
80
70
60
50
40
30
20
10
0
BusFrequency(Hz)
1k 10k 100k 1M 10M
I ( A)m
Q
- °55 C
+25 C°
+125 C°
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
Temperature( C)°
-60 -40 40 60 140 160
TemperatureError( C)°
-20 200 80 100 120
TMP103
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TYPICAL CHARACTERISTICS
At TA= +25°C and V+ = 1.8V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
(0.25 Conversions per Second) SHUTDOWN CURRENT vs TEMPERATURE
Figure 1. Figure 2.
QUIESCENT CURRENT vs BUS FREQUENCY
CONVERSION TIME vs TEMPERATURE (Temperature at 3.3V Supply)
Figure 3. Figure 4.
TEMPERATURE ERROR vs TEMPERATURE
Figure 5.
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I/O
Control
Interface
SCL
SDA
Temperature
Register
Configuration
Register
TLOW
Register
THIGH
Register
Pointer
Register
TMP103
0.01mF
V+
GND
2
5
1
SCL
6
SDA
To
Two-Wire
Controller
TMP103
SBOS545A FEBRUARY 2011REVISED MARCH 2011
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APPLICATION INFORMATION
GENERAL DESCRIPTION To maintain accuracy in applications that require air
or surface temperature measurement, care should be
The TMP103 is a digital output temperature sensor in taken to isolate the package from ambient air
a wafer chip-scale package (WCSP) that is optimal temperature.
for thermal management and thermal profiling. The
TMP103 includes a two-wire interface that is POINTER REGISTER
compatible with both I2C and SMBus interfaces. In
addition, the TMP103 has the capability of executing Figure 7 shows the internal register structure of the
multiple device access (MDA) commands that allow TMP103. The 8-bit Pointer Register of the device is
multiple TMP103s to respond to a single global bus used to address a given data register. The Pointer
command. MDA commands reduce communication Register uses the two LSBs to identify which of the
time and power in a bus that contains multiple data registers should respond to a read or write
TMP103 devices. The TMP103 is specified over a command. Table 1 identifies the bits of the Pointer
temperature range of 40ºC to +125 ºC. Register byte. During a write command, P2 through
P7 must always be '0'. Table 2 describes the pointer
The TMP103 serial interface is designed to support address of the registers available in the TMP103.
up to eight TMP103 devices on a single bus. The Power-up reset value of P1/P0 is '00'. By default, the
TMP103 is offered with eight internal interface TMP103 reads the temperature on power-up.
addresses. Each unique address option can be used
as a location or temperature zone designator. The
TMP103 responds to standard I2C/SMBus slave
protocols that allow the internal registers to be written
to or read from on an individual basis. The TMP103
also responds to MDA commands that allow all the
devices on the bus to be written to or read from,
without having to send the individual address and
commands to each device.
Pull-up resistors are required on SCL and SDA. A
0.01μF bypass capacitor is also recommended, as
shown in Figure 6.
Figure 7. Internal Register Structure
Table 1. Pointer Register Byte
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits
Table 2. Pointer Addresses
NOTE: SCL and SDA pins require pull-up resistors.
P1 P0 REGISTER
Figure 6. Typical Connections 0 0 Temperature Register (Read Only)
0 1 Configuration Register (Read/Write)
The temperature sensor in the TMP103 is the chip
itself. Thermal paths run through the package bumps 1 0 TLOW Register (Read/Write)
as well as the package. The lower thermal resistance 1 1 THIGH Register (Read/Write)
of metal causes the bumps to provide the primary
thermal path.
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Table 3. Temperature Register
TEMPERATURE REGISTER
D7 D6 D5 D4 D3 D2 D1 D0
The Temperature Register of the TMP103 is T7 T6 T5 T4 T3 T2 T1 T0
configured as an eight-bit, read-only register that
stores the output of the most recent conversion. A Negative numbers are represented in binary twos
single byte must be read to obtain data, and is complement format. Following power-up or reset, the
described in Table 3. The data format for temperature Temperature Register reads 0°C until the first
is summarized in Table 4. One LSB equals 1°C. conversion is complete.
Table 4. 8-Bit Temperature Data Format(1)
TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX
128 0111 1111 7F
127 0111 1111 7F
100 0110 0100 64
80 0101 0000 50
75 0100 1011 4B
50 0011 0010 32
25 0001 1001 19
0 0000 0000 00
1 1111 1111 FF
25 1110 0111 E7
55 1100 1001 C9
(1) The resolution for the ADC is 1°C/count, where count is equal to the digital output of the ADC.
For positive temperatures (for example, +50°C):
Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary
code, left-justified format. Denote a positive number with MSB = '0'.
Example: (+50°C)/(1°C/count) = 50 = 32h = 0011 0010
For negative temperatures (for example, 25°C):
Generate the twos complement of a negative number by complementing the absolute value binary number
and adding 1. Denote a negative number with MSB = '1'.
Example: (|25°C|)/(1°C/count) = 25 = 19h = 0001 1001
Twos complement format: 1110 0110 + 1 = 1110 0111
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Measured
Temperature
THIGH
TLOW
FHBit
(TransparentMode)
Read Read
Time
Read
FLBit
(TransparentMode)
FHBit
(LatchMode)
FLBit
(LatchMode)
TMP103
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CONFIGURATION REGISTER The latch bit (LC) in the configuration register is used
to latch the value of the flag bits (FH and FL) until the
The Configuration Register is an eight-bit read/write master issues a read command to the configuration
register used to store bits that control the operational register. The flag bits are set to '0' if a read command
modes of the temperature sensor. Read/write is received by the TMP103, or if LC = '0' and the
operations are performed MSB first. The format and temperature is within the temperature limits. The
power-up/reset value of the Configuration Register is power-on default values for these bits are FH = '0',
shown in Table 5. All registers are updated at the end FL = '0', and LC = '0'.
of the data byte. CONVERSION RATE
Table 5. Configuration and Power-Up/Reset
Format The conversion rate bits, CR1 and CR0 located in the
Configuration Register, configure the TMP103 for
D7 D6 D5 D4 D3 D2 D1 D0 conversion rates of 8Hz, 4Hz, 1Hz, or
ID CR1 CR0 FH FL LC M1 M0 0.25Hz (default). The TMP103 has a typical
00000010 conversion time of 26ms. To achieve different
conversion rates, the TMP103 performs a single
conversion and then powers down and waits for the
TEMPERATURE WATCHDOG FUNCTION appropriate delay set by CR1 and CR0. Table 6
The TMP103 contains a watchdog function that shows the settings for CR1 and CR0.
monitors device temperature and compares the result
to the values stored in the temperature limit registers Table 6. Conversion Rate Settings
(THIGH and TLOW) in order to determine if the device CR1 CR0 CONVERSION RATE
temperature is within these set limits. If the
temperature of the TMP103 becomes greater than 0 0 0.25Hz (default)
the value in the THIGH register, then the flag-high bit 0 1 1Hz
(FH) in the configuration register is set to '1'. If the 1 0 4Hz
temperature falls below value in the TLOW register, 1 1 8Hz
then the flag-low bit (FL) is set to '1'. If both flag bits
remain '0', then the temperature is within the After power-up or general-call reset, the TMP103
temperature window set by the temperature limit immediately starts a conversion, as shown in
registers, as shown in Figure 8.Figure 9. The first result is available after 26ms
(typical). The active quiescent current during
conversion is 40μA (typical at +27°C, V+ = 1.8V). The
quiescent current during delay is 1.0μA (typical at
+27°C, V+ = 1.8V).
(1) Delay is set by CR1 and CR0.
Figure 9. Conversion Start
SHUTDOWN MODE (M1 = '0', M0 = '0')
Shutdown mode saves maximum power by shutting
down all device circuitry other than the serial
interface, reducing current consumption to typically
less than 0.5μA. Shutdown mode is enabled when
Figure 8. Temperature Flag Functional Diagram bits M1 and M0 (in the Configuration Register) = '00'.
The device shuts down when the current conversion
is completed.
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Table 7. THIGH Register
ONE-SHOT (M1 = '0', M0 = '1')
D7 D6 D5 D4 D3 D2 D1 D0
The TMP103 features a One-Shot Temperature H7 H6 H5 H4 H3 H2 H1 H0
Measurement mode. When the device is in Shutdown
mode, writing a '01' to bits M1 and M0 starts a single
temperature conversion. During the conversion, bits Table 8. TLOW Register
M1 and M0 read '01'. The device returns to the D7 D6 D5 D4 D3 D2 D1 D0
shutdown state at the completion of the single L7 L6 L5 L4 L3 L2 L1 L0
conversion. After the conversion, bits M1 and M0
read '00'. This feature is useful for reducing power
consumption in the TMP103 when continuous BUS OVERVIEW
temperature monitoring is not required. The device that initiates the transfer is called a
As a result of the short conversion time, the TMP103 master, and the devices controlled by the master are
can achieve a higher conversion rate. A single slaves. The bus must be controlled by a master
conversion typically takes 26ms and a read can take device that generates the serial clock (SCL), controls
place in less than 20μs. When using One-Shot mode, the bus access, and generates the START and STOP
30 or more conversions per second are possible. conditions.
To address a specific device, a START condition is
CONTINUOUS CONVERSION MODE (M1 = '1')initiated, indicated by pulling the data line (SDA) from
When the TMP103 is in Continuous Conversion mode a high to low logic level while SCL is high. All slaves
(M1 = '1'), a single conversion is performed at a rate on the bus shift in the slave address byte on the
determined by the conversion rate bits, CR1 and CR0 rising edge of the clock, with the last bit indicating
(in the Configuration Register). The TMP103 whether a read or write operation is intended. During
performs a single conversion and then powers down the ninth clock pulse, the slave being addressed
and waits for the appropriate delay set by CR1 and responds to the master by generating an
CR0. See Table 6 for CR1 and CR0 settings. Acknowledge and pulling SDA low.
Data transfer is then initiated and sent over eight
TEMPERATURE LIMIT REGISTERS clock pulses followed by an Acknowledge Bit. During
The THIGH and TLOW registers are used to store the data transfer, SDA must remain stable while SCL is
temperature limit thresholds for the TMP103 high, because any change in SDA while SCL is high
watchdog function. At the end of each temperature is interpreted as a START or STOP signal.
measurement, the TMP103 compares the Once all data have been transferred, the master
temperature results to each of these limits. If the generates a STOP condition indicated by pulling SDA
temperature result is greater than the THIGH limit, then from low to high, while SCL is high.
the FH bit in the configuration register is set to '1'. If
the temperature result is less than the TLOW limit, then SERIAL INTERFACE
the FL bit in the configuration register is set to '1'; see
Figure 8.The TMP103 operates as a slave device only on the
two-wire bus and SMBus. Connections to the bus are
Table 7 and Table 8 describe the format for the THIGH made via the open-drain I/O lines SDA and SCL. The
and TLOW registers. Power-up reset values for THIGH SDA and SCL pins feature integrated spike
and TLOW are: THIGH = +60°C and TLOW =10°C. The suppression filters and Schmitt triggers to minimize
format of the data for THIGH and TLOW is the same as the effects of input spikes and bus noise. The
for the Temperature Register. TMP103 supports the transmission protocol for both
fast (1kHz to 400kHz) and high-speed (1kHz to
3.4MHz) modes. All data bytes are transmitted MSB
first.
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SERIAL BUS ADDRESS SLAVE MODE OPERATIONS
To communicate with the TMP103, the master must The TMP103 can operate as a slave receiver or slave
first address slave devices via a slave address byte. transmitter. As a slave device, the TMP103 never
The slave address byte consists of seven address drives the SCL line.
bits, and a direction bit that indicates the intent of
executing a read or write operation. Slave Receiver Mode
The TMP103 is available in eight versions, each with The first byte transmitted by the master is the slave
a different slave address, as shown in Table 9. These address, with the R/W bit low. The TMP103 then
addresses can be used as either a location or a acknowledges reception of a valid address. The next
temperature zone designator. byte transmitted by the master is the Pointer
Register. The TMP103 then acknowledges reception
Table 9. Device Slave Addresses of the Pointer Register byte. The next byte is written
to the register addressed by the Pointer Register. The
TWO-WIRE TEMPERATURE
PRODUCT TMP103 acknowledges reception of the data byte.
ADDRESS ZONE The master can terminate data transfer by generating
TMP103A 1110000 Zone1 a START or STOP condition.
TMP103B 1110001 Zone2
TMP103C 1110010 Zone3 Slave Transmitter Mode
TMP103D 1110011 Zone4 The first byte transmitted by the master is the slave
TMP103E 1110100 Zone5 address, with the R/W bit high. The slave
TMP103F 1110101 Zone6 acknowledges reception of a valid slave address. The
next byte is transmitted by the slave of the register
TMP103G 1110110 Zone7 indicated by the Pointer Register. The master
TMP103H 1110111 Zone8 acknowledges reception of the data byte. The master
can terminate data transfer by generating a
WRITING/READING OPERATION Not-Acknowledge on reception of the data byte, or
generating a START or STOP condition.
Accessing a particular register on the TMP103 is
accomplished by writing the appropriate value to the GENERAL CALL
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte The TMP103 responds to a two-wire General Call
with the R/W bit low. Every write operation to the address (0000000) if the eighth bit is '0'. The device
TMP103 requires a value for the Pointer Register acknowledges the General Call address and
(see Figure 12). responds to commands in the second byte. If the
second byte is 00000110, the TMP103 internal
When reading from the TMP103, the last value stored registers are reset to power-up values. The TMP103
in the Pointer Register by a write operation is used to does not support the General Address acquire
determine which register is read by a read operation. command.
To change the register pointer for a read operation, a
new value must be written to the Pointer Register. HIGH-SPEED (Hs) MODE
This action is accomplished by issuing a slave
address byte with the R/W bit low, followed by the In order for the two-wire bus to operate at frequencies
Pointer Register byte. No additional data are above 400kHz, the master device must issue an
required. The master can then generate a START Hs-mode master code (00001xxx) as the first byte
condition and send the slave address byte with the after a START condition to switch the bus to
R/W bit high to initiate the read command. See high-speed operation. The TMP103 does not
Figure 13 for details of this sequence. If repeated acknowledge this byte, but switches its input filters on
reads from the same register are desired, it is not SDA and SCL and its output filters on SDA to operate
necessary to continually send the Pointer Register in Hs-mode, allowing transfers at up to 3.4MHz. After
bytes; the TMP103 remembers the Pointer Register the Hs-mode master code has been issued, the
value until it is changed by the next write operation, master transmits a START condition followed by a
or the TMP103 is reset. two-wire slave address to initiate a data transfer
operation. The bus continues to operate in Hs-mode
until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP103 switches
the input and output filters back to the default
fast-mode operation.
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SCL SDA
GND V+
CF10nF³
RF5k£ W
SupplyVoltage
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TIMEOUT FUNCTION The TMP103A sends data on the first byte and the
TMP103B sends data on the second byte. The
The TMP103 resets the serial interface if SCL is held master must issue an acknowledge for each byte
low for 30ms (typ). The TMP103 releases the bus if it read in order to read all of the TMP103 devices on
is pulled low and waits for a START condition. To the bus; see Figure 15. If the master does not
avoid activating the timeout function, it is necessary acknowledge each byte of data, the TMP103s stop
to maintain a communication speed of at least 1kHz sending subsequent data for any remaining devices.
for SCL operating frequency. Up to eight TMP103 devices can be on the same bus
and respond to MDA commands; see Table 9.
MULTIPLE DEVICE ACCESS NOTE: If the bus contains an incomplete sequence of
The TMP103 supports Multiple Device Access TMP103 device addresses, the master must transmit
(MDA), which allows the master to communicate with all required dummy bytes for the missing device
multiple TMP103 devices on the same bus interface address to allow for normal MDA read operation. For
with one interface transaction. MDA commands example, if the TMP103A, TMP103B, and TMP103D
consist of an MDA read address (00000001) and an devices are on the bus, the master must transmit an
MDA write address (00000000). The device MDA read address followed by four bytes and four
acknowledges the MDA address and responds to the acknowledges in order to complete the MDA read
command accordingly. In order for MDA to function transaction.
correctly, different product versions of the TMP103
must be used in the system; see Table 9.NOISE
Multiple Device Access Write The TMP103 is a very low-power device and
The master transmits an MDA write address followed generates very low noise on the supply bus. Applying
by the pointer address of the register to be accessed; an RC filter to the V+ pin of the TMP103 can further
see Table 2. Following the pointer, all of the TMP103 reduce any noise the TMP103 might propagate to
devices on the bus acknowledge and wait for the next other components. RFin Figure 10 should be less
byte of data to be written to the addressed registers. than 5kand CFshould be greater than 10nF.
When the data byte is received by the TMP103
devices, they store and acknowledge the transmitted
byte. The TMP103s store the same data on all
devices on the bus in one transaction; see Figure 14.
Multiple Device Access Read
Note that before an MDA read transaction can begin,
the master must first send an MDA write transaction
in order to set the appropriate pointer address of the
register to be accessed, as stated in the previous
section. The master can then transmit an MDA read
address followed by a read byte for each TMP103
used on the bus. For example, if a TMP103A and
TMP103B are used on the same bus and an MDA
read address is sent, the address must be followed Figure 10. Noise Reduction
by two bytes of data and two master acknowledges.
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SCL
SDA
t(LOW) tRtFt(HDSTA)
t(HDSTA)
t(HDDAT)
t(BUF)
t(SUDAT)
t(HIGH) t(SUSTA) t(SUSTO)
P S S P
TMP103
SBOS545A FEBRUARY 2011REVISED MARCH 2011
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TIMING DIAGRAMS Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The TMP103 is two-wire and SMBus compatible. limited and is determined by the master device.
Figure 11 to Figure 15 describe the various
operations on the TMP103. Parameters for Figure 11 Acknowledge: Each receiving device, when
are defined in Table 10. Bus definitions are: addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
Bus Idle: Both SDA and SCL lines remain high. SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
Start Data Transfer: A change in the state of the period of the Acknowledge clock pulse. Setup and
SDA line, from high to low, while the SCL line is high, hold times must be taken into account. On a master
defines a START condition. Each data transfer is receive, the termination of the data transfer can be
initiated with a START condition. signaled by the master generating a
Stop Data Transfer: A change in the state of the Not-Acknowledge ('1') on the last byte that has been
SDA line from low to high while the SCL line is high transmitted by the slave.
defines a STOP condition. Each data transfer is
terminated with a repeated START or STOP
condition.
NOTE: P = STOP, S = START.
Figure 11. Two-Wire Timing Diagram
Table 10. Timing Diagram Definitions
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNIT
f(SCL) SCL Operating Frequency, VS>1.7V 0.001 0.4 0.001 3.4 MHz
f(SCL) SCL Operating Frequency, VS<1.7V 0.001 0.4 0.001 2.75 MHz
t(BUF) Bus Free Time Between STOP and START Condition 600 160 ns
Hold time after repeated START condition.
t(HDSTA) 100 100 ns
After this period, the first clock is generated.
t(SUSTA) Repeated START Condition Setup Time 100 100 ns
t(SUSTO) STOP Condition Setup Time 100 100 ns
t(HDDAT) Data Hold Time 0 0 ns
t(SUDAT) Data Setup Time 100 10 ns
t(LOW) SCL Clock Low Period, VS>1.7V 1300 160 ns
t(LOW) SCL Clock Low Period, VS<1.7V 1300 200 ns
t(HIGH) SCL Clock High Period 600 60 ns
tFClock/Data Fall Time 300 ns
tRClock/Data Rise Time 300 160 ns
tRClock/Data Rise Time for SCLK 100kHz 1000 ns
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Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
TMP103
ACKBy
TMP103
1 9 1
Frame3DataByte
ACKBy
TMP103
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
1 1 0 A2(1) A1(1) A0(1) R/W 0 0 0 0 0 0 P1 P0 ¼
¼
StopBy
Master
Frame1Two-WireSlaveAddressByte Frame2PointerRegisterByte
1
StartBy
Master
ACKBy
TMP103
ACKBy
TMP103
Frame3Two-WireSlaveAddressByte Frame4DataByteReadRegister
StartBy
Master
ACKBy
TMP103
ACKBy
Master
From
TMP103
1 9 1 9
1 9 1 9
SDA
SCL
1 1 0 R/W 0 0 0 0 0 0 P1 P0
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
1 1 1 0
A2(1) A1(1) A0(1)
A2(1) A1(1) A0(1) R/W D7 D6 D5 D4 D3 D2 D1 D0
StopBy
Master
StopBy
Master
TMP103
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SBOS545A FEBRUARY 2011REVISED MARCH 2011
(1) The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.
Figure 12. Two-Wire Timing Diagram for Write Word Format
(1) The value of A0, A1, and A2 are determined by the TMP103 version; see Table 9.
Figure 13. Two-Wire Timing Diagram for Read Word Format
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Frame1Two-WireMDAWriteAddressByte Frame2PointerRegisterByte
0
StartBy
Master
ACKBy
TMP103(1)
ACKBy
TMP103(1)
1 9 1
Frame3DataByte
ACKBy
TMP103(1)
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0 0 0 00 0 R/W 0 0 0 0 0 0 P1 P0 ¼
¼
StopBy
Master
TMP103
SBOS545A FEBRUARY 2011REVISED MARCH 2011
www.ti.com
(1) All TMP103 devices on the bus acknowledge the byte.
Figure 14. Two-Wire Timing Diagram MDA Write Word Format
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Frame1Two-WireMDAWriteAddressByte Frame2PointerRegisterByte
0
StartBy
Master
ACKBy
TMP103(1)
ACKBy
TMP103(1)
Frame3Two-WireMDAReadAddressByte Frame4DataByteReadRegister
StartBy
Master
ACKBy
TMP103(1)
ACKBy
Master(2)
From
TMP103A(3)
1 9 1 9
1 9 1 9
SDA
SCL
0 0 0 R/W 0 0 0 0 0 0 P1 P0
¼
¼
¼
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
0 0 0 0
0 0 0
00 0 R/W D7 D6 D5 D4 D3 D2 D1 D0
Frame5DataByteReadRegister
StopBy
Master
ACKBy
Master(2)
From
TMP103B(3)
19
D7 D6 D5 D4 D3 D2 D1 D0
StopBy
Master
Frame6DataByteReadRegister
StopBy
Master
ACKBy
Master(2)
From
TMP103C(3)
19
D7 D6 D5 D4 D3 D2 D1 D0
TMP103
www.ti.com
SBOS545A FEBRUARY 2011REVISED MARCH 2011
(1) All TMP103 devices on the bus acknowledge the byte.
(2) The master must issue an acknowledge for each byte read in order to read all of the TMP103 devices on the bus.
(3) Three TMP103 devices used in this case; up to eight devices can be used (see Table 9).
Figure 15. Two-Wire Timing Diagram MDA Read Word Format Using Typical Application (Front Page)
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 15
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TMP103
SBOS545A FEBRUARY 2011REVISED MARCH 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2011) to Revision A Page
Changed Package-Lead from WCSP-4 to DSBGA-4 in Package/Ordering Information table ............................................. 2
16 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 9-Mar-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMP103AYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103AYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103BYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103BYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103CYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103CYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103DYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103DYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103EYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103EYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103FYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103FYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103GYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103GYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103HYFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TMP103HYFFT ACTIVE DSBGA YFF 4 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 9-Mar-2011
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TMP103AYFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103AYFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103BYFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103CYFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103DYFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103EYFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103GYFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
TMP103HYFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2012
Pack Materials-Page 1