8543BGLFT - IDT, Integrated Device Technology Inc

DATA SHEET

Low Skew, 1-to-4,

Differential-to-LVDS Fanout Buffer

ICS8543

General Description

The ICS8543 is a low skew, high performance 1-to-4

Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage

Differential Signaling (LVDS) the ICS8543 provides a low power, low

noise, solution for distributing clock signals over controlled

impedances of 100Ω. The ICS8543 has two selectable clock inputs.

The CLK, nCLK pair can accept most standard differential input

levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL

input levels. The clock enable is internally synchronized to eliminate

runt pulses on the outputs during asynchronous

assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the

ICS8543 ideal for those applications demanding well defined

performance and repeatability.

Features

•Four differential LVDS output pairs

•Selectable differential CLK, nCLK or LVPECL clock inputs

•CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

•PCLK, nPCLK pair can accept the following differential input

levels: LVPECL, CML, SSTL

•Maximum output frequency: 800MHz

•Translates any single-ended input signals to LVDS levels with

resistor bias on nCLK input

•Additive phase jitter, RMS: 0.164ps (typical)

•Output skew: 40ps (maximum)

•Part-to-part skew: 500ps (maximum)

•Propagation delay: 2.6ns (maximum)

•Full 3.3V supply mode

•0°C to 70°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

ICS8543

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm

package body

G Package

Top View

Pin Assignment

Block Diagram

nQ0

nQ1

nQ2

nQ3

CLK_EN

CLK

CLK_SEL

Pulldown

nCLK Pullup

Pullup

PCLK Pulldown

nPCLK Pullup

GND

nPCLK

PCLK

nCLK

CLK

CLK_SEL

CLK_EN

GND

VDD

nQ0

VDD

nQ1

nQ2

GND

nQ3

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 9, 13 GND Power Power supply ground.

2 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follows clock input. When

LOW, Qx outputs are forced low, nQx outputs are forced high.

LVCMOS / LVTTL interface levels.

3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK, nPCLK inputs.

When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.

4 CLK Input Pulldown Non-inverting differential clock input.

5 nCLK Input Pullup Inverting differential clock input.

6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.

7 nPCLK Input Pullup Inverting differential LVPECL clock input.

8 OE Input Pullup Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3].

LVCMOS/LVTTL interface levels.

10, 18 VDD Power Positive supply pins.

11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels.

14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels.

16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels.

19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs Outputs

OE CLK_EN CLK_SEL Selected Source Q[0:3] nQ[0:3]

0 X X Hi-Z Hi-Z

1 0 0 CLK, nCLK Disabled; Low Disabled; High

1 0 1 PCLK, nPCLK Disabled; Low Disabled; High

1 1 0 CLK, nCLK Enabled Enabled

1 1 1 PCLK, nPCLK Enabled Enabled

Inputs Outputs

Input to Output Mode PolarityCLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3]

0 1 LOW HIGH Differential to Differential Non-Inverting

1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

Enabled

Disabled

CLK_EN

CLK, PCLK

nCLK, nPCLK

Q0:Q3

nQ0:nQ3

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, IO

Continuos Current

Surge Current

10mA

15mA

Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 50 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 3.765 V

VIL Input Low Voltage 0.8 V

IIH Input High Current OE, CLK_EN VDD = VIN = 3.465V 5 µA

CLK_SEL VDD = VIN = 3.465V 150 µA

IIL Input Low Current OE, CLK_EN VDD = 3.465V, VIN = 0V -150 µA

CLK_SEL VDD = 3.465V, VIN = 0V -5 µA

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as VIH.

Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

NOTE 1: Common mode input voltage is defined as VIH.

Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current CLK VDD = VIN = 3.465V 150 µA

nCLK VDD = VIN = 3.465V 5 µA

IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA

nCLK VDD = 3.465V, VIN = 0V -150 µA

VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V

VCMR

Common Mode Input Voltage;

NOTE 1, 2 0.5 VDD – 0.85 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current PCLK VDD = VIN = 3.465V 150 µA

nPCLK VDD = VIN = 3.465V 5 µA

IIL Input Low Current PCLK VDD = 3.465V, VIN = 0V -5 µA

nPCLK VDD = 3.465V, VIN = 0V -150 µA

VPP Peak-to-Peak Voltage 0.3 1.0 V

VCMR

Common Mode Input Voltage;

NOTE 1 1.5 VDD V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage 200 280 360 mV

∆VOD VOD Magnitude Change 0 40 mV

VOS Offset Voltage 1.125 1.25 1.375 V

∆VOS VOS Magnitude Change 5 25 mV

IOz High Impedance Leakage -10 +10 µA

IOFF Power Off Leakage -20 ±1 +20 µA

IOSD Differential Output Short Circuit Current -3.5 -5 mA

IOS Output Short Circuit Current -3.5 -5 mA

VOH Output Voltage High 1.34 1.6 V

VOL Output Voltage Low 0.9 1.06 V

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

AC Electrical Characteristics

Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: All parameters measured at 500MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output

cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Maximum Output Frequency 800 MHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 800MHz 1.7 2.6 ns

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

153.6MHz, Integration Range:

12kHz – 20MHz 0.164 ps

tsk(o) Output Skew; NOTE 2, 4 40 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 150 350 ps

odc Output Duty Cycle odc 45 50 55 %

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

Additive Phase Jitter @ 153.6MHz

12kHz to 20MHz = 0.164ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Parameter Measurement Information

3.3V LVDS Output Load AC Test Circuit

Differential Output Level

Part-to-Part Skew

Differential Input Level

Output Skew

Propagation Delay

SCOPE

nQx

LVDS

3.3V±5%

POWER SUPPLY

+–

Float GND

VDD

GND

VOS

Cross Points

VOD

nQ[0:3]

Q[0:3]

tsk(pp)

Part 1

Part 2

nQx

nQy

VDD

GND

nCLK,

CLK,

VCMR

Cross Points

VPP

nPCLK

PCLK

nQx

nQy

tsk(o)

CLK,

PCLK

tPD

nQ[0:3]

Q[0:3]

nCLK,

nPCLK

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Parameter Measurement Information, continued

Output Rise/Fall Time

Offset Voltage Setup

High Impedance Leakage Current Setup

Output Duty Cycle/Pulse Width/Period

Differential Output Voltage Setup

Differential Output Short Circuit Setup

20%

80% 80%

20%

tRtF

VOD

nQ[0:3]

Q[0:3]

out

LVDS

DC Input

➤

VOS/∆ VOS

VDD

out

LVDS

DC Inpu

➤

3.3V±5% POWER SUPPLY

Float GND

IOZ

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

nQ[0:3]

Q[0:3]

➤

100

out

LVDS

DC Input VOD/∆ VOD

VDD

out

LVDS

DC Input

➤

IOSD

VDD

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Parameter Measurement Information, continued

Output Short Circuit Current Setup Power Off Leakage Setup

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage VREF = VCC/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the VREF in the center of the input voltage

swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,

R1 and R2 value should be adjusted to set VREF at 1.25V. The values

below are for when both the single ended swing and VDD are at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however VIL cannot be less

than -0.3V and VIH cannot be more than VDD + 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

out

LVDS

DC Input

➤

IOS

➤

IOSB

VDD

out

LVDS

➤

IOFF

VDD

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both VSWING and VOH must meet the VPP

and VCMR input requirements. Figures 3A to 3F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver

50Ω

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

125Ω

84Ω

3.3V

Zo = 50Ω

CLK

nCLK

3.3V

LVPECL Differential

Input

HCSL

*R3 33Ω

*R4 33Ω

CLK

nCLK

3.3V 3.3V

Zo = 50Ω

Differential

Input

50Ω

*Optional – R3 and R4 can be 0Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50Ω

3.3V

50Ω

3.3V

100Ω

LVDS

CLK

nCLK

3.3V

Receive

Zo = 50Ω

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120Ω

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

3.3V LVPECL Clock Input Interface

The PCLK/nPCLK accepts LVPECL, CML, SSTL and other

differential signals. Both VSWING and VOH must meet the VPP and

VCMR input requirements. Figures 4A to 4E show interface examples

for the PCLK/nPCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm the

driver termination requirements.

Figure 4A. PCLK/nPCLK Input Driven by a CML Driver

Figure 4C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 4E. PCLK/nPCLK Input Driven by a

2.5V SSTL Driver

Figure 4B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 4D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

3.3V

Zo = 50Ω

3.3V

50Ω

125Ω

84Ω

3.3V

Zo = 50Ω

PCLK

nPCLK

3.3V

LVPECL LVPECL

Input

PCLK

nPCLK

LVPECL

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120

3.3V

100Ω

CML Built-In Pullup

PCLK

nPCLK

3.3V

LVPECL

Input

Zo = 50Ω

50Ω

100Ω - 200Ω

PCLK

VBB

nPCLK

3.3V LVPECL

3.3V

Zo = 50Ω

3.3V

LVPECL

Input

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Recommendations for Unused Input and Output Pins

Inputs:

CLK/nCLK INPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

PCLK/nPCLK INPUTS

For applications not requiring the use of the differential input, both

PCLK and nPCLK can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from PCLK to

ground.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

Outputs:

LVDS Outputs

All unused LVDS outputs should be terminated with 100Ω resistor

between the differential pair.

LVDS Driver Termination

A general LVDS interface is shown in Figure 5. Standard termination

for LVDS type output structure requires both a 100Ω parallel resistor

at the receiver and a 100Ω differential transmission line environment.

In order to avoid any transmission line reflection issues, the 100Ω

resistor must be placed as close to the receiver as possible. IDT

offers a full line of LVDS compliant devices with two types of output

structures: current source and voltage source. The standard

termination schematic as shown in Figure 5 can be used with either

type of output structure. If using a non-standard termination, it is

recommended to contact IDT and confirm if the output is a current

source or a voltage source type structure. In addition, since these

outputs are LVDS compatible, the amplitude and common mode

input range of the input receivers should be verified for compatibility

with the output.

Figure 5. Typical LVDS Driver Termination

100Ω

–

100Ω Differential Transmission Line

LVDS Driver LVDS

Receiver

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS8543.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8543 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.173W * 73.2°C/W = 82.7°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection

θJA by Velocity

Linear Feet per Minute 0200500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Reliability Information

Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

Transistor Count

The transistor count for ICS8543 is: 636

Package Outline and Package Dimensions

Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA by Velocity

Linear Feet per Minute 0200500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N20

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D6.40 6.60

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Ordering Information

Table 9. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

8543BG ICS8543BG 20 Lead TSSOP Tube 0°C to 70°C

8543BGT ICS8543BG 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C

8543BGLF ICS8543BGLF “Lead-Free” 20 Lead TSSOP Tube 0°C to 70°C

8543BGLFT ICS8543BGLF “Lead-Free” 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Revision History Sheet

Rev Table Page Description of Change Date

A T4E 5 In the VOL row, 1.06 has been moved to the Typical column from the maximum column. 9/18/01

A 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01

A 3 Updated Figure 1, CLK_EN Timing Diagram. 11/2/01

6 - 10

Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.

Updated Parameter Measurement Information figures. 5/6/02

B T5 5 AC Characteristics table - revised Output Frequency from 650MHz to 800MHz. 6/5/02

Features - deleted bullet "Designed to meet or exceed the requirements of

ANSI TIA/EIA-644".

LVDS Table - changed VOD typical value from 350mV to 280mV.

9/19/02

T2 2

Pin Characteristics - changed CIN 4pF max. to 4pF typical.

Absolute Maximum Ratings - changed Output rating.

Added Differential Clock Input Interface section.

Added LVPECL Clock Input Interface section.

Added LVDS Driver Termination section.

Updated format throughout data sheet.

12/31/03

D T1 2 Pin Description table - added function description to the OE pin. 4/7/04

DT8

Updated LVPECL Clock Input Interface section.

Added Lead Free part number to Ordering Information table. 6/16/04

Updated Figure 1, CLK_EN Timing Diagram.

Updated Differential Clock Input Interface section.

Updated LVPECL Clock Input Interface section.

Added Recommendation for Unused Input and Output Pins section.

Added Power Considerations section.

Updated format throughout the datasheet.

2/27/08

Features section - added Additive Phase Jitter bullet.

AC Characteristics Table - added Added Phase Jitter spec and thermal note.

Added Additive Phase Jitter plot.

Updated Wiring the Differential Input to Accept Single-ended Levels section.

Updated 3.3V Differential Clock Input Interface section.

Updated 3.3V LVPECL Clock Input Interface section.

Updated LVDS Driver Termination section.

Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.

Updated datasheet header/footer style.

11/12/10

Page 1, corrected Header Title.

Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C. 12/17/10

ICS8543 Data Sheet LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

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