HYM7V65801BTFG-8 - Hynix Semiconductor, Inc.

8Mx64 bits

PC100 SDRAM Unbuffered DIMM

based on 8Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh

HYM7V65801B F-Series

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.1/Apr.01



1999 Hyundai Electronics

DESCRIPTION

The Hynix HYM7V65801B F-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of eight

8Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on

a 168pin glass-epoxy printed circuit board. A 0.33uF and a 0.1uF decoupling capacitors per each SDRAM are mounted

on the PCB.

The HYM7V65801B F-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes

memory. The HYM7V65801B F-Series are offering fully synchronous operation referenced to a positive edge of the

clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally

pipelined to achieve very high bandwidth.

FEATURES

• PC100MHz support

• 168pin SDRAM Unbuffered DIMM

• Serial Presence Detect with EEPROM

• 1.375” (34.93mm) Height PCB with Single Sided

components

• Single 3.3 ± 0.3V power supply

• All devices pins are compatible with LVTTL interface

• Data mask function by DQM

• SDRAM internal banks : four banks

• Module bank : one physical bank

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

-. 1, 2, 4, 8, or Full Page for Sequential Burst

-. 1, 2, 4 or 8 for Interleave Burst

• Programmable /CAS Latency

-. 2, 3 Clocks

ORDERING INFORMATION

PART NO. MAX.

FREQUENCY INTERNAL

BANK REF. POWER SDRAM

PACKAGE PLATING

HYM7V65801BTFG-8 125MHz

HYM7V65801BTFG-10P 100MHz

HYM7V65801BTFG-10S 100MHz

4 Banks 4K Normal TSOP-II Gold

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

PIN DESCRIPTION

PIN NAME DESCRIPTION

CK0~CK3 Clock Inputs The System Clock Input. All other inputs are registered to the

SDRAM on the rising edge of CLK.

CKE0 Clock Enable Controls internal clock signal and when deactivated, the SDRAM

will be one of the states among power down, suspend or self

refresh.

/S0, /S2 Chip Select Enables or disables all inputs except CK, CKE and DQM.

BA0, BA1 SDRAM Bank Address Select bank to be activated during /RAS activity.

Select bank to be read/written during /CAS activity

A0~A11 Address Inputs Row address : RA0~RA11, Column address : CA0~CA8

Auto-precharge flag : A10

/RAS Row Address Strobe /RAS define the operation.

Refer to the function truth table for details.

/CAS Column Address Strobe /CAS define the operation.

Refer to the function truth table for details.

/WE Write Enable /WE define the operation.

Refer to the function truth table for details.

DQM0~DQM7 Data Input/Output Mask Controls output buffers in read mode and masks input data in

write mode.

DQ0~DQ63 Data Input/Output Multiplexed data input/output pins

VCC Power Supply (3.3V) Power supply for internal circuits and input/output buffers

VSS Ground Ground

SCL SPD Clock Input Serial Presence Detect Clock Input

SDA SPD Data Input/Output Serial Presence Detect Data input/output

SA0~SA2 SPD Address Input Serial Presence Detect Address input

WP Write Protect for SPD Write Protect for Serial Presence Detect on DIMM

NC No Connect No Connect or Don’t Use

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

PIN ASSIGNMENTS

FRONT SIDE BACK SIDE FRONT SIDE BACK SIDE

PIN NO. NAME PIN NO. NAME PIN NO. NAME PIN NO. NAME

1VSS 85 VSS 41 VCC 125 *CK1

2DQ0 86 DQ32 42 CK0 126 NC

3DQ1 87 DQ33 43 VSS 127 VSS

4DQ2 88 DQ34 44 NC 128 CKE0

5DQ3 89 DQ35 45 /S2 129 NC

6VCC 90 VCC 46 DQM2 130 DQM6

7DQ4 91 DQ36 47 DQM3 131 DQM7

8DQ5 92 DQ37 48 NC 132 NC

9DQ6 93 DQ38 49 VCC 133 VCC

10 DQ7 94 DQ39 50 NC 134 NC

51 NC 135 NC

Architecture Key 52 NC 136 NC

11 DQ8 95 DQ40 53 NC 137 NC

12 VSS 96 VSS 54 VSS 138 VSS

13 DQ9 97 DQ41 55 DQ16 139 DQ48

14 DQ10 98 DQ42 56 DQ17 140 DQ49

15 DQ11 99 DQ43 57 DQ18 141 DQ50

16 DQ12 100 DQ44 58 DQ19 142 DQ51

17 DQ13 101 DQ45 59 VCC 143 VCC

18 VCC 102 VCC 60 DQ20 144 DQ52

19 DQ14 103 DQ46 61 NC 145 NC

20 DQ15 104 DQ47 62 NC 146 NC

21 NC 105 NC 63 NC 147 NC

22 NC 106 NC 64 VSS 148 VSS

23 VSS 107 VSS 65 DQ21 149 DQ53

24 NC 108 NC 66 DQ22 150 DQ54

25 NC 109 NC 67 DQ23 151 DQ55

26 VCC 110 VCC 68 VSS 152 VSS

27 /WE 111 /CAS 69 DQ24 153 DQ56

28 DQM0 112 DQM4 70 DQ25 154 DQ57

29 DQM1 113 DQM5 71 DQ26 155 DQ58

30 /S0 114 NC 72 DQ27 156 DQ59

31 NC 115 /RAS 73 VCC 157 VCC

32 VSS 116 VSS 74 DQ28 158 DQ60

33 A0 117 A1 75 DQ29 159 DQ61

34 A2 118 A3 76 DQ30 160 DQ62

35 A4 119 A5 77 DQ31 161 DQ63

36 A6 120 A7 78 VSS 162 VSS

37 A8 121 A9 79 CK2 163 *CK3

38 A10/AP 122 BA0 80 NC 164 NC

39 BA1 123 A11 81 WP 165 SA0

40 VCC 124 VCC 82 SDA 166 SA1

83 SCL 167 SA2

Voltage Key 84 VCC 168 VCC

Note : *. CK1, CK3 are connected with termination R/C. (Refer to the Block Diagram.)

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

BLOCK DIAGRAM

Note : 1. The serial resistor values of DQs are 10 Ohms.

2. The padding capacitance of termination R/C for CK1, CK3 is 10pF.

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

SERIAL PRESENCE DETECT

BYTE FUNCTION FUNCTION VALUE

NUMBER DESCRIBED -8 -10P -10S -8 -10P -10S NOTE

BYTE0 # of Bytes Written into Serial Memory

at Module Manufacturer 128 Bytes 80h

BYTE1 Total # of Bytes of SPD Memory Device 256 Bytes 08h

BYTE2 Fundamental Memory Type SDRAM 04h

BYTE3 # of Row Addresses on This Assembly 12 0Ch 1

BYTE4 # of Column Addresses on This Assembly 9 09h

BYTE5 # of Module Banks on This Assembly 1 Banks01h

BYTE6 Data Width of This Assembly 64 Bits 40h

BYTE7 Data Width of This Assembly (Continued) -00h

BYTE8 Voltage Interface Standard of This Assembly LVTTL 01h

BYTE9 SDRAM Cycle Time @ /CAS Latency=3 8ns 10ns 10ns 80h A0h A0h

BYTE10 Access Time from Clock @ /CAS Latency=3 6ns 6ns 6ns 60h 60h 60h

BYTE11 DIMM Configuration Type None 00h

BYTE12 Refresh Rate/Type 15.625µs

/ Self Refresh Supported 80h

BYTE13 Primary SDRAM Width x8 08h

BYTE14 Error Checking SDRAM Width None 00h

BYTE15 Minimum Clock Delay Back to Back Random

Column Address tCCD = 1 CLK 01h

BYTE16 Burst Lengths Supported 1,2,4,8,Full Page 8Fh 2

BYTE17 # of Banks on Each SDRAM Device 4 Banks 04h

BYTE18 SDRAM Device Attributes, CAS # Latency /CAS Latency=2,3 06h

BYTE19 SDRAM Device Attributes, CS # Latency /CS Latency=0 01h

BYTE20 SDRAM Device Attributes, Write Latency /WE Latency=0 01h

BYTE21 SDRAM Module Attributes Neither Buffered nor Registered 00h

BYTE22 SDRAM Device Attributes, General

+/-10% voltage tolerance, Burst

Read Single bit Write, Precharge

All, Auto Precharge, Early RAS

Precharge

0Eh

BYTE23 SDRAM Cycle Time @ /CAS Latency=2 10ns 10ns 12ns A0h A0h C0h

BYTE24Access Time from Clock @ /CAS Latency=26ns 6ns 6ns 60h 60h 60h

BYTE25SDRAM Cycle Time @ /CAS Latency=1- - - 00h 00h 00h

BYTE26Access Time from Clock @ /CAS Latency=1- - - 00h 00h 00h

BYTE27Minimum Row Precharge Time (tRP) 20ns 20ns 20ns 14h 14h 14h

BYTE28Minimum Row Active to Row Active Delay (tRRD) 16ns 20ns 20ns 10h 14h 14h

BYTE29Minimum /RAS to /CAS Delay (tRCD) 20ns 20ns 20ns 14h 14h 14h

BYTE30 Minimum /RAS Pulse width (tRAS) 48ns 50ns 50ns 30h 32h 32h

BYTE31 Module Bank Density 64MB 10h

BYTE32 Command and Address Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h

BYTE33 Command and Address Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h

BYTE34 Data Signal Input Setup Time 2ns 2ns 2ns 20h 20h 20h

BYTE35 Data Signal Input Hold Time 1ns 1ns 1ns 10h 10h 10h

BYTE36

–61 Superset Information (may be used in future) -00h

BYTE62 SPD Revision Intel SPD 1.2A 12h 3, 8

BYTE63 Checksum for Bytes 0~62 -DFh 05h 25h

BYTE64 Manufacturer JEDEC ID Code Hynix JEDEC ID ADh

BYTE65

~71 ....Manufacturer JEDEC ID Code Unused FFh

BYTE72 Manufacturing Location

Hynix (Korea Area)

HSA (United States Area)

HSE (Europe Area)

HSJ (Japan Area)

Asia Area

0*h

1*h

2*h

3*h

4*h

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

Continued

BYTE FUNCTION FUNCTION VALUE

NUMBER DESCRIBED -8 -10P -10S -8 -10P -10S NOTE

BYTE73 Manufacturer’s Part Number (Component) 7 (SDRAM) 37h 4, 5

BYTE74 Manufacturer’s Part Number (Voltage Interface) V (3.3V, LVTTL) 56h 4, 5

BYTE75 Manufacturer’s Part Number (Data Width) 6 36h 4, 5

BYTE76 ....Manufacturer’s Part Number (Data Width) 5 35h 4, 5

BYTE77 Manufacturer’s Part Number (Memory Depth) 8 38h 4, 5

BYTE78 Manufacturer’s Part Number (Refresh) 0 (4K Refresh) 30h 4, 5

BYTE79 Manufacturer’s Part Number (Internal Banks) 1 (4 Banks) 31h 4, 5

BYTE80 Manufacturer’s Part Number (Generation) B42h 4, 5

BYTE81 Manufacturer’s Part Number (Package Type) T (TSOPII) 54h 4, 5

BYTE82 Manufacturer’s Part Number (Module Type) F (x8 based Unbuffered DIMM) 46h 4, 5

BYTE83 Manufacturer’s Part Number (Plating Type) G (Gold) 47h 4, 5

BYTE84 Manufacturer’s Part Number (Hyphen) - (Hyphen) 2Dh4, 5

BYTE85 Manufacturer’s Part Number (Min. Cycle Time) 8 1 1 38h 31h 31h 4, 5

BYTE86 ....Manufacturer’s Part Number (Min. Cycle Time) Blank 0 0 20h 30h 30h 4, 5

BYTE87 ....Manufacturer’s Part Number (Min. Cycle Time) Blank P S 20h 50h 53h 4, 5

BYTE88

~90 Manufacturer’s Part Number Blanks 20h 4, 5

BYTE91 Revision Code (for Component) Process Code -4, 6

BYTE92 ....Revision Code (for PCB) Process Code -4, 6

BYTE93 Manufacturing Date Work Week -3, 6

BYTE94 ....Manufacturing Date Year -3, 6

BYTE95

~98 Assembly Serial Number Serial Number -6

BYTE99

~125 Manufacturer Specific Data (may be used in

future) None 00h

BYTE126 System Frequency Support 100MHz 64h 8

BYTE127 Intel Specification Details for 100MHz Support Refer to Note7 A7h A7h A5h 7, 8

BYTE128

~256 Unused Storage Locations -00h

Note: 1. The bank address is excluded.

2. 1,2,4,8 for Interleave Burst Type

3. BCD adopted.

4. ASCII adopted.

5. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.

6. Not fixed but dependent.

7. CLK0, CLK2 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support

8. Refer to Intel SPD Specification Rev.1.2A.

9. Refer to Hynix Web Site

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Ambient Temperature TA 0 ~ 70 °C

Storage Temperature TSTG -55 ~ 125 °C

Voltage on any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 MA

Power Dissipation PD 8W

Soldering Temperature · Time TSOLDER 260 · 10 °C · Sec

Note : Operation at above absolute maximum can adversely affect device reliability.

DC OPERATING CONDITION

(TA = 0 to 70°C)

PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE

Power Supply Voltage VCC 3.0 3.3 3.6 V1

Input High Voltage VIH 2.0 3.0 VCC + 2.0 V1, 2

Input Low Voltage VIL VSS – 2.0 00.8 V1, 3

Note : 1. All voltage are referenced to VSS = 0V.

2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration.

3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration.

AC OPERATING CONDITION

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)

PARAMETER SYMBOL VALUE UNIT

AC Input High / Low Level Voltage VIH / VIL 2.4 / o.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise / Fall Time tR / tF 1ns

Output Timing Measurement Reference Level Voltage Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL *Note pF

Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).

For details, refer to AC/DC output circuit.

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

CAPACITANCE

(TA = 25°C, f = 1MHz)

PARAMETER PIN SYMBOL MIN MAX TYP. UNIT

CK0, CK2 CIN1 -45 -pF

CKE0 CIN2 -60 -pF

/S0, /S2 CIN3 -40 -pF

A0~A11, BA0, BA1 CIN4 -60 -pF

/RAS, /CAS, /WE CIN5 -60 -pF

Input Capacitance

DQM0~DQM7 CIN6 -15 -pF

Data Input/Output Capacitance DQ0~DQ63 CI/O -15 -pF

OUTPUT LOAD CIRCUIT

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

DC CHARACTERISTICS I

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)

PARAMETER SYMBOL MIN MAX UNIT NOTE

Input Leakage Current ILI -8 8uA 1

Output Leakage Current ILO -1 1uA 2

Output High Voltage VOH 2.4 -VIOH = -4mA

Output Low Voltage VOL -0.4 VIOL = +4mA

Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.

2. DOUT is disabled. VOUT = 0 to 3.6V.

DC CHARACTERISTICS II

(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)

SPEED

PARAMETER SYMBOL TEST CONDITION -8 -10P -10S UNIT NOTE

Operating Current IDD1 Burst Length = 1, One bank active

tRC ≥ tRC(min), IOL = 0mA 640 560 560 mA 1

IDD2P CKE ≤ VIL(max), tCK = min 16 mA

Precharge Standby Current

in Power Down Mode IDD2PS CKE ≤ VIL(max), tCK = ∞16 mA

IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 120 mA

Precharge Standby Current

in Non Power Down Mode IDD2NS CKE ≥ VIH(max), tCK = ∞

Input signals are stable. 120 mA

IDD3P CKE ≤ VIL(max), tCK = min 40 mA

Active Standby Current

in Power Down Mode IDD3PS CKE ≤ VIL(max), tCK = ∞40 mA

IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V 240 mA

Active Standby Current

in Non Power Down Mode IDD3NS CKE ≥ VIH(max), tCK = ∞

Input signals are stable. 240 mA

CL = 3 880 720 720

Burst Mode Operating

Current IDD4 tCK ≥ tCK(min), IOL = 0mA

All banks active CL = 2 720 720 720 mA 1

Auto Refresh Current IDD5 tRRC ≥ tRRC(min), All banks active 1600 1440 1440 mA 2

Self Refresh Current IDD6 CKE ≤ 0.2V 16 mA

Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

AC CHARACTERISTICS I

(AC operating conditions unless otherwise noted)

-8 -10P -10S

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT NOTE

/CAS Latency = 3 tCK3 8 10 10

System Clock

Cycle Time /CAS Latency = 2 tCK2 10 1000 10 1000 12 1000 ns

Clock High Pulse Width tCHW 3-3-3-ns I

Clock Low Pulse Width tCLW 3-3-3-ns I

/CAS Latency = 3 tAC3 -6-6-6

Access Time

from Clock /CAS Latency = 2 tAC2 -6-6-6ns 2

Data-Out Hold Time tOH 3-3-3-ns

Data-Input Setup Time tDS 2-2-2-ns 1

Data-Input Hold Time tDH 1-1-1-ns 1

Address Setup Time tDS 2-2-2-ns 1

Address Hold Time tDH 1-1-1-ns 1

CKE Setup Time tDS 2-2-2-ns 1

CKE Hold Time tDH 1-1-1-ns 1

Command Setup Time tDS 2-2-2-ns 1

Command Hold Time tDH 1-1-1-ns 1

CLK to Data Output in Low-Z time tOLZ 1-1-1-ns

/CAS Latency = 3 tOHZ3 363636CLK to Data

Output in

High-Z time /CAS Latency = 2 tOHZ2 363636ns

Note : 1. Assume tR / tF (input rise and fall time) is 1ns.

2. Access times to be measured with input signals of 1v/ns edge rate.

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

AC CHARACTERISTICS II

-8 -10P -10S

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT NOTE

Operation tRC 68 70 70

/RAS Cycle

Time Auto Refresh tRRC 68 -70 -70 -ns

/RAS to /CAS Delay tRCD 20 -20 -20 -ns

/RAS Active Time tRAS 48 100K 50 100K 50 100K ns

/RAS Precharge Time tRP 20 -20 -20 -ns

/RAS to /RAS Bank Active Delay tRRD 16 -20 -20 -ns

/CAS to /CAS Delay tCCD 1-1-1-CLK

Write Command to Data-in Delay tWTL 0-0-0-CLK

Data-in to Precharge Command tDPL 1-1-1-CLK

Data-in to Active Command tDAL 4-3-3-CLK

DQM to Data-out Hi-Z tDQZ 2-2-2-CLK

DQM to Data-in Mask tDQM 0-0-0-CLK

MRS to New Command tMRD 2-2-2-CLK

/CAS Latency = 3 tPROZ3 3-3-3-Precharge to

Data Output

Hi-Z /CAS Latency = 2 tPROZ2 2-2-2-CLK

Power Down Exit Time tPDE 1-1-1-CLK

Self Refresh Exit Time tSRE 1-1-1-CLK 1

Refresh Time tREF -64 -64 -64 ms

Note : 1. A new command can be given tRRC after self refresh exit.

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

OPERATING OPTION TABLE

HYM7V65801BTFG-8

/CAS

LATENCY tRCD tRAS tRC tRP tAC tOH

125MHz (8.0ns) 3CLKS 3CLKS 6CLKS 9CLKS 3CLKS 6ns 3ns

100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns

83MHz (12.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns

HYM7V65801BTFG-10P

/CAS

LATENCY tRCD tRAS tRC tRP tAC tOH

100MHz (10.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns

83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns

66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns

HYM7V65801BTFG-10S

/CAS

LATENCY tRCD tRAS tRC tRP tAC tOH

100MHz (10.0ns) 3CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns

83MHz (12.0ns) 2CLKS 2CLKS 5CLKS 7CLKS 2CLKS 6ns 3ns

66MHz (15.0ns) 2CLKS 2CLKS 4CLKS 6CLKS 2CLKS 6ns 3ns

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

COMMAND TRUTH TABLE

CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10/

BA NOTE

Mode Register Set HXLLLLXOP code

HX X X

No Operation HXLHHHX X

Bank Active HXL L HHXRA V

Read L

Read with Autoprecharge HXLHLHXCA HV

Write L

Write with Autoprecharge HXLHLLXCA HV

Precharge All Banks HX

Precharge Selected Bank HXL L HLX X LV

Burst Stop HXLH H LX X

DQM HX V X

Auto Refresh H H LLLHX X

Entry HL L L L HX

HX X XSelf Refresh Exit LHLHHHXX1

HX X X

Entry HLLHHHX

HX X X

Precharge

Power Down Exit LHLHHHX

HX X X

Entry HLLV V V X

Clock Suspend

Exit LHX X

Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.

2. X = Don’t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,

NOP = No operation

PC100 SDRAM Unbuffered DIMM

HYM7V65801B F-Series

Rev. 1.1/Apr.01

PACKAGE DIMENSIONS