1
GMM77316280CTG-5/6
16,777,216 WORDS x 72 BIT
CMOS DYNAMIC RAM MODULE
* This Data Sheet is subject to change without notice.
Description
The GMM77316280CTG is an 16M x 72 bits
Dynamic RAM MODULE which is assembled
18 pieces of 16M x 4bit DRAMs in 32 pin
TSOP¥± package and two 16bit driver ICs in
48pin TSSOP package mounted on a 168 pin
printed circuit board with decoupling capacitors.
The GMM77316280CTG is optimized for
application to the systems which are required
high density and large capacity such as main
memory of the computers and an image memory
systems, and to the others which are requested
compact size.
The GMM77316280CTG provides common
data inputs and Extended Data Outputs.
Features
* 168 pins Dual In-Line Package
- GMM77316280CTG : Gold plating
* Extended Data Ouput (EDO) Mode Capability
* Single Power Supply
* Fast Access Time & Cycle Time
* Low Power
Active : 9144/8496mW (MAX)
Standby : 105mW (CMOS level : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
(Unit: ns)
GMM77316280CTG-5
tRAC tCAC tRC tHPC
50
60 20 104 25GMM77316280CTG-6
GMM77316280CTG (Both Side)
Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Symbol
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
DQ16
DQ17
VSS
RSVD
RSVD
VCC
/WE0
/CAS0
VSS
DQ36
DQ37
DQ38
DQ39
VCC
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ50
DQ51
DQ52
DQ53
VSS
RSVD
RSVD
VCC
RFU
/CAS1*
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
VSS
PD1
PD3
PD5
PD7
ID 0
VCC
RSVD
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12*
VCC
RFU
RFU
VSS
/OE2
/RAS2
/CAS4
RSVD
/WE2
VCC
RSVD
RSVD
DQ18
DQ19
VSS
DQ20
DQ21
Pin Configuration (Top View)
Pin Symbol
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
RSVD
/RAS1*
RFU
VSS
A1
A3
A5
A7
A9
A11
A13*
VCC
RFU
B0
VSS
RFU
/RAS3*
/CAS5*
RSVD
/PDE
VCC
RSVD
RSVD
DQ54
DQ55
VSS
DQ56
DQ57
Pin Symbol
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
VCC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
VSS
DQ64
DQ65
DQ66
DQ67
VCC
DQ68
DQ69
DQ70
DQ71
VSS
PD2
PD4
PD6
PD8
ID 1
VCC
Note : Pins Marked * are not used in this module.
Speed
18 84 20
GMM77316280CTG-5/6
2
Block Diagram
DQ 0 DQ 36
DQ 37
DQ 38
DQ 39
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 52
DQ 53
DQ 54
DQ 55
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 64
DQ 65
DQ 66
DQ 67
DQ 68
DQ 69
DQ 70
DQ 71
VCC
VSS
0.22uF Capacitor D0~D17, Buffer
DQ 0 DQ 0
DQ 1
DQ 2
DQ 3 D9
DQ 0
DQ 1
DQ 2
DQ 3 D10
DQ 0
DQ 1
DQ 2
DQ 3 D11
DQ 0
DQ 1
DQ 2
DQ 3 D12
DQ 0
DQ 1
DQ 2
DQ 3 D13
DQ 0
DQ 1
DQ 2
DQ 3 D14
DQ 0
DQ 1
DQ 2
DQ 3 D15
DQ 0
DQ 1
DQ 2
DQ 3 D16
DQ 0
DQ 1
DQ 2
DQ 3 D17
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 32
DQ 33
DQ 34
DQ 35
DQ 48
DQ 49
DQ 50
DQ 51
DQ 1
DQ 2
DQ 3 D0
DQ 0
DQ 1
DQ 2
DQ 3 D2
DQ 0
DQ 1
DQ 2
DQ 3 D3
DQ 0
DQ 1
DQ 2
DQ 3 D4
DQ 0
DQ 1
DQ 2
DQ 3 D5
DQ 0
DQ 1
DQ 2
DQ 3 D6
DQ 0
DQ 1
DQ 2
DQ 3 D7
DQ 0
DQ 1
DQ 2
DQ 3 D8
DQ 0
DQ 1
DQ 2
DQ 3 D1
VCC
VSS
2.2uF Tantal
Capacitor
+
DRAMS: D0~D17
A1~A11
A0
B0
DRAMS: D0~D8
DRAMS: D9~D17
VSS
PDE (when= 0, 1= NC)
D0~D17, Buffer
OE0
WE0
CAS0
RAS0
A1~A11
CAS4
RAS2
OE2
WE2
GMM77316280CTG-5/6
3
Pin Description
Pin Function Pin Function
A0,B0,A1-A11
DQ0-DQ71 VCC
VSS
NC
Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read/Write Enable
Power (+3.3V)
Ground
No Connection
RAS0, RAS2
CAS0, CAS4
WE0, WE2
PDE Presence Detect Enable
PD 1~8 Presence Detect
ID 0~1 ID bit
RSVD Reserved Use
RFU Reserved for Future Use
OE0, OE2 Output Enable
Presence Detect Pins (Optional)
Pin 50ns 60ns
PD1
PD2
1
PD3
PD4
1
1
1
1
1
1
1
PD5
PD6 1
01
1
0
PD7
PD8
00
1
0
ID0
ID1 00
0
Absolute Maximum Ratings*
*Note: 1. Stress greater than above Absolute Maximum Ratings may cause permanent damage to the device.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol Parameter Unit
VCC
VIH
VIL
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
Max
3.6
Typ
3.3
-
-
Min
3.0
Note
1
1
1
Symbol Parameter Rating Unit
TA
TSTG
VIN/VOUT
0 ~ 70
-55 ~ 125
-0.5 ~ 4.6
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS V
IOUT 50
Short Circuit Output Current mA
PD21
Power Dissipation W
C
C
2.0
-0.3
Vcc+0.3
0.8
Vcc Voltage on Vcc Pin Relative to VSS -0.5 ~ 4.6 V
*Note: 1. All voltages referenced to VSS.
GMM77316280CTG-5/6
4
DC Electrical Characteristics: (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Unit Note
V
V
uA
uA
§Ì
§Ì
§Ì
§Ì
§Ì
§Ì
§Ì
1,2
1,3
2
1
Symbol Parameter
VOH
VOL
Output Level
Output ``H`` Level Voltage (IOUT = -2§Ì)
Output Level
Output ``L`` Level Voltage (IOUT = 2§Ì)
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
ICC2
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
ICC3
RAS-Only Refresh Current
Average Power Supply Current
RAS-Only Refresh Mode
(RAS Cycling, CAS = VIH, tRC = tRC min)
ICC4
Extended Data Out Mode Current
Average Power Supply Current
Extended Data Out Mode
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
ICC5
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS>=VCC-0.2V, DOUT = High-Z)
ICC6 CAS-before-RAS Refresh Current
(tRC = tRC min)
ICC7 Standby Current
II(L)
IO(L)
Input Leakage Current, Any Input
(0V VIN Vcc)
Output Leakage Current
(DOUT is Disabled, 0V VOUT Vcc)
RAS = VIH
CAS = VIL
DOUT = Enable
GMM77316280CTG
Min Max
50ns
60ns
2.4
0
-
-
-
-
-
-
-
-
-
-
-
-5
-5
50ns
60ns
50ns
60ns
50ns
60ns
Vcc
0.4
2540
2360
2540
2360
2540
2360
56
2000
1820
29
110
5
5
GMM77316280CTG-5/6
5
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C, f = 1MHz)
Symbol Parameter NoteUnitMaxMin
CI1
CI2
C13
Input Capacitance (A0~A11,B0)
Input Capacitance (WE0, WE2, OE0, OE2)
Input Capacitance (RAS0,RAS2)
1
1, 2
1, 2
pF
pF
pF
20
20
65
-
-
-
C14 Input Capacitance (CAS0,CAS4) 1, 2pF20-
CI/O I/O Capacitance (DQ0~DQ71) 1, 2pF20-
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns Output timing reference levels : VOL/VOH = 0.8/2.0V
Input level : VIL/VIH = 0.0/3.0V Output load : 1 TTL gate+CL (100pF)
Input timing reference levels : VIL/VIH = 0.8/2.0V (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Max Max
Min
tRC
tRP
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
4
tRAD
3
tRSH
tCSH
tCRP
Min
84
30
50
8
5
8
0
8
12
10
18
35
10
-
-
10000
-
-
-
-
32
20
-
-
-
Unit Notes
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
tT
tREF Refresh Period ( 4096 Cycles)
2
-
50
64
§À
ms
tODD
tDZO
tDZC
18
0
0
-
-
-
§À
§À
§À
60
10
104 -
40 -
10000
5-
10 -
0-
10 -
14 40
12 25
20 -
40 -
10 -
20 -
0-
0-
250
-64
tCP 8-§À
10 -
10000 10000
GMM77316280CTG-5 GMM77316280CTG-6
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
TransitionTime
(Rise and Fall)
OE to DIN Delay Time
OE Delay Time from DIN
CAS Set-up Time from DIN
CAS Precharge Time
5
6
6
7
GMM77316280CTG-5/6
6
Read Cycles
Symbol Max Max
MinMin
-
-
-
0
0
0
30
50
18
30
-
-
-
Unit Notes
§À
§À
§À
§À
§À
§À
§À
§À
-
tRAC
tCAC
tAA
tRCS
tRCH
tRRH
tRAL
tCAL
8,9
tOAC -18 -20 §À
-60
-20
-35
0-
0-
0-
35 -
18 -15 -
9,10,17
§À
§À
tRDD
tWDD
§À
tOFR
§ÀtWEZ -15
-15
15 -
-15
-13
-13
13 -
13 -
§À
§À
§À
tCLZ
tOH
tCDD
CAS to Output in Low - Z
18 -
§À
§À
tOHR
tOEZ
§ÀtOFF
20 -
-20
-20
-
3-
-2
18
-18
-
3-
-
-
§ÀtRCHR 60 -50 -
§ÀtOHO 3-3-
2
9
33
GMM77316280CTG-5 GMM77316280CTG-6
Parameter
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Read Command Set-up Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead TIme
Column Address to CAS Lead Time
Access Time from OE
RAS to DIN Delay Time
Output Buffer Turn-off Delay Time from RAS
Output Buffer Turn-off Delay Time from WE
Output Data Hold Time
CAS to DIN Delay Time
Output Data Hold Time from RAS
Output Buffer Turn-off Delay Time from OE
WE to DIN Delay Time
Read Command Hold Time from RAS
Output Buffer Turn-off Delay Time from CAS
9,11,17
12
12
13,21
13
5
13
21
13,21
21
Output Data Hold Time from OE
GMM77316280CTG-5/6
7
Wrtie Cycles
Read-Modify-Write Cycles
tRWC
tRWD
tCWD
tAWD
Refresh Cycle
Symbol Max Max
Min
Min
116
72
30
42
-
-
-
-
Unit Notes
§À
§À
§À
§À
Refresh Cycles
tCSR
Symbol
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
tCHR CAS Hold Time
(CAS-before-RAS Refresh Cycle)
Parameter Max Max
Min
Min
5-
Unit Notes
§À
8-
-
§À
§À
tOEH 13 -§À
140
84
34
49
15
-
-
-
-
-
14
5
10
10
-
-
tRPC RAS Precharge to CAS Hold Time 5-§À
5-
-
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
Symbol
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
Data-in Hold Time
Parameter Max Max
Min
Min
0
8
8
8
0
13
-
-
-
-
-
-
Unit Notes
§À
§À
§À
§À
§À
§À
§À
-
14
15
15
0
10
10
10
0
15
-
-
-
-
-
-
-
Read-Modify-Write Cycle Time
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
Parameter
OE Hold Time from WE
18 20
14
14
GMM77316280CTG-5 GMM77316280CTG-6
GMM77316280CTG-5 GMM77316280CTG-6
GMM77316280CTG-5 GMM77316280CTG-6
21
tWRP WE setup Time
(CAS-before-RAS Refresh Cycle)
tWRH WE Hold Time
(CAS-before-RAS Refresh Cycle)
5
8
5§À
GMM77316280CTG-5/6
8
-
-28
§À
§À
-
-35
33 -
100000
§À
40 -
100000
tRASP
tACP
tRHCP
28 -§À
35 -
8
5
-
-
§À
§À
10
5
-
-
5-§À
§À
5-
8-10 -
tCOL
tCOP
tOEP
tRCHP
EDO Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
OE Precharge Time
CAS Hold Time Referred OE
CAS to OE set-up Time
Read Command Hold Time from CAS
Precharge
Output Data Hold Time from CAS Low
16
Max Max
Min
Min
20
8
-
-
Unit Notes
§À
§À
25
10
-
-
Extended Data Out Mode Cycles
tHPC
tWPE
Symbol
EDO Page Mode Cycle Time
Write pulse width during CAS Precharge
Parameter GMM77316280CTG-5 GMM77316280CTG-6
tDOH
Max Max
Min
Min
57
45
-
-
Unit Notes
§À
§À
68
54
-
-
EDO Page Mode Read-Modify-Write cycle
tHPRWC
tCPW
Symbol
EDO Page Mode Read-Modify-Write Cycle Time
WE delay time from CAS precharge
Parameter GMM77316280CTG-5 GMM77316280CTG-6
20
9,17
9,22
14
Present Detect Read cycle
Symbol Max Max
Min
Min Unit Notes
ns
§À
GMM77316280CTG-5 GMM77316280CTG-6
tPD
tPDOFF
Parameter
PDE to Valid PD bit
PDE to PD bit in active
1010
772 2
GMM77316280CTG-5/6
9
Notes:
AC measurements assume tT = 2§À.
AC initial pause of 200 us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is
controlled exclusively by tCAC.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is
controlled exclusively by tAA.
Either tOED or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
Assumes that t RCD<=tRCD(max) and t RAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max).
Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF(max), tOEZ(max), tOFR(max) and t WEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if t WCS >=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD >=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and t CPW>=tCPW(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
tRASP defines RAS pulse width in extended data out mode cycles.
Access time is determined by the longest among tAA, tCAC and tCPA.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
GMM77316280CTG-5/6
10
tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + tCP + 2tT) becomes greater than the
specified tHPC(min) value.
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
tDOH defines the time at which the output level go cross. V OL=0.8V, VOH=2.0V of output timing
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
§Â period on the condition a and b below.
a. Enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
For L_version, it is available to apply each 128 §Â and 31.2 us instead of 64 §Â and 15.6us at
note 23.
At tRASS£¾100 us , self refresh mode is activated, and not activated at t
RASS £¼10us. It is undefined
within the range of 10 us £¼tRASS £¼100 us . for tRASS £¾10 us , it is necessary to satisfy tRPS.
XXX: H or L ( H : VIH(min)<=
VIN<=
VIH(max), L: VIH(min)<=
VIN<=
VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
20.
21.
22.
23.
24.
25.
26.
27.
The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
GMM77316280CTG-5/6
11
Package Dimension
85168
184
5250(133.35)
5013.78(127.35)
1700(43.18)
1450(36.83) 2150(54.61)
450(11.43) 250(6.35)
700(17.78)
157.48(4.0)
1250(31.75)
"C" "B" "A"
4550(115.57)
Unit: mil (mm)
* (1 mil = 1/1000 inches)
NOTE : 1. Tolerances on all dimensions +/-5 (0.127) unless otherwise specified.
2. Thickness includes Plating and / or Metallization.
DETAIL "B" DETAIL "A"
5.9(0.15)
100(2.54) min.
39.37(1.0)
50(1.27)
78.74(2.0)
39.37(1.0)
DETAIL "C"
78.74(2.0)
122.83(3.12)
39.37(1.0)
125(3.175)
125(3.175)
R78.74
(2.0)
R78.74
(2.0)
157.48(4.0) max.
50(1.27)
157.48(4.0) min.
(Front Side)
(Rear Side)
