TP3094 TP3094 COMBO Quad PCM Codec/Filter Literature Number: SNOS417A TP3094 COMBO(R) Quad PCM Codec/Filter General Description Features * Handles four voice channels * Complete Codec and Filter system including: The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice channels, combining transmit bandpass and receive low pass channel filters with companding Alaw or m-law PCM encoders and decoders. The device is fabricated using National's advanced CMOS process. - Transmit and receive channel filters - A-law or -law companding encoder/decoder * Power down mode for low power consumption * Compatible to standard time division multiplexed PCM bus - 8 bit mode, frame signal from external reference - 32 bit mode, internal TSA, with consecutive TS * Up to 128 channels (32 devices) can be cascaded * Programmable functions (common for all 4 channels): - A-law or -law e The device includes anti-aliasing filters and sigma-delta converters dedicated to each channel, and by a common signal processing unit which performs all the remaining filtering and processing for the four channels. et - Single MCLK clock,automatically selectable from 8.192MHz, 4.096MHz, 2.048MHz and 1.536/1.544MHz - Digital and Analog loopback test modes The TP3094 includes a flexible PCM digital interface, which allows the device to be connected to PCM busses of different formats. It can also be connected with other TP3094 devices in a cascade fashion, for a system with up to 128 POTS interfaces (when a 2.048MHz PCM bus is used). Designed for CCITT and LSSGR applications Single +5V power supply 44 lead PLCC surface mount package Maximize line card circuit density Use in Central Office, Loop Carrier, and PBX equipment subscriber line and trunk cards * Wide operating temperature range -40C to bs ol * * * * * 85C O VXI3 GXO3 VRO3 AVCC1 PDN3 PDN2 PDN1 PDN0 A/Law MCLK DR Connection Diagram 5 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 TP3094 12 34 13 33 14 32 15 31 30 16 29 17 18 19 20 21 22 23 24 DX DGND PT4 DVCC FSX3 NC FSR3 FSX2 FSR2 FSX1 FSR1 25 26 27 28 GXO0 VRO0 PT3 AVCC0 PT1 PCMMode PT2 TST TSX FSR0 FSX0 AGND1 VXI2 GXO2 VRO2 NC VRO1 GXO1 VXI1 NF AGND0 VXI0 6 7 Order Number TP3094V See NS Package V44A COMBO(R) and TRI-STATE(R) are registered trademarks of National Semiconductor Corporation (c) 2003 National Semiconductor Corporation www.national.com TP3094 Quad PCM Codec/Filter April 2003 Simplified Block Diagram + VRO0 GXO1 VXI1- + VRO1 GXO2 VXI2- DAC ClockDetection ADC + MCLK Digital Signal Processor PCM Interface ADC TSx DAC + DX DR FSX0-3 FSR0-3 PCMMode ADC DAC TST et VRO3 PLL DAC VRO2 GXO3 VXI3- ADC e GXO0 VXI0- bs ol A/u Law PDN0-3 NF PT3 PT4 PT2 PT1 AVCC0 AGND0 AVCC1 AGND1 DVCC DGND Ref & Bias O FIGURE 1. Simplified block diagram 2 www.national.com Pin Descriptions signed transmit time-slots (for all four channels). MCLK (input) Master and PCM bit clock input. Must be either 1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or 8.192MHz. Its value is automatically detected internally on power up with the valid frame sync input. DR (input) Receive PCM data input. Serial PCM data is shifted into the device on the falling edge of MCLK during the assigned receive time-slot. FSX0, FSR0 (inputs) Transmit and Receive Frame synchronization inputs for channel 0. They identify the beginning of a new frame in the transmit and receive direction. They are 8 KHz logic signals, and must be synchronous to MCLK. Short Frame Sync and Long Frame Sync are both supported. In 32-bit mode these signals constitute the 8kHz reference for all channels. Only Short Frame Sync is supported in 32-bit mode. AVCC0, AVCC1 Positive supply pins for the analog circuitry. AVCC0 is for channel 0 and channel 1. AVCC1 is for channel 2 and channel 3. AVCC0=AVCC1=+5V 5%. These two pins should be connected together outside the device. et FSX1, FSR1 (inputs/outputs) Transmit and Receive Frame synchronization inputs for channel 1. In 32-bit mode these pins become outputs and generate a frame sync signal with the last bit of the 32-bit stream, in order to allow to cascade another TP3094 in 32-bit mode. FSX1 is the Transmit Frame output and FSR1 is the Receive Frame output. bs ol DVCC Positive supply for the digital circuitry. DVCC=+5V 5%. e AGND0, AGND1 Analog ground. All analog signals are referenced to AGND0 and AGND1. AGND0 is the analog ground for channel 0 and channel 1. AGND1 is the analog ground for channel 2 and channel 3. These two pins should be connected together outside the device. DGND Digital ground. All logic signals are referenced to DGND. This ground has to be connected to the ground of other digital devices at board level. FSX2,FSX3, FSR2,FSR3 (inputs) Transmit and Receive Frame synchronization inputs for channel 2 and 3. These pins are recommended to be connected to analog ground when in 32-bit mode. Analog ports VXI0-, VXI1-, VXI2-, VXI3- (inputs) Inverting analog inputs of the transmit input amplifiers of channels 0-3. They are referenced to an internal reference voltage of about 2.4V. A/u LAW select (input) A/u law select. Through this pin either A-law (+5V) or u-law (0V) is selected. GXO0, GXO1, GXO2, GXO3 (outputs) Outputs of the transmit input amplifiers of channels 0-3. They are referenced to an internal reference voltage of about 2.4V O PDN0-3 (input) Power Down control signals. Each channel has a dedicated Power Down input. When active high, these pins set the low power mode, shutting down most of the circuitry dedicated to it and reducing the power consumption. The relative analog outputs VROi and GXOi, and the digital output DX are put in high impedance. VRO0, VRO1, VRO2, VRO3 (ouputs) Analog outputs of the receive amplifiers for channels 0-3. They are referenced to an internal reference voltage of about 2.4V TST (input) Test Modes Enable. When active (HIGH), together with the PDNi pins selects one of the available test modes (see the text for a full description of these modes). PCM Port DX (ouput) Transmit PCM data output. Serial PCM data is shifted out on the rising edge of MCLK during the assigned transmit time-slot. Tristated when the assigned transmit time-slot is not active. PCMMode (input) PCM Mode selection. When this signal is LOW (0V), the 8 bit mode is selected and each channel TSx (ouput) Open drain output that pulses low during the as3 www.national.com Pin Descriptions (continued) Power Initialization When power is first applied to the device, poweron reset circuitry initializes the device and places it in the power down state. All non-essential circuits are de-activated. PCM output DX and analog outputs VRO0-3 are placed in the high impedance state, while FSX1 and FSR1 outputs are held low (in case 32-bit mode is selected). In the power down mode, power consumption is reduced to a minimum, typically 2mW. The device will remain in this state as long as no MCLK is applied and no Frame Signal is applied (just FSX0 and FSR0 in case of 32-bit mode). For each channel, when the PDN input is not active, MCLK is applied, and a FS (receive or transmit) pulse is running, the device enters the active power up mode. The MCLK frequency is detected with any available FS signal; the clock rate detection may last for up to 4ms, after which the device is ready for powering up. Analog and PCM output signals will be available after a few frames; it will take about 100ms until the first activated channel is fully functional. The device will only power up when at least one of the FS signals and the MCLK signal are in a valid frequency ratio. expects its individual transmit and receive frame signal. When it is HIGH, the 32 bit mode is selected; in this mode FSX0 and FSR0 are used as framing signals and the TS are allocated consecutively from these frames, starting from Ch0 to Ch3. In this mode FSX1 and FSR1 become outputs and produce 1 bit long frame signals with the last bit of the 32 bit stream. These Frame signals can be used to cascade another device in 32 bit mode. e NF Noise Filter Pin. For optimal noise rejection a 100nF capacitor must be connected between this pin and the analog ground AGND0. et PT1, PT2, PT3, PT4 (inputs) These pins are used by National for internal manufacturing test. They must be connected to digital ground for normal device operation. bs ol NC All NC pins must be connected to nearest analog ground, to reduce the device noise sensitivity. Power Down and Reset When one channel is in Power Down Mode, the DX output will remain in high impedance state and the input on the DR will be ignored when its FS signal is active; the analog output VRO will be in high impedance. Each channel will enter the power down mode when at least one of the following conditions occurs * The PDN signal is active for more than 16 MCLK cycles (and TST is not active at the same time) * More than 4 pulses of the respective FS are missing. * MCLK is missing for a 12us. Functional Description O The TP3094 performs the complete CODEC/filter functions for four voice channels using a digital signal processing architecture. MCLK provides the clock reference to the whole circuitry and the bit clock for the PCM bus. Its value can be either 8.192MHz, 4.096MHz, 2.048MHz or 1.536/ 1.544MHz, and it is automatically selected internally. The TP3094 handles the conversion between the analog signals on the subscriber line and the PCM data samples on a PCM highway. Digital filters are used to band-limit the voice signals. The device can work in a 8 bit mode where each channel has an independently selected Time Slot, or in the 32 bit mode, where the four channels use four consecutive Time Slots. The timedivision multiplexed PCM data is transferred to the PCM highway through the standard serial PCM bus. Each channel has its dedicated Power Down input. When the PDN input is active (HIGH) for at least 16 MCLK clock cycles, the channel will go into power down mode and reset its state within a frame sync. The channel will recover from Power Down, after having detected the PDN signal inactive (LOW) for at least 16 MCLK clock cycles and after 1 frame sync pulse. This power down mode will work only in presence of the master clock at the pin MCLK. 4 www.national.com processing functions, such as PCM expansion according to the ALaw or uLaw and signal filtering. Then, for each channel it drives the Digital to Analog converter, through the proper interpolation stages and filters. Finally the signal is filtered and buffered to the output receive pin. The maximum output level voltage on the VRO pins on a load of 5kOhm+100pF is 1.12Vrms. When both the transmit and receive frame sync of a channel are missing the channel will go into Power Down Mode (if only one of them is missing the channel will not go into Power Down). A maximum of 32 frame sync pulses must be missing for power down and the channel will achieve its reset state after 32.5us. The channel will recover from power down, within the time of 4ms after the frame syncs (transmit or receive) will be active. When the device is in 32-bit mode, missing FSX0, FSR0 for 512us, will force all channels in power down mode. PCM Interface The PCM interface consists of the following signals * DX, DR - transmit and receive digital signals, carrying the pcm samples * FSX0-3, FSR0-3 - transmit and receive frame signals * TSX - output time slots signal, indicating the time slot occupied on the DX by the device * PCMMode - PCM interface select et e When the master clock MCLK is missing, all the channels will go into the Global Power Down Mode, with the lowest possible power consumption. The device will recover from this mode, when the clock signal comes back (and at least one frame sync is present), and then the active channels will operate after less than 100ms. The device will go into the same Global Power Down Mode when all the frame syncs (of all the channels, in case of 8bit mode, the FSX0, FSR0 in case of 32-bit mode) are not present or when all 4 PDN signals are active. The recovery time from this mode for the first active channel is less than 100ms. bs ol PCMMode = HIGH PCMMode = LOW 32 bit 8 bit * A/uLaw - A-law/ u-law select signal * TABLE 1. A/uLaw Coding A/uLaw = HIGH A/uLaw = LOW A-law u-law Transmit Section The transmit section input is an operational amplifier, with provision for gain adjustment using two external resistors. Only the inverting input is provided (together with the output), this allows, beside the adjustment of the gain, to implement the echo balance function with external passive components. The opamp drives the antialiasing input filter, followed by the A to D converter, which provides the digital input to the signal processing unit. The signal processing unit accepts the signal samples from each channel input stage, performs the necessary decimation and filtering function, PCM compression and provides the eight bit samples to the PCM interface block. The analog input is dc biased at the value of 2.4V. A DC decoupling is necessary between this input and the SLIC output. The maximum analog signal level, at the op-amp output, is 1.12Vrms. Maximum recommended transmit gain is 20dB (10x). * MCLK - bit clock signal O MCLK is both the system master clock and the PCM bus bit clock, and it is selected internally to be either 8.192MHz, 4.096MHz, 2.048MHz, or 1.536/ 1.544MHz. The internal clock selection is perfomed, based on the relative ratio between the frame signals (FS) and the clock signals. For proper functionality all the channel FS must have the same valid rate of 8kHz (giving a valid clock rate). In case one of the frame syncs runs other than 8kHz, the device will not function properly. Each bit on DX is clocked out on the rising edges of the bit clock (MCLK), starting from the Most Significant Bit (Sign bit). Each bit on DR is clocked in on the falling edges of the bit clock, starting from the MSB. The device may operate on to the PCM bus in two modes, selected by the input pin PCMMode; when PCMMode is "0V" the 8bit mode is selected and when PCMMode is "+5V" the 32-bit mode is selected. Receive Section This section takes the 8 bit samples from the PCM interface block and performs all the signal 5 www.national.com Functional Description (continued) ignored. In case all the channels are placed in power down, the device will still generate the FS carry output on FSX1, FSR1. For timing diagrams refer to Fig.7 and Fig.8. 8-bit Mode In the 8-bit mode, PCM data is transferred independently for each of the four channels. Each channel has its dedicated transmit and receive frame signals, which determine the time-slots to be taken on the PCM bus. Both short sync and long sync frame are supported. All the channels must have the same FS format (either short or long sync), in case a channel will have a valid frame with different FS format, the device will not function properly. In the short sync, the frame signals must be one bit long; with FSX high during a falling edge of MCLK, the next rising edge of MCLK enables the DX tristate output buffer, which will output the sign bit. The following 7 rising edges clock out the remaining 7 bits, and the next rising edge (9th) disables the DX output. With FSR high during a falling edge of MCLK, the next falling edge of MCLK latches in the sign bit. The following 7 negative edges of MCLK will then latch the remaining 7 bit of the incoming byte. In the long sync frame, the Frame signals must be at least three bits long. The DX output buffer is enabled with the rising edge of FSX or on the rising edge of MCLK, whichever comes later, and the first bit (sign) is clocked out. The following 7 rising edges of MLCK clock out the remaining 7 bits. The DX output is disabled by the 9th rising edge of MCLK. A rising edge on FSR will cause the PCM data at DR to be latched in on the next falling edges of MCLK. For timing diagrams refer to Fig.2, Fig.4, Fig.5 and Fig.6. bs ol et e Test Modes The TP3094 includes the following test modes * digital loopback * analog loopback * DC conversion These modes can be programmed per channel or for all 4 channels simultaneously. The device is programmed into any test mode by exercising the pins TST, PDN0, PDN1, PDN2, PDN3 together. The signals to this pins must be stable for at least 16 MCLK cycles before the device enters any selected test mode. When exiting the test mode, the PDN must return to the previous state to resume the original operating state. During any test mode (TST=1), it will not be possible to change the PU/PD state for any channel not involved in the test mode configuration (e.g. not in test mode). The channel(s) under test must be placed in power up prior the test mode selection, in case left in power down, any programmed test mode will not be operational. When the device exits the test mode, normal operation will return, and the PU/PD programmability will be available, by the state of the PDN signals. The programming of the test modes is according to the table below. The digital loopback is a bit true feedback from the PCM highway to the PCM highway, performed exactly at the PCM internal interface. Each byte is looped back from RX to TX on the programmed time slot (FS). The analog output is forced to 0Vac level (typically 2.4Vdc), with low output impedance. O 32-bit Mode In the 32-bit mode, the four PCM data bytes of the four channels are treated as a single 32-bit data word. The PCM transfer is started by the positive pulses on the transmit or receive frame sync (FSX0, FSR0) inputs. The following 32 negative edges of MCLK will then latch the input PCM data at DR, for all 4 channel starting from channel 0; while the positive edges will clock out the transmit PCM data at DX, from channel 0 to channel 3. In this mode the pins FSX1 and FSR1 become the frame signal carry-out signals, providing a singlebit-long frame pulse during the last bit of the 32bit stream and allowing another TP3094 to be connected in 32-bit mode. In case any channel is powered down (through the PDN pin) during its assigned time slot the DX pin will be set in tristate and the DR signal will be The analog loopback is performed from the output of the D/A converter (before the output amplifier) and the input of the A/D, so the RX signal is looped back towards the TX direction, through the device. The analog output is at 0Vac level, with high output impedance. In the DC conversion mode, the channel under test is programmed to transfer any DC signal (within the available range) in the TX direction, from the analog GXO to the DX digital output, by 6 www.national.com Functional Description (continued) bypassing the low frequency filter. Test Modes Normal Operation Single Channel Digital Loopback Single Channel Analog Loopback Single Channel DC Conversion 4 Channels Digital Loopback 4 Channels Analog Loopback 4 Channels DC Conversion Invalid States TST 0 1 1 1 1 1 1 1 PDN0 x 1 0 1 0 0 0 0 PDN1 x 1 1 0 0 0 0 0 PDN2 x A0 A0 A0 0 0 1 1 PDN3 x A1 A1 A1 0 1 0 1 Description Ch. select with PDN2, PDN3 Ch. select with PDN2, PDN3 Ch. select with PDN2, PDN3 Channel Selected Channel 0 Channel 1 Channel 2 Channel 3 et A1 0 0 1 1 O bs ol A0 0 1 0 1 e Where A0, A1 select the channel under test, according to the following table 7 www.national.com Timing Diagrams MCLK 125S FSX3 or FSR3 FSX2 or FSR2 FSX0 or FSR0 D7 CH3 D0 D7 CH2 D0 D7 CH1 DR D7 CH3 D0 D7 CH2 D0 D7 CH1 D0 D7 CH0 D0 e DX CH0 D7 D0 et D0 TSX bs ol FIGURE 2. Timing diagram for PCM Interface, 8-bit mode (Long Frame Sync) tWMH tPM tFM MCLK tRM tWML FIGURE 3. MCLK Timing TSX tTSZC O tDBTS MCLK 1st tHBFL 2nd 3rd 4th 5th 6th 7th 8th 9th tSBF FSX/FSR tZDF tZDF DX tDZC tDBD D7 (Sign) D6 (MSB) t SDB DR D7 (Sign) D6 (MSB) D4 D5 D2 D3 D1 D0 (LSB) tHDB D5 D4 D3 D2 D1 D0 (LSB) FIGURE 4. Timing diagram for PCM Interface, 8-bit mode (Long Frame Sync) 8 www.national.com Timing Diagrams (continued) MCLK 125S FSX3 or FSR3 FSX2 or FSR2 D7 CH3 D0 D7 CH2 DR D7 CH3 D0 D7 CH2 D0 CH1 D7 D7 D0 D0 CH1 CH0 D7 bs ol TSX D7 D0 D0 et DX e FSX0 or FSR0 CH0 D0 FIGURE 5. Timing diagram for PCM Interface, 8-bit mode (Short Frame Sync) TSX tTSZC tDBTS MCLK O 1st FSX or t SF 2nd 3rd 5th 4th 6th 7th 9th 8th tHF FSR tDBD DX tDBD D7 (Sign) tDZC D6 (MSB) t SDB DR D7 (Sign) D6 (MSB) D4 D5 D2 D3 D1 D0 (LSB) tHDB D5 D4 D3 D2 D1 D0 (LSB) FIGURE 6. Timing diagram for PCM Interface, 8-bit mode (Short Frame Sync) for each channel 9 www.national.com Timing Diagrams (continued) MCLK 125S FSX0 or FSR0 FSX1 or FSR1 DR e D7CH0 D0 D7 CH1 D0 D7 CH2 D0 D7 CH3 D0 DX et D7CH0 D0 D7 CH1 D0 D7 CH2 D0 D7 CH3 D0 bs ol TSX FIGURE 7. Timing diagram for PCM Interface, 32-bit mode TSX tTSZC tDBTS MCLK O 1st FSX0 or tSF 2nd 3rd 33th 32th 5th 4th tHF tDOFL FSR0 tDOFH FSX1 or FSR1 tDBD tDBD DX D7-0 (Sign) D6-0 (MSB) tDZC tSDB DR D7-0 (Sign) D6-0 (MSB) D0-3 (LSB) D4-0 D5-0 tHDB D5-0 D4-0 D1-3 D0-3 (LSB) FIGURE 8. Timing diagram for PCM Interface, 32-bit mode 10 www.national.com Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. 7V VCC to DGND Voltage at any digital inputs or outputs VCC +0.3V to DGND -0.3V Voltage at any analog inputs or outputs VCC +0.3V to AGND-0.3V Storage temperature range -65oC to +150oC Lead temperature(Soldering, 10 Sec) 260oC ESD (human body model) 2000 V Latch-up immunity on any pin 200 mA Electrical Characteristics Conditions All digital inputs Min Typ et Digital Interface Symbol Parameter Input low voltage VIL e Unless otherwise noted, limits printed in bold characters are guaranteed for VCC(all supplies)=5.0V5%, DGND=AGND=0V, TA=-40C to 85C by correlation with 100% electrical testing at TA=25C. All other limits are assured by correlation with other production tests and/or product design and characterization. All digital signals are referenced to DGND, and all analog signals are referenced to AGND. Typical are specified at VCC=+5V, TA=25C. Max 0.8 Input high voltage All digital inputs VOL Output low voltage IL=2mA 0.4 V VOH Output high voltage IIL Input low current IL=-2mA IL=-100uA DGND<VIN<VIL, all digital inputs 2.4 3.5 -10 10 V V A Input high current VIH<VIN<VCC, all digital inputs -10 10 A Output current in high impedance state Input Capacitance DGND<VO<VCC (DX) -10 10 A 10 pF 200 nA IOZ Ci bs ol VIH IIH Analog Interface Input leakage current IXI RXI CXI Input capacitance 1V<VXI<4V, all analog inputs Transmit input common mode voltage range Receive input common mode voltage range Output resistance O VCMXI Input resistance 1V<VXI<4V, all analog inputs in Power UP mode 1V<VXI<4V, all analog inputs VCMXO RRO RROZ 2.2 Units V -200 RLRO 0.7V<VRO<4.1V, VROi CLRO Load capacitance VRO AVXA Voltage Gain VXI to GXO,RL on GXO>10k FUXA Unity Gain Bandwidth RLGXO Load resistance 0.7V<VGX<4.1V, GXOi CLGXO Load capacitance GXO VRO RX output drive level RL=5000 M 10 10 pF -10% 2.375 +10% V -10% 2.375 +10% V 5 10 All analog outputs Output resistance in PDN Load resistance V 2000 5000 100 5000 1 2 MHz 10000 50 1.12 11 pF V/V pF Vrms www.national.com Electrical Characteristics (continued) Parameter Power Dissipation ICC0 Power down current (all channels down) ICC1 Power up active current (all channel active) Amplitude Response Absolute Levels tmax Virtual decision value defined per ITU G.711 Conditions Min Typ Max Units Measured after having first achieved power-up state. MCLK=2.048MHz No load, MCLK=2.048MHz 0.9 1.5 mA 35 50 mA Nominal 0dBm0 level is 0dBm at the analog inputs/outputs Max overload level 3.17dBm0 (-law) 3.14dBm0 (A-law) 0.7746 Vrms e Symbol 1.116 1.112 Vrms Vrms 0.15 dB dB dB Transmit gain, absolute TA=25oC, VCC=5V, Input at VXI=0dBm0 at 1015.625Hz -0.15 GXAT/V Cumulative Transmit gain Variation with supplies and temperature ranges TA=0oC to 70oC, VCC=5V5%, -0.2 0.2 -0.3 0.3 Transmit gain variation with level O GXAL Transmit gain, relative to GXA oC +85oC, VCC=5V5% TA=-40 to Input at GXO=0dBm0 at 1015.625Hz f=16Hz f=50Hz f=60Hz f=200Hz f=300-3000Hz f=3300Hz f=3400Hz f=4000Hz f=4.6KHz and up (Note 2), measure response from 0 to 4000Hz Sinusoidal test method, reference level = -10dBm0 at VXI GXO=-40dBm0 to +3dBm0 GXO=-50dBm0 to -40dBm0 GXO=-55dBm0 to -50dBm0 bs ol GXR et GXA -35 -30 -30 0 0.15 0.15 0 -14 -32 dB dB dB dB dB dB dB dB dB dB -0.2 -0.4 -1.0 -0.15 0.2 0.4 1.0 0.15 dB dB dB dB dB -1.8 -0.15 -0.35 -0.7 GRA Receive gain, absolute TA=25oC, VCC=5V5% Input PCM level at DR=0dBm0 at 1015.625Hz GRAT/V Cumulative Receive gain Variation with supplies and temperature ranges TA=0oC to 70oC, VCC=5V5%, -0.2 0.2 TA=-40oC -0.3 0.3 -0.15 -0.35 -0.7 0.15 0.15 0 -14 GRR Receive gain, relative to GRA 85oC, to VCC=5V5%, Input PCM level at DR=0dBm0 at 1015.625Hz f=0-3000Hz f=3300Hz f=3400Hz f=4000Hz 12 dB dB dB dB www.national.com Electrical Characteristics (continued) Symbol Parameter Conditions Min GRAL Receive gain variation with level Sinusoidal test method, PCM level=-40dBm0 to +3dBm0 PCM Level=-50dBm0 to -40dBm0 PCM Level=-55dBm0 to -50dBm0 Typ -0.2 -0.4 -1.0 Max Units 0.2 0.4 1.0 dB dB dB Note 2: Measure voiceband image signal, stimulus signal level is -25dBm0. Transmit signal to total distortion Sinusoidal test method, A-law (psophometric filter), u-Law (C message filter), FSX=FSR, fXI=1015.625Hz GXO=+3dBm0 GXO=0 to -30dBm0 GXO= -40dBm0 GXO= -45dBm0 GXO= -50dBm0 GXO= -55dBm0 Sinusoidal test method, PCM code for all channels equals to positive zero, FSX=FSR, fXI=1015.625Hz, GXO=0dBm e Distortion STDXP bs ol STDRP Receive signal to total distortion Receive single frequency distortion O SFDR et Transmit single frequency distortion SFDX SOSRS Receive spurious out of band signals dB dB dB dB dB dB 33 36 29 25 20 14 Sinusoidal test method, A-law, (psophometric filter), u-Law (C message filter), FSX=FSR, f=1015.625Hz, PCM level=+3dBm0 PCM level=0 to -30dBm0 PCM level=-40dBm0 PCM level=-45dBm0 PCM level=-50dBm0 PCM level= -55dBm0 Sinusoidal test method, PCM code for all channels equals to 0dBm0, FSX=FSR, f=1015.625Hz, GXO=0Vrms Single frequency, PCM code for all channels equals 0 dBm0, 300Hz-3.4KHz, FSX=FSR, GXO=0Vrms f=4.6KHz-7.6KHz f=7.6KHz-8.4KHz f=8.4KHz-100KHz 13 -46 33 36 29 25 20 15 dB dB dB dB dB dB -46 dB -30 -40 -30 dB dB dB www.national.com Electrical Characteristics (continued) Envelope delay distortion Transmit delay, absolute DXA Transmit delay, relative to DXA DXR DRA Receive delay, absolute DRR Receive delay, relative to DRA Noise NXP Transmit Idle channel noise, A-law Transmit Idle channel noise, -law NRP NRC Receive Idle channel noise, A-law Receive Idle channel noise, -law Analog to Analog Noise O NXR Min Typ Max Units f=1400Hz, 275 330 S GXO=-10dBm0 f=500-600Hz f=600-1000Hz f=1000-2600Hz f=2600-2800Hz f=1400Hz, 150 85 50 80 112 220 145 100 140 220 s s s s PCM level=-10dBm0 f=500-600Hz f=600-1000Hz f=1000-2600Hz f=2600-2800Hz f=2800-3000Hz -40 -40 Psophometric weighted, PCM code for all channels equals to positive zero, FSX=FSR, GXO=0Vrms C-message weighted, PCM code for all channels equals to alternating positive and negative zeros, FSX=FSR, GXO=0Vrms Psophometric weighted, PCM code for all channels equals to positive zero, FSX=FSR, GXO=0Vrms C-message weighted, PCM code for all channels equals to alternating positive and negative zeros, FSX=FSR, GXO=0Vrms DX connected to DR, f=0-100kHz FSX=FSR, GXO=0Vrms bs ol NXC Conditions Power supply rejection Positive power supply PPSRX rejection, transmit PPSRR Positive power supply rejection, receive S -15 -10 75 105 145 90 125 175 s s s s s -73 -69 dBm0p 12 16 dBrnC0 -83 -79 dBm0p 7 11 dBrnC0 -70 -53 dBm0 e Parameter et Symbol PCM code for all channels equals to positive zero, A-law, FSX=FSR, GXO=0Vrms, VCC=5.0V+100mVrms f=0-4000Hz f=4.6KHz-25KHz PCM code for all channels equals to positive zero, A-law, FSX=FSR, GXO=0Vrms, VCC=5.0V+100mVrms 40 40 45 45 dB dB f=0-4000Hz f=4.6KHz-25KHz 40 40 45 45 dB dB 14 www.national.com Electrical Characteristics (continued) Symbol Parameter Conditions Min Typ Max Units CTR-X Receive to transmit crosstalk (Intra-channel Crosstalk) CTFEX Far end crosstalk with analog stimulus (Interchannel crosstalk) PCM code for stimulated channel equals to 0dBm0, 300Hz3.4KHz, PCM code for all other channels equals to positive zero, FSX=FSR, Measure PCM response. PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, f=750Hz All other channels GXO=0Vrms -80 -75 dB -80 -73 dB CTNEX Near end crosstalk with digital stimulus (Interchannel crosstalk) PCM code for stimulated channel equals to 0dBm0, f=750Hz, PCM code for all other channels equals to positive zero, FSX=FSR, All other channels GXO=0Vrms -80 -73 dB CTX-R Transmit to receive crosstalk (Intra-channel crosstalk) PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, 300Hz-3.4KHz, all other channels GXO=0Vrms, -80 -75 dB bs ol et e Crosstalk Far end crosstalk with digital stimulus (Interchannel crosstalk) PCM code for stimulated channel equals to 0dBm0, f=750Hz, PCM code for all other channels equals to positive zero, FSX=FSR, All other channels GXO=0Vrms -80 -76 dB CTNEX Near end crosstalk with analog stimulus (Interchannel crosstalk) PCM code for all channels equals to positive zero, FSX=FSR, Stimulating signal GXO=0dBm0, f=750Hz All other channels GXO=0Vrms -80 -76 dB O CTFER 15 www.national.com Timing Specifications Symbol Parameter Conditions Min Typ Max Units 60 MHz MHz MHz MHz MHz % 10 ns 10 ns Clock and Data Timing All timing parameters are measured at VOH=2.0V and VOL=0.7V DCMCLK MCLK Duty Cycle tRM Rise time of MCLK tFM Fall time of MCLK tSDB Setup time DR valid to MCLK low Hold time DR valid from MCLK low Delay from MCLK high to DX valid Delay from MCLK high to DX disabled Delay from MCLK high to TSX disabled tHDB tDBD tDZC tDBTS tPDN tSF tHF 40 CL=100pF+2LSTTL loads Delay time to TSX low ns 20 ns ns CL=100pF+2LSTTL loads 20 ns CL=100pF+2LSTTL loads 20 ns 0 50 ns CL = 0pF to 150pF PDN persistence Set-up Time from FS to MCLK Low Hold Time from MCLK Low to FS Low 20 45 bs ol tTSZC 1.536 1.544 2.048 4.096 8.192 e Frequency of MCLK et 1/tPM 16xtPM Short Frame Sync Pulse 20 ns Short Frame Sync Pulse 20 ns Long Frame Timing Parameter Conditions Min tHBFL Holding time from Clock to Frame Sync Set-up time from Frame Sync to Clock low Delay time Valid Data from FS or MCLK, whichever comes later Long Frame Only 10 ns Long Frame Only 35 ns O Symbol tSBF tZDF CL = 0pF to 150pF Typ Max 50 Units ns Note: when measuring signals going to TRI-STATE(R), the timing delay is measured when the signal is 10% away from the starting level. 16 www.national.com Applications Information System Bus +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip Ring VRO0 GX11 Tip VXI1 SLIC Zb Ring VRO1 GX2 Tip VXI2 SLIC Zb Ring VRO2 Tip T P 3 0 9 4 SLIC FSX1 FSR1 PDN1 FSX2 FSR2 PDN2 FSX3 FSR3 PDN3 PCM Mode VXI3 Ring PDN0 et GX3 FSX0 FSR0 e SLIC Zb Zb TSX VRO3 MCLK NF A/ULaw AGND0 AGND1 5V (A-law) DGND (u-law) bs ol DGND O FIGURE 9. Typical application in a non cascaded mode 17 www.national.com Applications Information To additional TP3094 COMBOs +5V Supply System Bus AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip SLIC Zb Ring FSX0 VRO0 GX11 Tip VXI1 SLIC Zb Ring VRO1 GX2 Tip Zb Ring PDN0 FSX1 FSR1 PDN1 FSX2 FSR2 PDN2 e VXI2 SLIC FSR0 T P 3 0 9 4 FSX3 FSR3 PDN3 VRO2 GX3 5V Tip SLIC Ring et VXI3 PCM Mode Zb TSX VRO3 MCLK NF A/ULaw AGND0 5V (A-law) DGND (u-law) AGND1 bs ol DGND +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip SLIC Zb Ring FSX0 VRO0 GX11 Tip VXI1 SLIC Zb Ring VRO1 GX2 Tip PDN0 FSX1 FSR1 PDN1 FSX2 FSR2 PDN2 VXI2 O SLIC Zb Ring SLIC FSX3 FSR3 PDN3 VRO2 GX3 5V Tip Ring FSR0 T P 3 0 9 4 VXI3 PCM Mode Zb TSX VRO3 MCLK NF DGND A/ULaw AGND0 5V (A-law) DGND (u-law) AGND1 FIGURE 10. TP3094 in a cascade mode 18 www.national.com e et bs ol 44-Lead Molded Plastic Chip Carrier (PLCC) Order Number TP3094V NS Package Number V44A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: O TP3094 Quad PCM Codec/Filter Physical Dimensions inches (millimeters) unless otherwise noted 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be National Semiconductor Corporation Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety. National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 National Semiconductor Asia Pacific Customer Response Group Tel: 65-254-4466 Fax: 65-250-4466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specification. 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