CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
BiCMOS Technology With Low Quiescent
Power
D
Buffered Inputs
D
Inverted Outputs
D
Input/Output Isolation From VCC
D
Controlled Output Edge Rates
D
48-mA Output Sink Current
D
Output Voltage Swing Limited to 3.7 V
D
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D
Packaged in Standard Plastic DIP
description
The CD74FCT844A is a 9-bit, D-type latch with
3-state outputs, designed specifically for driving
highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.
The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS
transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing
(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC
bounce and ground bounce and their effects during simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking 48 mA.
The CD74FCT844A outputs are transparent to the inputs when the latch-enable (LE) input is high. When LE
goes low , the data is latched. The output-enable (OE) input controls the 3-state outputs. When OE is high, the
outputs are in the high-impedance state. The latch operation is independent of the state of OE. This device,
having preset (PRE) and clear (CLR), is ideal for parity-bus interfacing. When PRE is low , the outputs are high
if OE is low. PRE overrides CLR. When CLR is low, the outputs are low if OE is low. When CLR is high, data
can be entered into the latch.
OE can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the
high-impedance state. The outputs also are in the high-impedance state during power-up and power-down
conditions. The outputs remain in the high-impedance state while the device is powered down. In the
high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
The CD74FCT844A is characterized for operation from 0°C to 70°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
PRE CLR OE LE DQ
L X L X X H
HLLXX L
HHLHL H
HHLHH L
HHLLX Q
0
X X H X X Z
logic symbol†
EN
1
7
6D 8
7D 9
8D 10
9D
1D
2
1D
18
17
16
15
23
3
2D 4
3D 5
4D 6
5D
22
21
20
19
S2
14
R
11
C1
13
LE
OE
PRE
CLR
2
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
OE
PRE
1Q
CLR
LE
To Eight Other Channels
1
14
11
13
223
S2
C1
1D
R
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
DC supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input clamp current, IIK (VI < –0.5 V) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output clamp current, IOK (VO < –0.5 V) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output sink current per output pin, IOL 70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output source current per output pin, IOH –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC, (ICC) 237 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through GND 453 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1) 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 2)
MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
IOH High-level output current –15 mA
IOL Low-level output current 48 mA
∆t/∆vInput transition rise or fall rate 0 10 ns/V
TAOperating free-air temperature 0 70 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN MAX
MIN
MAX
UNIT
VIK II = –18 mA 4.75 V –1.2 –1.2 V
VOH IOH = –15 mA 4.75 V 2.4 2.4 V
VOL IOL = 48 mA 4.75 V 0.55 0.55 V
IIVI = VCC or GND 5.25 V ±0.1 ±1
m
A
IOZ VO = VCC or GND 5.25 V ±0.5 ±10
m
A
IOS†VI = VCC or GND, VO = 0 5.25 V –75 –75 mA
ICC VI = VCC or GND, IO = 0 5.25 V 8 80
m
A
∆ICC‡One input at 3.4 V,
Other inputs at VCC or GND 5.25 V 1.6 1.6 mA
CiVI = VCC or GND 10 10 pF
CoVO = VCC or GND 15 15 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
‡This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating temperature conditions (unless otherwise
noted) (see Figure 1)
MIN MAX UNIT
CLR low 8
twPulse duration PRE low 8ns
LE low 4
Data before LE↓2.5
tsu Setup time PRE inactive 2.5 ns
CLR inactive 2.5
thHold time Data before LE↓2.5 ns
trec Recovery time PRE, CLR 14 ns
switching characteristics over recommended operating temperature conditions (unless otherwise
noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT) (OUTPUT) TYP
MIN
MAX
UNIT
td
D
Q
7.5 1.5 10
ns
t
pd LE
Q
9 1.5 12
ns
tPLH PRE
Q
9 1.5 12
ns
tPHL CLR
Q
9.8 1.5 13
ns
ten OE Q 10.5 1.5 14 ns
tdis OE Q 6 1.5 8 ns
CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 1 V
VOH(V) Quiet output, minimum dynamic VOH 0.5 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
CD74FCT844A
BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS728 – JULY 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
1.5 V1.5 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V ≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
7 V
Open
7 V
TEST S1
3 V
0 V
1.5 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 7 V
500 ΩGND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V1.5 V
500 Ω
500 Ω
1.5 V 1.5 V
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.5 V
1.5 V 10%10% 90% 90% 3 V
0 V
trtf
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
