N04L1630C2B AMI Semiconductor, Inc. ULP Memory Solutions 670 North McCarthy Blvd. Suite 220 Milpitas, CA 95035 PH: 408-935-7777, FAX: 408-935-7770 Advance Information 4Mb Ultra-Low Power Asynchronous CMOS SRAMs 256K x 16 bit POWER SAVER TECHNOLOGY TM Overview Features The N04L1630C2B is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits. The device is designed and fabricated using AMI Semiconductor's advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The N04L1630C2B is optimized for the ultimate in low power and is suited for various applications where ultra-lowpower is critical such as medical applications, battery backup and power sensitive hand-held devices. The unique page mode operation saves operating power while improving the performance over standard SRAMs. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 256Kb x 16 SRAMs. * Wide Power Supply Range 2.7 to 3.6 Volts * Very low standby current 1uA (Typical) * Very low operating current 2.0mA at 1s (Typical) * Very low Page Mode operating current 0.8mA at 1s (Typical) * Simple memory control Dual Chip Enables (CE1 and CE2) Byte control for independent byte operation Output Enable (OE) for memory expansion * Very fast output enable access time 30ns OE Access Time 55ns Random Access Time 30ns Page Mode Access Time * Automatic power down to standby mode * TTL compatible three-state output driver * RoHS Compliant TSOP and BGA packages Product Family Part Number Package Type N04L1630C2BB2 48-BGA Green N04L1630C2BT2 44-TSOP II Green Operating Temperature Power Supply (Vcc) Speed Options -40oC to +85oC 2.7V - 3.6V 55ns 70ns Standby Operating Current (ISB), Current (Icc), Typical Typical 1A 2 mA @ 1MHz (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 1 N04L1630C2B AMI Semiconductor, Inc. Advance Information Pin Configurations (4Mb) A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN ONE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CE2 A8 A9 A10 A11 A17 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B I/O8 UB A3 A4 CE1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 48 Pin BGA (top) TSOP II Pin Descriptions Pin Name Pin Function A0-A17 Address Inputs WE CE1 CE2 OE LB UB I/O0-I/O7 Write Enable Input Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Lower Byte Data Input/Output I/O8-I/O15 Upper Byte Data Input/Output VCC Power VSS Ground NC Not Connected (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Functional Block Diagram Word Address Decode Logic Address Inputs A0, A5 - A17 Page Address Decode Logic CE1 CE2 WE OE UB LB Control Logic 16K Page x 16 word x 16 bit RAM Array Input/ Output I/O0 - I/O7 Mux and Buffers I/O8 - I/O15 Word Mux Address Inputs A1 - A4 Functional Description CE1 CE2 WE OE UB LB I/O0 - I/O151 MODE POWER H X X X X X High Z Standby2 Standby Standby X L X X X X High Z Standby2 L H X X H H High Z Standby Standby L X3 1 L L 1 Data In Write3 Active L L1 L1 Data Out Read Active H L1 1 High Z Active Active L L L H H H H H L 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. Capacitance1 Item Symbol Test Condition Input Capacitance CIN CI/O I/O Capacitance Max Unit VIN = 0V, f = 1 MHz, TA = 25oC 8 pF 25oC 8 pF VIN = 0V, f = 1 MHz, TA = Min 1. These parameters are verified in device characterization and are not 100% tested (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Absolute Maximum Ratings1 Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT -0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC -0.3 to 4.5 V Power Dissipation PD 500 mW Storage Temperature TSTG -40 to 125 o Operating Temperature TA -40 to +85 oC Soldering Temperature and Time TSOLDER 260oC, 10sec oC C 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Test Conditions Min. Typ1 Max Unit 2.7 3.0 3.6 V Item Symbol Supply Voltage VCC Data Retention Voltage VDR Input High Voltage VIH 0.7Vcc VCC+0.3 V Input Low Voltage VIL -0.3 0.6 V Output High Voltage VOH Chip Disabled3 IOH = -100uA IOH = -1mA 1.8 V VCC-0.2 V 2.4 V IOL = 100uA 0.2 IOL = 2.1mA 0.4 V Output Low Voltage VOL Input Leakage Current ILI VIN = 0 to VCC 0.5 A Output Leakage Current ILO OE = VIH or Chip Disabled 0.5 A Read/Write Operating Supply Current @ 1 s Cycle Time2 ICC1 VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 2.5 3.0 mA Read/Write Operating Supply Current @ 70 ns Cycle Time2 ICC2 VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 10 15.0 mA Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation) ICC3 VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 4 8 mA ISB1 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V 1 10.0 A 5 A Maximum Standby Current3 Maximum Data Retention Current3 IDR Vcc = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 1. Typical values are measured at Vcc=Vcc Typ., TA=25C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Power Savings with Page Mode Operation (WE = VIH) Page Address (A0, A5 - A17) Word Address (A1 - A4) Open page Word 1 Word 2 ... Word 16 CE1 CE2 OE LB, UB Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A1-A4 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30pF Operating Temperature -40 to +85 oC Timing -55 -70 Units Item Symbol Read Cycle Time tRC Address Access Time tAA 55 70 ns Page Mode Address Access Time tAAP 30 35 ns Chip Enable to Valid Output tCO 55 70 ns Output Enable to Valid Output tOE 30 35 ns Byte Select to Valid Output tBE 55 70 ns Chip Enable to Low-Z output tLZ 10 10 ns Output Enable to Low-Z Output tOLZ 5 5 ns Byte Select to Low-Z Output tBZ 10 10 ns Chip Disable to High-Z Output tHZ 0 20 0 20 ns Output Disable to High-Z Output tOHZ 0 20 0 20 ns Byte Select Disable to High-Z Output tBHZ 0 20 0 20 ns Output Hold from Address Change tOH 10 10 ns Write Cycle Time tWC 55 70 ns Chip Enable to End of Write tCW 45 50 ns Address Valid to End of Write tAW 45 50 ns Byte Select to End of Write tBW 45 50 ns Write Pulse Width tWP 40 40 ns Address Setup Time tAS 0 0 ns Write Recovery Time tWR 0 0 ns Write to High-Z Output tWHZ Data to Write Time Overlap tDW 40 40 ns Data Hold from Write Time tDH 0 0 ns End Write to Low-Z Output tOW 5 5 ns Min. Max. 55 Min. Max. 70 20 ns 20 ns (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA tHZ CE1 tCO CE2 tLZ tOHZ tOE OE tOLZ tBE LB, UB tBLZ Data Out High-Z tBHZ Data Valid (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Timing Waveform of Page Mode Read Cycle (WE = VIH) tRC Page Address (A0, A5 - A17) tAAP tAA Word Address (A1 - A4) tHZ CE1 tCO CE2 tOE tOHZ OE tOLZ tBE LB, UB Data Out tBLZ High-Z tBHZ (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Timing Waveform of Write Cycle (WE control) tWC Address tWR tAW CE1 tCW CE2 tBW LB, UB tAS tWP WE tDW High-Z tDH Data Valid Data In tWHZ tOW High-Z Data Out Timing Waveform of Write Cycle (CE1 Control) tWC Address tAW CE1 (for CE2 Control, use inverted signal) tWR tCW tAS tBW LB, UB tWP WE tDW Data Valid Data In tLZ Data Out tDH tWHZ High-Z (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information 44-Lead TSOP II Package (T44) 18.410.13 11.760.20 10.160.13 0.80mm REF DETAIL B 0.45 0.30 SEE DETAIL B 1.100.15 0o-8o 0.20 0.00 0.80mm REF Note: 1. All dimensions in inches (Millimeters) (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Advance Information Ball Grid Array Package 0.280.05 1.240.10 D A1 BALL PAD CORNER (3) 1. 0.350.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. SD e SE 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e BOTTOM VIEW (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. Z N04L1630C2B AMI Semiconductor, Inc. Advance Information Ordering Information N04L1630C2BX-XX I Performance Package Type 55 = 55ns 70 = 70ns B2 = 48-ball BGA Green (RoHS Compliant) T2 = 44-pin TSOP II Green (RoHS Compliant) Revision History Revision Date Change Description A April 2003 Initial Advanced Release B August 2004 Changed part number to -30 from -3W and Vcc range to 2.7 V - 3.6V C January 2005 Change IDR = 5 A, ICC(typ) = 2.5mA. Modified page mode address A1-A4 configuration. D January 2005 General Update E March 22, 2005 Changed tWP and tDW to 40ns for -55 and -70, to 45ns for -85 F June 9, 2005 Added TSOP II Green Package Ordering Option G Dec. 2005 Added RoHS Compliant H July 2006 Added BGA package I September 2006 Converted to AMI Semiconductor (c) 2006 AMI Semiconductor, Inc. All rights reserved. AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be expected to result in significant injury or death, including life support systems and critical medical instruments. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.