N04L1630C2BT2 - AMI Semiconductor, Inc.

N04L1630C2B

(DOC# 14-02-042 ReI I ECN# 01-1374 1

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

Advance Information

AMI Semiconductor, Inc.

ULP Memory Solutions

670 North McCarthy Blvd. Suite 220

Milpitas, CA 95035

PH: 408-935-7777, FAX: 408-935-7770

4Mb Ultra-Low Power Asynchronous CMOS SRAMs

256K × 16 bit POWER SAVER TECHNOLOGY TM

Overview

The N04L1630C2B is an integrated memory

device containing a 4 Mbit Static Random Access

Memory organized as 262,144 words by 16 bits.

The device is designed and fabricated using AMI

Semiconductor’s advanced CMOS technology to

provide both high-speed performance and ultra-low

power. The device operates with two chip enable

(CE1 and CE2) controls and output enable (OE) to

allow for easy memory expansion. Byte controls

(UB and LB) allow the upper and lower bytes to be

accessed independently and can also be used to

deselect the device. The N04L1630C2B is

optimized for the ultimate in low power and is

suited for various applications where ultra-low-

power is critical such as medical applications,

battery backup and power sensitive hand-held

devices. The unique page mode operation saves

operating power while improving the performance

over standard SRAMs. The device can operate

over a very wide temperature range of -40oC to

+85oC and is available in JEDEC standard

packages compatible with other standard 256Kb x

16 SRAMs.

Features

• Wide Power Supply Range

2.7 to 3.6 Volts

• Very low standby current

1uA (Typical)

• Very low operating current

2.0mA at 1µs (Typical)

• Very low Page Mode operating current

0.8mA at 1µs (Typical)

• Simple memory control

Dual Chip Enables (CE1 and CE2)

Byte control for independent byte operation

Output Enable (OE) for memory expansion

• Very fast output enable access time

30ns OE Access Time

55ns Random Access Time

30ns Page Mode Access Time

• Automatic power down to standby mode

• TTL compatible three-state output driver

• RoHS Compliant TSOP and BGA packages

Product Family

Part Number Package Type Operating

Temperature

Power

Supply (Vcc)

Speed

Options

Standby

Current (ISB),

Typical

Operating

Current (Icc),

Typical

N04L1630C2BB2 48-BGA Green

-40oC to +85oC2.7V - 3.6V 55ns

70ns 1µA 2 mA @ 1MHz

N04L1630C2BT2 44-TSOP II Green

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Pin Configurations (4Mb)

Pin Descriptions

Pin Name Pin Function

A0-A17 Address Inputs

WE Write Enable Input

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

OE Output Enable Input

LB Lower Byte Enable Input

UB Upper Byte Enable Input

I/O0-I/O7 Lower Byte Data Input/Output

I/O8-I/O15 Upper Byte Data Input/Output

VCC Power

VSS Ground

NC Not Connected

ONE

CE1

I/O0

I/O1

I/O2

I/O3

VCC

VSS

I/O4

I/O5

I/O6

I/O7

A16

A15

A14

A13

A12

I/O15

I/O14

I/O13

I/O12

VSS

VCC

I/O11

I/O10

I/O9

I/O8

CE2

A10

A11

A17

TSOP II

123456

ALB OE A0 A

1 A2 CE2

BI/O8 UB A3 A

4 CE1 I/O0

CI/O9 I/O10 A

5 A

6 I/O1 I/O2

DVSS I/O11 A

17 A7I/O3VCC

EVCC I/O12 NC A16 I/O4VSS

FI/O14 I/O13 A14 A15 I/O5I/O6

GI/O15 NC A12 A13 WE I/O7

HNC A8A9A10 A11 NC

48 Pin BGA (top)

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Functional Block Diagram

Functional Description

CE1 CE2 WE OE UB LB I/O0 - I/O151

1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7

are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.

MODE POWER

HXXXXX High Z Standby2

2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally

isolated from any external influence and disabled from exerting any influence externally.

Standby

XLXXXX High Z Standby2Standby

L H X X H H High Z Standby Standby

LHL

3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

L1L1Data In Write3Active

LHHL

L1L1Data Out Read Active

LHHH

L1L1High Z Active Active

Capacitance1

1. These parameters are verified in device characterization and are not 100% tested

Item Symbol Test Condition Min Max Unit

Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC8pF

I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC8pF

Address

Inputs

A1 - A4

Address

Inputs

A0,

A5 - A17

Word

Address

Decode

Logic

16K Page

x 16 word

x 16 bit

RAM Array

Word Mux

Input/

Output

Mux

and

Buffers

Page

Address

Decode

Logic

Control

Logic

CE1

CE2

I/O0 - I/O7

I/O8 - I/O15

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Absolute Maximum Ratings1

1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

Item Symbol Rating Unit

Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC+0.3 V

Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V

Power Dissipation PD500 mW

Storage Temperature TSTG –40 to 125 oC

Operating Temperature TA-40 to +85 oC

Soldering Temperature and Time TSOLDER 260oC, 10sec oC

Operating Characteristics (Over Specified Temperature Range)

Item Symbol Test Conditions Min. Typ1

1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.

Max Unit

Supply Voltage VCC 2.7 3.0 3.6 V

Data Retention Voltage VDR Chip Disabled31.8 V

Input High Voltage VIH 0.7Vcc VCC+0.3 V

Input Low Voltage VIL –0.3 0.6 V

Output High Voltage VOH

IOH = -100uA VCC–0.2 V

IOH = -1mA 2.4 V

Output Low Voltage VOL

IOL = 100uA 0.2 V

IOL = 2.1mA 0.4

Input Leakage Current ILI VIN = 0 to VCC 0.5 µA

Output Leakage Current ILO OE = VIH or Chip Disabled 0.5 µA

Read/Write Operating Supply Current

@ 1 µs Cycle Time2

2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance

expected in the actual system.

ICC1

VCC=VCCMax, VIN=VIH or VIL

Chip Enabled, IOUT = 0 2.5 3.0 mA

Read/Write Operating Supply Current

@ 70 ns Cycle Time2ICC2

VCC=VCCMax, VIN=VIH or VIL

Chip Enabled, IOUT = 0 10 15.0 mA

Page Mode Operating Supply Current

@ 70ns Cycle Time2 (Refer to Power

Savings with Page Mode Operation)

ICC3

VCC=VCCMax, VIN=VIH or VIL

Chip Enabled, IOUT = 0 48mA

Maximum Standby Current3

3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within

0.2 volts of either VCC or VSS.

ISB1

VIN = VCC or 0V

Chip Disabled

tA= 85oC, VCC = 3.6 V

110.0µA

Maximum Data Retention Current3IDR

Vcc = 1.8V, VIN = VCC or 0

Chip Disabled, tA= 85oC5µA

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Power Savings with Page Mode Operation (WE = VIH)

Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal

organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power

saving feature.

The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open

and 16-bit words of data are read from the open page. By treating addresses A1-A4 as the least significant

bits and addressing the 16 words within the open page, power is reduced to the page mode value which is

considerably lower than standard operating currents for low power SRAMs.

Page Address (A0, A5 - A17)

LB, UB

CE1

CE2

Word Address (A1 - A4)

Open page

Word 1 Word 2 Word 16

...

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Timing Test Conditions

Item

Input Pulse Level 0.1VCC to 0.9 VCC

Input Rise and Fall Time 5ns

Input and Output Timing Reference Levels 0.5 VCC

Output Load CL = 30pF

Operating Temperature -40 to +85 oC

Timing

Item Symbol

-55 -70 Units

Min. Max. Min. Max.

Read Cycle Time tRC 55 70 ns

Address Access Time tAA 55 70 ns

Page Mode Address Access Time tAAP 30 35 ns

Chip Enable to Valid Output tCO 55 70 ns

Output Enable to Valid Output tOE 30 35 ns

Byte Select to Valid Output tBE 55 70 ns

Chip Enable to Low-Z output tLZ 10 10 ns

Output Enable to Low-Z Output tOLZ 55ns

Byte Select to Low-Z Output tBZ 10 10 ns

Chip Disable to High-Z Output tHZ 0 20 0 20 ns

Output Disable to High-Z Output tOHZ 0 20 0 20 ns

Byte Select Disable to High-Z Output tBHZ 0 20 0 20 ns

Output Hold from Address Change tOH 10 10 ns

Write Cycle Time tWC 55 70 ns

Chip Enable to End of Write tCW 45 50 ns

Address Valid to End of Write tAW 45 50 ns

Byte Select to End of Write tBW 45 50 ns

Write Pulse Width tWP 40 40 ns

Address Setup Time tAS 00ns

Write Recovery Time tWR 00ns

Write to High-Z Output tWHZ 20 20 ns

Data to Write Time Overlap tDW 40 40 ns

Data Hold from Write Time tDH 00

End Write to Low-Z Output tOW 55ns

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH)

Timing Waveform of Read Cycle (WE=VIH)

Address

Data Out

tRC

tAA

tOH

Data ValidPrevious Data Valid

Address

LB, UB

Data Valid

tRC

tAA

tCO

tHZ

tOHZ

tBHZ

tOLZ

tOE

tLZ

High-Z

Data Out

tBE

tBLZ

CE1

CE2

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Timing Waveform of Page Mode Read Cycle (WE = VIH)

Page Address (A0, A5 - A17)

LB, UB

tAA

tCO

tHZ

tOHZ

tBHZ

tOLZ

tOE

High-Z

Data Out

tBE

tBLZ

CE1

CE2

Word Address (A1 - A4)

tAAP

tRC

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Timing Waveform of Write Cycle (WE control)

Timing Waveform of Write Cycle (CE1 Control)

Address

Data In

CE1

CE2

LB, UB

Data Valid

tWC

tAW

tCW

tWR

tWHZ

tDH

High-Z

Data Out

High-Z

tOW

tAS tWP

tDW

tBW

Address

Data Valid

tWC

tAW

tCW

tWR

tDH

LB, UB

Data In

High-Z

tAS

tWP

tLZ

tDW

tBW

Data Out

tWHZ

CE1

(for CE2 Control, use

inverted signal)

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

44-Lead TSOP II Package (T44)

Note:

1. All dimensions in inches (Millimeters)

18.41±0.13

10.16±0.13

SEE DETAIL B

1.10±0.15

11.76±0.20

0.45

0.30

0.80mm REF

DETAIL B

0.80mm REF

0o-8o

0.20

0.00

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Ball Grid Array Package

SIDE VIEWTOP VIEW

BOTTOM VIEW

A1 BALL PAD

CORNER (3)

1.24±0.10

0.28±0.05

0.15

0.05

1. 0.35±0.05 DIA.

1. DIMENSION IS MEASURED AT THE

MAXIMUM SOLDER BALL DIAMETER.

PARALLEL TO PRIMARY Z.

2. PRIMARY DATUM Z AND SEATING

PLANE ARE DEFINED BY THE

SPHERICAL CROWNS OF THE

SOLDER BALLS.

3. A1 BALL PAD CORNER I.D. TO BE

MARKED BY INK.

2. SEATING PLANE - Z

K TYP

J TYP e

A1 BALL PAD

CORNER

(DOC# 14-02-042 ReI I ECN# 01-1374

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

N04L1630C2B

Advance InformationAMI Semiconductor, Inc.

Ordering Information

AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.

AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-

poses only and they vary depending upon specific applications.

AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of

any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be

expected to result in significant injury or death, including life support systems and critical medical instruments.

Revision History

Revision Date Change Description

A April 2003 Initial Advanced Release

B August 2004 Changed part number to -30 from -3W and Vcc range to 2.7 V - 3.6V

C January 2005 Change IDR = 5 µA, ICC(typ) = 2.5mA.

Modified page mode address A1-A4 configuration.

D January 2005 General Update

E March 22, 2005 Changed tWP and tDW to 40ns for -55 and -70, to 45ns for -85

F June 9, 2005 Added TSOP II Green Package Ordering Option

G Dec. 2005 Added RoHS Compliant

H July 2006 Added BGA package

I September 2006 Converted to AMI Semiconductor

N04L1630C2BX-XX I

55 = 55ns

70 = 70ns

B2 = 48-ball BGA Green (RoHS Compliant)

T2 = 44-pin TSOP II Green (RoHS Compliant)

Performance

Package Type