PALCE16V8 PALCE16V8Z COM'L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25 COM'L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS (Zero-Power) 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin PAL(R) devices Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology R G N AL EW D E D V ES IC IG ES N F S O -- 5-ns propagation delay for "-5" version -- 7.5-ns propagation delay for "-7" version Direct plug-in replacement for the PAL16R8 series Outputs programmable as registered or combinatorial in any combination Peripheral Component Interconnect (PCI) compliant Programmable output polarity Programmable enable/disable control Preloadable output registers for testability Automatic register reset on power up Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages Extensive third-party software and programmer support Fully tested for 100% programming and functional yields and high reliability 5-ns version utilizes a split leadframe for improved performance GENERAL DESCRIPTION U SE The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALCE16V8Z provides zero standby power and high speed. At 30-A maximum standby current, the PALCE16V8Z allows battery-powered operation for an extended period. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. Publication# 16493 Amendment/0 Rev: F Issue Date: September 2000 BLOCK DIAGRAM I1 - I8 CLK/I0 8 MACRO MC0 MC1 I/O0 I/O1 MACRO MACRO MACRO MACRO MC2 MC3 MC4 MC5 MACRO MACRO MC6 MC7 G N AL EW D D EV ES IC IG ES N F S O OE/I9 MACRO R Programmable AND Array 32 x 64 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 16493E-1 FUNCTIONAL DESCRIPTION U SE The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide userprogrammable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE16V8 are automatically configured from the user's design specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file, once downloaded to a programmer, configures the device according to the user's desired function. The user is given two design options with the PALCE16V8. First, it can be programmed as a standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8. The programmer will program the PALCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. 2 PALCE16V8 and PALCE16V8Z Families Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell. 11 OE 0X 10 VCC To Adjacent Macrocell 11 10 00 01 SL0X SG1 G N AL EW D E D V ES IC IG ES N F S O R 11 0X D SL1X CLK I/OX 10 Q Q 10 11 0X *SG1 *In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. SL0X From Adjacent Pin 16493E-2 Figure 1. PALCE16V8 Macrocell CONFIGURATION OPTIONS U SE Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, it is always disabled. With the exception of MC0 and MC7, a macrocell configured as a dedicated input derives the input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1 (CLK). The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell, and SL1x sets the output as either active low or active high for the individual macrocell. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC7 and OE the adjacent pin for MC0. PALCE16V8 and PALCE16V8Z Families 3 Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE16V8 has three combinatorial output configurations: dedicated output in a nonregistered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output in a Non-Registered Device G N AL EW D D EV ES IC IG ES N F S O R The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0. Combinatorial I/O in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0. Combinatorial I/O in a Registered Device U SE The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Dedicated Input Configuration The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except for MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2. Table 1. Macrocell Configuration SG0 SG1 SL0X Cell Configuration Devices Emulated SG0 SG1 Device Uses Registers 4 SL0X Cell Configuration Devices Emulated Device Uses No Registers 0 1 0 Registered Output PAL16R8, 16R6, 16R4 1 0 0 Combinatorial Output PAL10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 0 1 1 Combinatorial I/O PAL16R6, 16R4 1 0 1 Input PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 1 1 1 Combinatorial I/O PAL16L8 PALCE16V8 and PALCE16V8Z Families Programmable Output Polarity U SE G N AL EW D E D V ES IC IG ES N F S O R The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts. Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0. PALCE16V8 and PALCE16V8Z Families 5 OE OE D Q D Q CLK b. Registered active high G N AL EW D D EV ES IC IG ES N F S O a. Registered active low c. Combinatorial I/O active low d. Combinatorial I/O active high VCC U SE Q R CLK Q VCC Note 1 e. Combinatorial output active low Note 1 f. Combinatorial output active high Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration is not available on pins 15 and 16. Adjacent I/O pin Note 2 g. Dedicated input Figure 2. Macrocell Configurations 6 PALCE16V8 and PALCE16V8Z Families 16493E-2 Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload G N AL EW D E D V ES IC IG ES N F S O R The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability U SE The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE16V8 is fabricated with Vantis' advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE16V8's predictable timing ensures compliance with the PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down PALCE16V8 and PALCE16V8Z Families 7 most of its internal circuitry. The current will go to almost zero (ICC < 15 A). The outputs will maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. This saving is illustrated in the ICC vs. frequency graph. U SE G N AL EW D D EV ES IC IG ES N F S O R Product-Term Disable On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut off from the product terms so that they do not draw current. As shown in the ICC vs. frequency graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs. 8 PALCE16V8 and PALCE16V8Z Families LOGIC DIAGRAM 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK/I 0 1 11 VCC 0X 10 20 V CC 11 10 00 01 SL0 7 0 SG1 11 0X D 7 19 I/O7 10 Q SL1 7 10 11 0X G N AL EW D E D V ES IC IG ES N F S O R I1 2 Q SG0 11 VCC 0X 10 SL0 7 11 10 00 01 SL0 6 8 SG1 15 11 0X D 18 I/O6 10 Q SL16 I2 3 Q 10 11 0X SG1 11 VCC 0X 10 SL0 6 11 10 00 01 SL0 5 16 SG1 I3 4 Q 17 I/O5 10 Q SL1 5 U SE 23 11 0X D 10 11 0X SG1 11 VCC 0X 10 SL0 5 11 10 00 01 SL0 4 24 SG1 11 0X D Q 16 I/O4 10 Q 31 SL1 4 10 11 0X I4 5 SG1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 SL0 4 CLK OE 16493E-2 PALCE16V8 and PALCE16V8Z Families 9 LOGIC DIAGRAM (CONTINUED) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK OE 11 10 00 01 11 VCC 0X 10 SL0 3 32 SG1 11 0X D 39 Q 15 I/O 3 10 Q SL1 3 10 11 0X I5 6 R SG1 11 G N AL EW D D EV ES IC IG ES N F S O 0X 10 VCC SL0 3 11 10 00 01 SL0 2 40 SG1 47 I6 11 0X D 14 I/O 2 10 Q SL1 2 7 Q 10 11 0X SG1 11 VCC 0X 10 SL0 2 11 10 00 01 SL0 1 48 SG1 55 D U SE Q 13 I/O1 10 Q SL1 1 I7 8 56 11 0X 10 11 0X SG1 11 VCC 0X 10 SL0 1 11 10 00 01 SL0 0 SG1 11 0X D 63 SL1 0 Q 12 I/O 0 10 Q 10 11 0X I8 9 SG0 SL00 11 OE/I 9 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 16493E-6 (concluded) 10 PALCE16V8 and PALCE16V8Z Families ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V R Latchup Current (TA = 0C to 75C) . . . . . . . . . 100 mA G N AL EW D D EV ES IC IG ES N F S O Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min Min 2.4 IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Max Unit V 0.5 2.0 V V 0.8 V Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -150 mA ICC (Static) Supply Current for -5 Outputs Open (IOUT = 0 mA), VIN = 0 V VCC = Max 125 mA ICC (Dynamic) Supply Current for -7 Outputs Open (IOUT = 0 mA), VCC = Max, f = 25 MHz 115 mA U SE Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-5/7 (Com'l) 11 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. R SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1 -5 2 G N AL EW D D EV ES IC IG ES N F S O Parameter Symbol Parameter Description Min Max Min Unit 7.5 ns Input or Feedback to Combinatorial Output 1 tS Setup Time from Input or Feedback to Clock 3 5 ns tH Hold Time 0 0 ns tCO Clock to Output tSKEWR Skew Between Registered Outputs (Note 3) tWL Clock Width tWH tPXZ OE to Output Disable tEA tER ns 1 ns 4 ns HIGH 3 4 ns 142.8 100 MHz 1/(tS+tCF) (Note 5) 166 125 MHz 1/(tWH+tWL) 166 125 MHz 1/(tS+tCO) 1 6 1 6 ns 1 5 1 6 ns Input to Output Enable Using Product Term Control 2 6 3 9 ns Input to Output Disable Using Product Term Control 2 5 3 9 ns U SE OE to Output Enable 1 5 3 Maximum Frequency Internal Feedback (fCNT) (Note 4) No Feedback tPZX 1 LOW External Feedback fMAX 4 3 Max tPD 1 5 -7 2 Notes: 1. See "Switching Test Circuit" for test conditions. 2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 12 PALCE16V8H-5/7 (Com'l) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Latchup Current (TA = -40C to +85C). . . . . . . 100 mA Operating ranges define those limits between which the functionality of the device is guaranteed. G N AL EW D D EV ES IC IG ES N F S O Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V R Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min Min 2.4 IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Max Unit V 0.5 2.0 V V 0.8 V Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -150 mA Commercial Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz 115 mA 130 mA ICC (Dynamic) U SE Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) Industrial Supply Current -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-10 (Com'l, Ind) 13 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Parameter Symbol G N AL EW D D EV ES IC IG ES N F S O R SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1 Parameter Description -10 Min 2 Max Unit 10 ns tPD Input or Feedback to Combinatorial Output 3 tS Setup Time from Input or Feedback to Clock 7.5 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width tWH fMAX tPXZ OE to Output Disable tEA tER ns 6 ns HIGH 6 ns 1/(tS+tCO) 66.7 MHz 1/(tS+tCF) (Note 4) 71.4 MHz 1/(tWH+tWL) 83.3 MHz 2 10 ns 2 10 ns Input to Output Enable Using Product Term Control 3 10 ns Input to Output Disable Using Product Term Control 3 10 ns U SE OE to Output Enable 7.5 LOW External Feedback Maximum Frequency Internal Feedback (fCNT) (Note 3) No Feedback tPZX 3 Notes: 1. See "Switching Test Circuit" for test conditions. 2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 14 PALCE16V8H-10 (Com'l, Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V R Latchup Current (TA = 0C to 75C) . . . . . . . . . 100 mA G N AL EW D D EV ES IC IG ES N F S O Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Test Description IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min Min 2.4 IOL = 24 mA, VIN = VIH or VIL, VCC = Min Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Max Unit V 0.5 2.0 V V 0.8 V Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -150 mA ICC Supply Current (Dynamic) Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz 55 mA U SE Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8Q-10 (Com'l) 15 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Parameter Symbol G N AL EW D D EV ES IC IG ES N F S O Parameter Description R SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1 -10 Min 2 Max Unit 10 ns tPD Input or Feedback to Combinatorial Output 3 tS Setup Time from Input or Feedback to Clock 7.5 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width tWH fMAX 3 7.5 ns LOW 6 ns HIGH 6 ns 1/(tS+tCO) 66.7 MHz 1/(tS+tCF) (Note 4) 71.4 MHz 1/(tWH+tWL) 83.3 MHz External Feedback Maximum Frequency Internal Feedback (fCNT) (Note 3) No Feedback OE to Output Enable tPXZ OE to Output Disable tEA Input to Output Enable Using Product Term Control tER Input to Output Disable Using Product Term Control SE tPZX 2 10 ns 2 10 ns 3 10 ns 3 10 ns U Notes: 1. See "Switching Test Circuit" for test conditions. 2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 16 PALCE16V8Q-10 (Com'l) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Latchup Current (TA = -40C to +85C). . . . . . . 100 mA Operating ranges define those limits between which the functionality of the device is guaranteed. G N AL EW D D EV ES IC IG ES N F S O Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V R Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Test Description Min IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min Max 2.4 IOL = 24 mA, VIN = VIH or VIL, VCC = Min V 0.5 Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Unit 2.0 V V 0.8 V Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 A IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) -100 A IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 A IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) -100 A ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -150 mA U SE Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) -30 H 90 Q 55 H 130 Q 65 Commercial Supply Current mA Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz ICC (Dynamic) Industrial Supply Current mA Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-15/25 (Com'l, Ind), Q-15/25 (Com'l), Q-20/25 (Ind) 17 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. R SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1 -20 G N AL EW D D EV ES IC IG ES N F S O -15 Parameter Symbol Parameter Description Min Max Min Max -25 Min Max Unit 25 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 12 13 15 ns tH Hold Time 0 0 0 ns tCO Clock to Output tWL fMAX 10 LOW Clock Width tWH 15 HIGH Maximum Frequency (Note 2) 11 12 ns 8 10 12 ns 8 10 12 ns External Feedback 1/(tS+tCO) 45.5 41.6 37 MHz Internal Feedback (fCNT) 1/(tS+tCF) (Note 3) 50 45.4 40 MHz No Feedback 1/(tWH+tWL) 62.5 50.0 41.6 MHz OE to Output Enable tPXZ OE to Output Disable tEA Input to Output Enable Using Product Term Control tER Input to Output Disable Using Product Term Control SE tPZX U 20 15 18 20 ns 15 18 20 ns 15 18 20 ns 15 18 20 ns Notes: 1. See "Switching Test Circuit" for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 18 PALCE16V8H-15/25 (Com'l, Ind), Q-15/25 (Com'l), Q-20/25 (Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C). . . . . . . 100 mA G N AL EW D D EV ES IC IG ES N F S O R Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Parameter Symbol VOH VOL Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage VIL Input LOW Voltage SE VIH Test Description VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOH = 6 mA 3.84 IOH = 20 A VCC - 0.1 V VIN = 5.25 V, VCC = Max (Note 3) Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) IOZH Off-State Output Leakage Current HIGH IOZL ISC V V V IOL = 6 mA 0.33 V IOL = 20 A 0.1 V 2.0 V 0.9 V 10 A -10 A VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) 10 A Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) -10 A Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) -150 mA Supply Current (Static) Outputs Open (IOUT = 0 mA) VCC = Max f = 0 MHz 30 A f = 15 MHz 75 mA U Input HIGH Leakage Current Unit 0.5 Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1 and 2) IIH Max IOL = 24 mA Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1 and 2) IIL ICC Min Supply Current (Dynamic) -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. Represents the worst case of HC and HCT standards, allowing compatibility with either. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8Z-12 (Ind) 19 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Parameter Symbol G N AL EW D D EV ES IC IG ES N F S O Parameter Description R SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1 -12 Min Max Unit 12 ns tPD Input or Feedback to Combinatorial Output (Note 2) tS Setup Time from Input or Feedback to Clock 8 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width tWH fMAX 8 ns LOW 5 ns HIGH 5 ns 1/(tS+tCO) 62.5 MHz 1/(tS+tCF) 77 MHz 1/(tWH+tWL) 100 MHz External Feedback Maximum Frequency Internal Feedback (fCNT) (Notes 3 and 4) No Feedback OE to Output Enable tPXZ OE to Output Disable tEA Input to Output Enable Using Product Term Control tER Input to Output Disable Using Product Term Control SE tPZX 8 ns 8 ns 13 ns 13 ns U Notes: 1. See "Switching Test Circuit" for test conditions. 2. This parameter is tested in standby mode. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 20 PALCE16V8Z-12 (Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C). . . . . . . 100 mA G N AL EW D D EV ES IC IG ES N F S O R Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Parameter Symbol VOH VOL Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage VIL Input LOW Voltage SE VIH Test Description VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOH = 6 mA 3.84 IOH = 20 A VCC - 0.1 V VIN = 5.25 V, VCC = Max (Note 3) Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) IOZH Off-State Output Leakage Current HIGH IOZL ISC V V V IOL = 6 mA 0.33 V IOL = 20 A 0.1 V 2.0 V 0.9 V 10 A -10 A VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) 10 A Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) -10 A Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) -150 mA Supply Current (Static) Outputs Open (IOUT = 0 mA) VCC = Max f = 0 MHz 15 A f = 25 MHz 75 mA U Input HIGH Leakage Current Unit 0.5 Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1 and 2) IIH Max IOL = 24 mA Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1 and 2) IIL ICC Min Supply Current (Dynamic) -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. Represents the worst case of HC and HCT standards, allowing compatibility with either. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8Z-15 (Ind) 21 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Parameter Symbol G N AL EW D D EV ES IC IG ES N F S O Parameter Description R SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1 -15 Min 2 Max Unit 15 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 10 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width tWH fMAX Maximum Frequency (Notes 3 and 4) 10 ns LOW 8 ns HIGH 8 ns External Feedback 1/(tS+tCO) 50 MHz Internal Feedback (fCNT) 1/(tS+tCF) 58.8 MHz No Feedback 1/(tWH+tWL) 62.5 MHz OE to Output Enable tPXZ OE to Output Disable tEA Input to Output Enable Using Product Term Control tER Input to Output Disable Using Product Term Control SE tPZX 15 ns 15 ns 15 ns 15 ns U Notes: 1. See "Switching Test Circuit" for test conditions. 2. This parameter is tested in standby mode. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 22 PALCE16V8Z-15 (Ind) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65C to +150C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to +125C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +75C Supply Voltage with Respect to Ground . . . . . . . . . . -0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V Industrial (I) Devices Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C). . . . . . . 100 mA Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. G N AL EW D D EV ES IC IG ES N F S O Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . -40C to +85C R DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage Test Description VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min VIL Input LOW Voltage IIH Input HIGH Leakage Current IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) Supply Current (Static) Outputs Open (IOUT = 0 mA) VCC = Max ICC U SE Input HIGH Voltage Supply Current (Dynamic) Max Unit IOH = 6 mA 3.84 V IOH = 20 A VCC - 0.1 V V IOL = 24 mA 0.5 V IOL = 6 mA 0.33 V IOL = 20 A 0.1 V Guaranteed Input Logical HIGH Voltage for all Inputs (Notes 1 and 2) VIH Min 2.0 V Guaranteed Input Logical LOW Voltage for all Inputs (Notes 1 and 2) 0.9 V VIN = 5.25 V, VCC = Max (Note 3) 10 A -10 A 10 A -10 A -150 mA f = 0 MHz 15 A f = 25 MHz 90 mA -30 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. Represents the worst case of HC and HCT standards, allowing compatibility with either. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8Z-25 (Com'l, Ind) 23 CAPACITANCE1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 C, 5 pF COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. Parameter Symbol G N AL EW D D EV ES IC IG ES N F S O R SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1 Parameter Description -25 Min 2 Max Unit 25 ns tPD Input or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input or Feedback to Clock 20 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width tWH fMAX Maximum Frequency (Notes 4 and 5) tPZX OE to Output Enable tPXZ OE to Output Disable tEA tER 10 ns LOW 8 ns HIGH 8 ns External Feedback 1/(tS+tCO) 33.3 MHz Internal Feedback (fCNT) 1/(tS+tCF) 50 MHz No Feedback 1/(tWH+tWL) 50 MHz ns 25 ns Input to Output Enable Using Product Term Control 25 ns Input to Output Disable Using Product Term Control 25 ns U SE 25 Notes: 1. See "Switching Test Circuit" for test conditions. 2. This parameter is tested in standby mode. 3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be 2 ns faster. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 24 PALCE16V8Z-25 (Com'l, Ind) SWITCHING WAVEFORMS Input or Feedback Input or Feedback VT VT tS tPD tH VT Combinatorial Output Clock VT 16493E-3 tCO Registered Output VT R 16493E-5 b. Registered output G N AL EW D D EV ES IC IG ES N F S O a. Combinatorial output VT Input tWH Clock tER VT Output tWL 16493E-4 c. Clock width tEA VOH - 0.5V VOL + 0.5V VT 16493E-6 d. Input to output disable/enable VT OE tPXZ VOH - 0.5V Output VT VOL + 0.5V 16493E-7 e. OE to output disable/enable U SE tPZX Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical. PALCE16V8 and PALCE16V8Z Families 25 KEY TO SWITCHING WAVEFORMS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State R INPUTS G N AL EW D D EV ES IC IG ES N F S O WAVEFORM KS000010-PAL SWITCHING TEST CIRCUIT 5V U SE S1 R1 Output Test Point R2 CL 16493E-8 Commercial Specification tPD, tCO tEA tER 26 S1 CL R1 R2 Closed Z H: Open 1.5 V L Z: Closed 390 50 pF Z L: Closed H Z: Open Measured Output Value 200 5 pF H-5: 200 PALCE16V8 and PALCE16V8Z Families 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C 150 16V8H-5 G N AL EW D E D V ES IC IG ES N F S O R 125 ICC (mA) 100 75 50 0 U SE 25 0 10 20 30 40 Frequency (MHz) 16V8H-7 16V8H-10 16V8H-15/25 16V8Z-12/15 16V8Q-10/15/25 16V8Z-25 50 16493E-9 ICC vs. Frequency The selected "typical" pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. PALCE16V8 and PALCE16V8Z Families 27 ENDURANCE CHARACTERISTICS The PALCE16V8 is manufactured using Vantis' advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed--a feature which allows 100% testing at the factory. Symbol Parameter tDR Min Pattern Data Retention Time N Min Reprogramming Cycles Test Conditions Value Unit Max Storage Temperature 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles ROBUSTNESS FEATURES G N AL EW D D EV ES IC IG ES N F S O R PALCE16V8X-X/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices are also being retrofitted with these robustness features. INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8 VCC VCC U SE > 50 k ESD Protection and Clamping Programming Pins Only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC VCC > 50 k Provides ESD Protection and Clamping Preload Feedback Circuitry Input 16493E-10 Typical Output 28 PALCE16V8 and PALCE16V8Z Families INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z VCC Programming Pins Only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry R ESD Input Protection Transition and Detection Clamping G N AL EW D E D V ES IC IG ES N F S O Typical Input VCC 16493E-11 Provides ESD Protection and Clamping Preload Feedback Input Circuitry Input Transition Detection Typical Output POWER-UP RESET U SE The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW Min Max Unit 1000 ns See Switching Characteristics PALCE16V8 and PALCE16V8Z Families 29 VCC 4V Power tPR Registered Output tS Clock tWL G N AL EW D D EV ES IC IG ES N F S O R 16493E-12 Figure 3. Power-Up Reset Waveform TYPICAL THERMAL CHARACTERISTICS Measured at 25C ambient. These parameters are not tested. Parameter Symbol Parameter Description Typ PDID PLCC Unit jc Thermal impedance, junction to case 25 22 C/W ja Thermal impedance, junction to ambient 71 64 C/W 200 lfpm air 61 55 C/W 400 lfpm air 55 51 C/W 600 lfpm air 51 47 C/W 800 lfpm air 47 45 C/W Thermal impedance, junction to ambient with air flow U SE jma Plastic jc Considerations The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 30 PALCE16V8 and PALCE16V8Z Families CONNECTION DIAGRAMS Top View PLCC I1 2 19 I/O7 I2 3 18 I/O6 I3 4 17 I/O5 I4 5 16 I/O4 I5 6 15 I/O3 I6 7 14 I/O2 I7 8 13 I8 9 PIN DESIGNATIONS CLK = Clock GND = Ground 18 I/O6 I4 5 17 I/O5 I5 6 16 I/O4 I/O1 I6 7 15 I/O3 12 I/O0 I7 8 14 I/O2 11 OE/I9 = Input I/O = Input/Output OE = Output Enable VCC = Supply Voltage R 4 I/O1 GND I/O0 10 11 12 13 OE/I9 9 16493E-10 U SE I 20 19 I3 16493E-9 Note: Pin 1 is marked for orientation. 1 I8 10 2 G N AL EW D E D V ES IC IG ES N F S O GND 3 I/O7 VCC VCC 20 CLK/I0 1 I1 CLK/I0 I2 DIP/SOIC PALCE16V8 and PALCE16V8Z Families 31 ORDERING INFORMATION Commercial and Industrial Products Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 16 V 8 H -5 J C /5 FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4) OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS G N AL EW D D EV ES IC IG ES N F S O R NUMBER OF ARRAY INPUTS OPERATING CONDITIONS C = Commercial (0C to +75C) I = Industrial (-40C to +85C) POWER H = Half Power (90-125 mA ICC) Q = Quarter Power (55 mA ICC) Z = Zero Power (15 A ICC Standby) SPEED -5 = -7 = -10 = -12 = -15 = -20 = -25 = 5 ns tPD 7.5 ns tPD 10 ns tPD 12 ns tPD 15 ns tPD 20 ns tPD 25 ns tPD PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) S = 20-Pin Plastic Gull-Wing Small Outline Package (SO 020) Valid Combinations PALCE16V8H-7 PALCE16V8H-10 JC /5 PC, JC, SC U PALCE16V8H-5 SE Valid Combinations PC, JC, SC, PI, JI /4 PALCE16V8Q-10 JC /5 PALCE16V8H-15 PC, JC, SC PALCE16V8Q-15 PC, JC PALCE16V8Q-20 PI, JI PALCE16V8H-25 PC, JC, SC, PI, JI PALCE16V8Q-25 PC, JC, PI, JI Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local Lattice/ Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. /4 PALCE16V8Z-12 PI, JI PALCE16V8Z-15 PALCE16V8Z-25 32 PC, JC, SC, PI, JI, SI PALCE16V8 and PALCE16V8Z Families