Publication# 16493 Rev: F
Amendment/0Issue Date: September 2000
USE GAL DEVICES FOR
NEW DESIGNS
PALCE16V8 COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8Z COM’L:-25 IND:-12/15/25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
◆
Pin and function compatible with all 20-pin PAL
®
devices
◆
Electrically erasable CMOS technology provides reconfigurable logic and full testability
◆
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
◆
Direct plug-in replacement for the PAL16R8 series
◆
Outputs programmable as registered or combinatorial in any combination
◆
Peripheral Component Interconnect (PCI) compliant
◆
Programmable output polarity
◆
Programmable enable/disable control
◆
Preloadable output registers for testability
◆
Automatic register reset on power up
◆
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
◆
Extensive third-party software and programmer support
◆
Fully tested for 100% programming and functional yields and high reliability
◆
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL
device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
2 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently configurable macrocells (MC
0
-
MC
7
). Each macrocell can
be configured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V
CC
or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify
the design and create a programming file (JEDEC). This file, once downloaded to a programmer ,
configures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard P AL device from the P AL16R8 series. The P AL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the P ALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC files without making any changes to them.
Programmable AND Array
32 x 64
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
OE/I9I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7
8
I1 – I8CLK/I0
16493E-1
PALCE16V8 and PALCE16V8Z Families 3
USE GAL DEVICES FOR
NEW DESIGNS
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC
0
and MC
7
, a macrocell configured as a dedicated input derives the
input signal from an adjacent I/O. MC
0
derives its input from pin 11 (OE) and MC
7
from pin 1
(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0
determines whether registers will be allowed. SG1 deter mines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0
x
, in
conjunction with SG1, selects the configuration of the macrocell, and SL1
x
sets the output as
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
x
are the control signals for all four multiplexers. In
MC
0
and MC
7
, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC
7
and OE the adjacent pin for MC
0
.
Figure 1. PALCE16V8 Macrocell
1 1
0 X
1 0
*SG1
SG1 SL0X
DQ
Q
1 0
1 1
0 X
1 1
1 0
0 0
0 1
VCC
CLK
SL0X
OE
To
Adjacent
Macrocell
From
Adjacent
Pin
1 1
0 X
1 0
SL1X
I/OX
16493E-2
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
4 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
x.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buf fer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
x
= 1. Only seven product terms are
available to the OR gate. The eighth product term is used to enable the output buffer . The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC
7
,
and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 1. The output buffer is disabled. Except
for MC
0
and MC
7
, the feedback signal is an adjacent I/O. For MC
0
and MC
7
, the feedback signals
are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
Table 1. Macrocell Configuration
SG0 SG1 SL0XCell
Configuration Devices
Emulated SG0 SG1 SL0XCell
Configuration Devices
Emulated
Device Uses Registers Device Uses No Registers
0 1 0 Registered Output PAL16R8, 16R6,
16R4 100
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
011
Combinatorial
I/O PAL16R6, 16R4 1 0 1 Input PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
111
Combinatorial
I/O PAL16L8
PALCE16V8 and PALCE16V8Z Families 5
USE GAL DEVICES FOR
NEW DESIGNS
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1
x
which controls an exclusive-OR gate at the output
of the AND/OR logic. The output is active high if SL1
x
is 1 and active low if SL1
x
is 0.
6 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
Figure 2. Macrocell Configurations
D
Q
Q
OE
CLK
a. Registered active low
D
Q
Q
OE
CLK
b. Registered active high
c. Combinatorial I/O active low d. Combinatorial I/O active high
e. Combinatorial output active low
VCC
f. Combinatorial output active high
VCC
Adjacent I/O pin
g. Dedicated input
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
2. This configuration is not available on pins 15 and 16.
Note 1 Note 1
Note 2
16493E-2
PALCE16V8 and PALCE16V8Z Families 7
USE GAL DEVICES FOR
NEW DESIGNS
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
P ALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function
of the logic.
Register Preload
The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.
Security Bit
A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.
Programming and Erasing
The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
perfor med by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying perfor mance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
yields and post-programming functional yields in the industry.
Technology
The high-speed PALCE16V8 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.
PCI Compliance
PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the
PCI Local Bus
Specification
published by the PCI Special Interest Group. The PALCE16V8’s predictable timing
ensures compliance with the PCI AC specifications independent of the design.
Zero-Standby Power Mode
The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down
8 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
most of its internal circuitry. The current will go to almost zero (ICC < 15 µA). The outputs will
maintain the states held before the device went into the standby mode. There is no speed
penalty associated with coming out of standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the ICC vs. frequency graph.
Product-Term Disable
On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut
off from the product terms so that they do not draw current. As shown in the ICC vs. frequency
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zer o-Power PLDs .
PALCE16V8 and PALCE16V8Z Families 9
USE GAL DEVICES FOR
NEW DESIGNS
LOGIC DIAGRAM
034781112151619202324272831
0
7
8
15
16
23
24
31
03478111215161920 2427283123
I2
I1
CLK/I01
2
3
I4
I34
5
CLK OE
1 1
0 X
1 0
SG1
SL07
1 1
0 X
1 0
SG1
SL05
1 1
0 X
1 0
SG1
SL04
SG1
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
SL05
0 X
SG1
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
SL04
0 X
1 1
0 X
1 0
SG1
SL06
SG1
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
SL06
0 X
SG0
1 1
0 X
1 0
DQ
Q
1 0
1 1
0 X
1 1
1 0
0 0
0 1
VCC
17
I/O4
16
18
I/O5
I/O6
I/O7
19
SL17
SL16
SL15
SL14
20 VCC
SL07
16493E-2
10 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
LOGIC DIAGRAM (CONTINUED)
034781112151619202324272831
32
39
40
47
48
55
0 3 4 7 8 1112 1516 1920 2324 2728 31
I8
I7
I6
I5
56
63
6
7
8
9
CLK OE
1 1
0 X
1 0
SG1
SL03
1 1
0 X
1 0
SG1
SL01
1 1
0 X
1 0
SG1
SL00
1 1
0 X
1 0
SG1
SL02
OE/I
1 1
0 X
1 0
DQ
Q
1 0
1 1
0 X
1 1
1 0
0 0
0 1
SG0
VCC
SG1
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
SL01
0 X
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
0 X
SG1
1 1
0 X
1 0
DQ
Q
1 0
1 1
1 1
1 0
0 0
0 1
VCC
SL02
0 X
SG1 SL03
I/O3
15
I/O2
14
I/O1
13
I/O0
12
11
SL13
SL12
SL11
SL10
9
SL00
GND 10
16493E-6
(concluded)
PALCE16V8H-5/7 (Com’l) 11
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2) –100 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –150 mA
ICC (Static) Supply Current for -5 Outputs Open (IOUT = 0 mA), VIN = 0 V
VCC = Max 125 mA
ICC (Dynamic) Supply Current for -7 Outputs Open (IOUT = 0 mA),
VCC = Max, f = 25 MHz 115 mA
12 PALCE16V8H-5/7 (Com’l)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-5 -7
UnitMin 2Max Min 2Max
tPD Input or Feedback to Combinatorial Output 1 5 3 7.5 ns
tSSetup Time from Input or Feedback to Clock 3 5 ns
tHHold Time 0 0 ns
tCO Clock to Output 1415ns
tSKEWR Skew Between Registered Outputs (Note 3) 1 1 ns
tWL Clock Width LOW 3 4 ns
tWH HIGH 3 4 ns
fMAX Maximum Frequency
(Note 4)
External Feedback 1/(tS+tCO) 142.8 100 MHz
Internal Feedback (fCNT) 1/(tS+tCF) (Note 5) 166 125 MHz
No Feedback 1/(tWH+tWL) 166 125 MHz
tPZX OE to Output Enable 1616ns
tPXZ OE to Output Disable 1516ns
tEA Input to Output Enable Using Product Term Control 2639ns
tER Input to Output Disable Using Product Term Control 2539ns
PALCE16V8H-10 (Com’l, Ind) 13
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) Devices
Temperature (TA) Operating
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2) –100 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –150 mA
ICC (Dynamic) Commercial Supply Current Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
115 mA
Industrial Supply Current 130 mA
14 PALCE16V8H-10 (Com’l, Ind)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-10
UnitMin 2Max
tPD Input or Feedback to Combinatorial Output 3 10 ns
tSSetup Time from Input or Feedback to Clock 7.5 ns
tHHold Time 0ns
tCO Clock to Output 3 7.5 ns
tWL Clock Width LOW 6 ns
tWH HIGH 6 ns
fMAX Maximum Frequency
(Note 3)
External Feedback 1/(tS+tCO) 66.7 MHz
Internal Feedback (fCNT) 1/(tS+tCF) (Note 4) 71.4 MHz
No Feedback 1/(tWH+tWL) 83.3 MHz
tPZX OE to Output Enable 210ns
tPXZ OE to Output Disable 210ns
tEA Input to Output Enable Using Product Term Control 3 10 ns
tER Input to Output Disable Using Product Term Control 3 10 ns
PALCE16V8Q-10 (Com’l) 15
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to 75°C) . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage IOH = -3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2) –100 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –150 mA
ICC Supply Current (Dynamic) Outputs Open (IOUT = 0 mA),
VCC = Max, f = 15 MHz 55 mA
16 PALCE16V8Q-10 (Com’l)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-10
UnitMin 2Max
tPD Input or Feedback to Combinatorial Output 3 10 ns
tSSetup Time from Input or Feedback to Clock 7.5 ns
tHHold Time 0ns
tCO Clock to Output 3 7.5 ns
tWL Clock Width LOW 6 ns
tWH HIGH 6 ns
fMAX Maximum Frequency
(Note 3)
External Feedback 1/(tS+tCO) 66.7 MHz
Internal Feedback (fCNT) 1/(tS+tCF) (Note 4) 71.4 MHz
No Feedback 1/(tWH+tWL) 83.3 MHz
tPZX OE to Output Enable 210ns
tPXZ OE to Output Disable 210ns
tEA Input to Output Enable Using Product Term Control 3 10 ns
tER Input to Output Disable Using Product Term Control 3 10 ns
PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind) 17
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) Devices
Temperature (TA) Operating
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VIN = VIH or VIL, VCC = Min 2.4 V
VOL Output LOW Voltage IOL = 24 mA, VIN = VIH or VIL, VCC = Min 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1) 0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2) –100 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –150 mA
ICC (Dynamic)
Commercial Supply Current Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
H90
mA
Q55
Industrial Supply Current H 130 mA
Q65
18 PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-15 -20 -25
UnitMin Max Min Max Min Max
tPD Input or Feedback to Combinatorial Output 15 20 25 ns
tSSetup Time from Input or Feedback to Clock 12 13 15 ns
tHHold Time 0 0 0 ns
tCO Clock to Output 10 11 12 ns
tWL Clock Width LOW 8 10 12 ns
tWH HIGH 8 10 12 ns
fMAX
Maximum
Frequency
(Note 2)
External Feedback 1/(tS+tCO) 45.5 41.6 37 MHz
Internal Feedback
(fCNT)1/(tS+tCF)
(Note 3) 50 45.4 40 MHz
No Feedback 1/(tWH+tWL) 62.5 50.0 41.6 MHz
tPZX OE to Output Enable 15 18 20 ns
tPXZ OE to Output Disable 15 18 20 ns
tEA Input to Output Enable Using Product Term Control 15 18 20 ns
tER Input to Output Disable Using Product Term Control 15 18 20 ns
PALCE16V8Z-12 (Ind) 19
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage VIN = VIH or VIL, VCC = Min IOH = 6 mA 3.84 V
IOH = 20 µA VCC – 0.1 V V
VOL Output LOW Voltage VIN = VIH or VIL, VCC = Min
IOL = 24 mA 0.5 V
IOL = 6 mA 0.33 V
IOL = 20 µA 0.1 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2) 0.9 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3) –10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –150 mA
ICC Supply Current (Static) Outputs Open (IOUT = 0 mA)
VCC = Max f = 0 MHz 30 µA
Supply Current (Dynamic) f = 15 MHz 75 mA
20 PALCE16V8Z-12 (Ind)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values therefore, minimum values are recommended for simulation purposes only.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-12
UnitMin Max
tPD Input or Feedback to Combinatorial Output (Note 2) 12 ns
tSSetup Time from Input or Feedback to Clock 8ns
tHHold Time 0ns
tCO Clock to Output 8ns
tWL Clock Width LOW 5ns
tWH HIGH 5ns
fMAX Maximum Frequency
(Notes 3 and 4)
External Feedback 1/(tS+tCO)62.5 MHz
Internal Feedback (fCNT) 1/(tS+tCF)77 MHz
No Feedback 1/(tWH+tWL)100 MHz
tPZX OE to Output Enable 8ns
tPXZ OE to Output Disable 8ns
tEA Input to Output Enable Using Product Term Control 13 ns
tER Input to Output Disable Using Product Term Control 13 ns
PALCE16V8Z-15 (Ind) 21
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage VIN = VIH or VIL, VCC = Min IOH = 6 mA 3.84 V
IOH = 20 µA VCC – 0.1 V V
VOL Output LOW Voltage VIN = VIH or VIL, VCC = Min
IOL = 24 mA 0.5 V
IOL = 6 mA 0.33 V
IOL = 20 µA 0.1 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2) 0.9 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3) –10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –150 mA
ICC Supply Current (Static) Outputs Open (IOUT = 0 mA)
VCC = Max f = 0 MHz 15 µA
Supply Current (Dynamic) f = 25 MHz 75 mA
22 PALCE16V8Z-15 (Ind)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-15
UnitMin 2Max
tPD Input or Feedback to Combinatorial Output 15 ns
tSSetup Time from Input or Feedback to Clock 10 ns
tHHold Time 0ns
tCO Clock to Output 10 ns
tWL Clock Width LOW 8 ns
tWH HIGH 8 ns
fMAX
Maximum
Frequency (Notes 3
and 4)
External Feedback 1/(tS+tCO) 50 MHz
Internal Feedback (fCNT) 1/(tS+tCF) 58.8 MHz
No Feedback 1/(tWH+tWL) 62.5 MHz
tPZX OE to Output Enable 15 ns
tPXZ OE to Output Disable 15 ns
tEA Input to Output Enable Using Product Term Control 15 ns
tER Input to Output Disable Using Product Term Control 15 ns
PALCE16V8Z-25 (Com’l, Ind) 23
USE GAL DEVICES FOR
NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
DC Input Voltage . . . . . . . . . . . -0.5 V to VCC + 0.5 V
DC Output or I/O Pin Voltage . . . -0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) Devices
Temperature (TA) Operating
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
Parameter
Symbol Parameter Description Test Description Min Max Unit
VOH Output HIGH Voltage VIN = VIH or VIL, VCC = Min IOH = 6 mA 3.84 V
IOH = 20 µA VCC – 0.1 V V
VOL Output LOW Voltage VIN = VIH or VIL, VCC = Min
IOL = 24 mA 0.5 V
IOL = 6 mA 0.33 V
IOL = 20 µA 0.1 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2) 0.9 V
IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 3) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 3) –10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –30 –150 mA
ICC Supply Current (Static) Outputs Open (IOUT = 0 mA)
VCC = Max f = 0 MHz 15 µA
Supply Current (Dynamic) f = 25 MHz 90 mA
24 PALCE16V8Z-25 (Com’l, Ind)
USE GAL DEVICES FOR
NEW DESIGNS
CAPACITANCE1
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be 2 ns faster.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25 °C, 5 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
Parameter
Symbol Parameter Description
-25
UnitMin 2Max
tPD Input or Feedback to Combinatorial Output (Note 3) 25 ns
tSSetup Time from Input or Feedback to Clock 20 ns
tHHold Time 0ns
tCO Clock to Output 10 ns
tWL Clock Width LOW 8ns
tWH HIGH 8ns
fMAX
Maximum
Frequency (Notes 4
and 5)
External Feedback 1/(tS+tCO)33.3 MHz
Internal Feedback (fCNT) 1/(tS+tCF)50 MHz
No Feedback 1/(tWH+tWL)50 MHz
tPZX OE to Output Enable 25 ns
tPXZ OE to Output Disable 25 ns
tEA Input to Output Enable Using Product Term Control 25 ns
tER Input to Output Disable Using Product Term Control 25 ns
PALCE16V8 and PALCE16V8Z Families 25
USE GAL DEVICES FOR
NEW DESIGNS
SWITCHING WAVEFORMS
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
tPD
Input or
Feedback
Combinatorial
Output
VT
VT
a. Combinatorial output
16493E-3
tWH
Clock
c. Clock width
VT
tWL
16493E-4
VT
Input or
Feedback
Registered
Output
b. Registered output
tS
tCO
VT
tH
VT
Clock
16493E-5
VT
VT
Input
Output
d. Input to output disable/enable
tER tEA
VOH – 0.5V
VOL + 0.5V
16493E-6
16493E-7
VT
VT
OE
Output
e. OE to output disable/enable
tPZX
tPXZ VOH – 0.5V
VOL + 0.5V
26 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
KEY TO SWITCHING WAVEFORMS
SWITCHING TEST CIRCUIT
Specification S1CL
Commercial
Measured Output ValueR1R2
tPD, tCO Closed
50 pF
200 Ω
390 Ω
1.5 V
tEA Z → H: Open 1.5 V
Z → L: Closed
tER H → Z: Open 5 pF H-5: 200 ΩH → Z: VOH – 0.5 V
L → Z: Closed L → Z: VOL + 0.5 V
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010-PAL
CL
Output
R1
R2
S1
Test Point
5
V
16493E-8
PALCE16V8 and PALCE16V8Z Families 27
USE GAL DEVICES FOR
NEW DESIGNS
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
ICC vs. Frequency
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
150
125
100
75
50
25
0
01020304050
Frequency (MHz)
ICC (mA)
16V8H-5
16V8H-7
16V8H-10
16V8H-15/25
16V8Q-10/15/25
16493E-9
16V8Z-12/15
16V8Z-25
28 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
ENDURANCE CHARACTERISTICS
The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and
I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing.
A special noise filter makes the programming circuitry completely insensitive to any positive
overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices
are also being retrofitted with these robustness features.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8
Symbol Parameter Test Conditions Value Unit
tDR Min Pattern Data Retention Time Max Storage Temperature 10 Years
Max Operating Temperature 20 Years
N Min Reprogramming Cycles Normal Programming Conditions 100 Cycles
16493E-10
Typical Input
Typical Output
Preload
Circuitry
ESD
Protection
and
Clamping
Feedback
Input
VCC
VCC
> 50 kΩ
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins Only
> 50 kΩ
VCC
PALCE16V8 and PALCE16V8Z Families 29
USE GAL DEVICES FOR
NEW DESIGNS
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z
POWER-UP RESET
The PALCE16V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways VCC can rise to its steady state, two conditions are required to ensure a valid
power-up reset. These conditions are:
◆The VCC rise must be monotonic.
◆Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol Parameter Descriptions Min Max Unit
tPR Power-Up Reset Time 1000 ns
tSInput or Feedback Setup Time See Switching Characteristics
tWL Clock Width LOW
16493E-11
Typical Input
Typical Output
Feedback
Input
ESD
Protection
and
Clamping
Input
Transition
Detection
VCC
VCC
Programming
Voltage
Detection
Positive
Overshoot
Filter Programming
Circuitry
Provides ESD
Protection and
Clamping
Programming
Pins Only
Input
Transition
Detection
Preload
Circuitry
30 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Plastic
θ
jc Considerations
The data listed for plastic
θ
jc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the
θ
jc measurement relative to a specific location on the pack-
age surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore,
θ
jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem-
perature. Therefore, the measurements can only be used in a similar environment.
Parameter
Symbol Parameter Description
Typ
UnitPDID PLCC
θjc Thermal impedance, junction to case 25 22 °C/W
θja Thermal impedance, junction to ambient 71 64 °C/W
θjma Thermal impedance, junction to ambient with air flow
200 lfpm air 61 55 °C/W
400 lfpm air 55 51 °C/W
600 lfpm air 51 47 °C/W
800 lfpm air 47 45 °C/W
Figure 3. Power-Up Reset Waveform
tPR
tWL
tS
4 V VCC
Power
Registered
Output
Clock
16493E-12
PALCE16V8 and PALCE16V8Z Families 31
USE GAL DEVICES FOR
NEW DESIGNS
CONNECTION DIAGRAMS
Top View
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
OE = Output Enable
VCC = Supply Voltage
DIP/SOIC
Note:
Pin 1 is marked for orientation.
PLCC
1
2
3
4
5
6
7
8
9
10
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
GND
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
20
19
18
17
16
15
14
13
12
11
16493E-9
120 19
18
17
16
15
14
2
3
4
5
6
7
8
910 11 12 13
I3
I4
I5
I6
I7
I/O6
I/O5
I/O4
I/O3
I/O2
OE/I9
I/O0
I/O1
GND
I8
CLK/I0
VCC
I/O7
I1
I2
16493E-10
32 PALCE16V8 and PALCE16V8Z Families
USE GAL DEVICES FOR
NEW DESIGNS
ORDERING INFORMATION
Commercial and Industrial Products
Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options.
The order number (Valid Combination) is formed by a combination of:
Valid Combinations
Valid Combinations lists configurations planned to be
supported in volume for this device. Consult the local Lattice/
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
S = 20-Pin Plastic Gull-Wing
Small Outline Package (SO 020)
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
I = Industrial (-40°C to +85°C)
PAL CE 16 V 8 H -5 J C
SPEED
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
FAMILY TYPE
PAL = Programmable Array Logic
POWER
H = Half Power (90–125 mA ICC)
Q = Quarter Power (55 mA ICC)
Z = Zero Power (15 µA ICC Standby)
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
/5
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4 = First Revision
/5 = Second Revision
(Same Algorithm as /4)
Valid Combinations
PALCE16V8H-5 JC /5
PALCE16V8H-7 PC, JC, SC
PALCE16V8H-10 PC, JC, SC, PI, JI /4
PALCE16V8Q-10 JC /5
PALCE16V8H-15 PC, JC, SC
/4
PALCE16V8Q-15 PC, JC
PALCE16V8Q-20 PI, JI
PALCE16V8H-25 PC, JC, SC, PI, JI
PALCE16V8Q-25 PC, JC, PI, JI
PALCE16V8Z-12 PI, JI
PALCE16V8Z-15
PALCE16V8Z-25 PC, JC, SC, PI, JI, SI
