www.irf.com © 2011 International Rectifier
Feb 28, 2011
IR1155S
PROGRAMMABLE FREQUENCY, ONE CYCLE CONTROL PFC IC
Features
Description Package
IR1155 Application Diagram
• PFC IC with IR proprietary “One Cycle Control”
• Continuous conduction mode boost type PFC
• Programmable switching frequency (48k-200kHz)
• Average current mode control
• Output overvoltage protection
• Open loop protection
• Cycle by cycle peak current limit
• VCC under voltage lockout
• Programmable soft start
• Micropower startup
• User initiated micropower “Sleep Mode”
• OVP/EN pin internal filtering for higher noise immunity
• 1.5A peak gate drive
• Latch immunity and ESD protection
The μPFC IR1155 power factor correction IC, based on IR proprietary "One
Cycle Control" (OCC) technique, provides for high PF, low THD and
excellent DC Bus regulation while enabling drastic reduction in component
count, PCB area and design time as compared to traditional solutions. The
IC is designed to operate in continuous conduction mode Boost PFC
converters with average current mode control over 85-264VAC input line
voltage range. Switching frequency can be programmed to anywhere
between 48kHz to 200kHz based on the specific application requirement.
In addition, IR1155 offers several advanced system-enabling and protective
features such as dedicated pin for over voltage protection, cycle by cycle
peak current limitation, open loop protection, VCC UVLO, soft-start and
micropower startup/sleep-mode with IC current consumption less than
200µA. The sleep mode, invoked by pulling the OVP/EN pin low, enables
compliance with standby power requirements mandated by regulations
such as Energy Star, Green Power, Blue Angel etc.
AC LINE
VOUT
A
C NEUTRAL
VCC
RTN
-+
COM
1
OVP
4
VFB 6
VCC 7
GATE 8
ISNS
3
FREQ
2
COMP 5
IR1155S
IR1155S
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Qualification Information
Industrial
Qualification Level Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
Moisture Sensitivity Level MSL2 260°C
(per IPC/JEDEC J-STD-020)
Machine Model Class A
(per JEDEC standard JESD22-A115)
ESD
Human Body Model Class 1B (passes 500V)
(per EIA/JEDEC standard EIA/JESD22-A114)
IC Latch-Up Test Class I, Level A
(per JESD78)
RoHS Compliant Yes
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Remarks
VCC Voltage VCC -0.3 20 V
FREQ Voltage VFREQ -0.3 6.5 V
ISNS Voltage VISNS -10 0.3 V
VFB, OVP Voltage VFB, VOVP -0.3 6.5 V
COMP Voltage VCOMP -0.3 6.5 V
GATE Voltage VGATE -0.3 18 V
ISNS Current IISNS -2 2 mA
Junction Temperature TJ -40 150 °C
Storage Temperature TS -55 150 °C
Thermal Resistance
Junction to Ambient RθJA 128 °C/W
Package Power Dissipation PD 976 mW TAMB = 25°C
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameter Symbol Min. Typ. Max. Units Remarks
Supply Voltage VCC 12 19 V
Junction Temperature TJ -25 125 °C
Switching Frequency FSW 48 200 kHz
IR1155S
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Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range TJ from –25 °C to 125°C. Typical values represent the median values, which are
related to 25°C. If not other wise stated, a supply voltage of VCC =15V is assumed for test condition.
Supply Section
Parameter Symbol Min. Typ. Max. Units Remarks
VCC Turn On
Threshold VCC ON 10.65 11.3 11.95 V
VCC Turn Off
Threshold (Under
Voltage Lock Out)
VCC UVLO 9.2 9.8 10.4 V
VCC Turn On/Off
Hysteresis VCC HYST 1.5 V
Operating Current ICC 10 13 mA Cload=1nF, FSW=181kHz
6 8 mA
Standby Mode (Inactive Gate,
Inactive Internal Oscillator)
VFB<VOLP
See State Transition Diagram
Startup Current ICCSTART 175 uA VCC=VCC ON - 0.1V
Sleep Current ISLEEP 125 200 uA
Sleep Mode (Inactive Gate,
Inactive Oscillator)
- VOVP<VSLEEP,OFF
See State Transition Diagram
Sleep Mode
Threshold (Enable) VSLEEP,ON 0.80 0.90 1.00 V
IC Enable threshold,
Bias on OVP pin
Sleep Mode
Threshold (Disable) VSLEEP,OFF 0.53 0.60 0.67 V IC Disable threshold,
Bias on OVP pin
IR1155S
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Oscillator Section
Parameter Symbol Min. Typ. Max. Units Remarks
Switching Frequency FSW 48 200 kHz 200khz:C=430pF approx.
48kHz: C=2nF approx.
Oscillator Charge Current IOSC(CHG) 200 µA
Oscillator Discharge
Current
IOSC(DCHG) 6.6 mA
Oscillator Peak VOSC PK 4 V
Oscillator Valley VOSC VAL 2 V
5 % C=2nF, TA = 25°C
Initial Accuracy FSW ACC
8 % C=500pF, TA = 25°C
Voltage Stability VSTAB 0.2 1 % 14V < VCC < 19V
Temperature Stability TSTAB 2 % -25°C ≤ TJ ≤ 125°C
Total Variation FVT 10 % Line & Temperature
Maximum Duty Cycle DMAX 94 99 %
Minimum Duty Cycle DMIN 0 % Pulse Skipping
Protection Section
Parameter Symbol Min. Typ. Max. Units Remarks
Open Loop Protection
(OLP) VFB Threshold V OLP 17 19 21 % VREF Bias on VFB pin
Output Over Voltage
Protection (OVP) V OVP 104.5 106.5 108.5 % VREF Bias on OVP/EN pin
Output Over Voltage
Protection (OVP) Reset VOVP(RST) 100.2 102.2 104.2 % VREF Bias on OVP/EN pin
Peak Current Limit
Protection (IPK LMT) ISNS
Voltage Threshold
V ISNS -0.85 -0.77 -0.69 V Bias on ISNS pin
OVP Input Bias Current IOVP(Bias) -0.2 µA
IR1155S
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Internal Voltage Reference Section
Voltage Error Amplifier Section
Parameter Symbol Min. Typ. Max. Units Remarks
Transconductance gm 35 50 65 µS
30 44 58 TAMB = 25°C
Source Current IOVEA(SRC)
20 44 90
µA
-25°C ≤TAMB≤ 125°C
-57 -43 -30 TAMB = 25°C
Sink Current IOVEA(SNK)
-90 -43 -20
µA
-25°C ≤TAMB≤ 125°C
Soft Start Delay Time tSS 35 msec RGAIN = 1kΩ, CZERO = 0.33uF,
CPOLE = 0.01uF
VCOMP Voltage (Fault) VCOMP FLT 1 1.4 V
@ 100µA steady state
current
Effective VCOMP Voltage VCOMP EFF 4.6 4.9 5.2 V
VFB Input Bias Current IIB(Bias) -0.2 µA VFB=4.9V
Output Low Voltage VOL 0.25 V
Output High Voltage VOH 5 5.4 V
VCOMP Start Voltage VCOMP START 240 340 460 mV
Parameter Symbol Min. Typ. Max. Units Remarks
Reference Voltage VREF 4.9 5 5.1 V TA = 25°C
Line Regulation RREG 10 20 mV 14 V < VCC < 19V
Temp Stability TSTAB 0.4 % -25°C ≤ TAMB ≤ 125°C
Total Variation ΔVTOT 4.85 5.1 V Line & Temperature
IR1155S
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Current Amplifier Section
Parameter Symbol Min. Typ. Max. Units Remarks
DC Gain gDC 3.1 V/V
Corner Frequency fC 5 kHz - Average current mode, Note 1
Input Offset Voltage VIO 4 16 mV Note 1
ISNS Bias Current IISNS(Bias) -57 -13 µA
Blanking Time TBLANK 220 370 520 ns
Gate Driver Section
Parameter Symbol Min. Typ. Max. Units Remarks
Gate Low Voltage VGLO 0.8 V IGATE=200mA
12 13 14 V Internal Gate clamp
Gate High Voltage VGTH
10 V VCC = 11.5V
Rise Time tr 20 ns CLOAD = 1nF
Fall Time tf 20 ns CLOAD = 1nF
Output Peak Current IOPK 1.5 A CLOAD = 10nF, Note 1
Gate Voltage @ Fault VG fault 0.08 V IGATE = 20mA
Note 1 – Guaranteed by design, but Not tested in production
IR1155S
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Lead Assignments & Definitions
8
7
6
5 4
3
2
1
Lead Assignment Pin# Symbol Description
1
2
3
4
5
6
7
8
COM
FREQ
ISNS
OVP
COMP
VFB
VCC
GATE
Ground
Frequency Set
Current Sense
Output Over Voltage Detect / Enable
Voltage Loop Compensation
Output Voltage Sense
IC Supply Voltage
Gate Drive Output
IR1155S
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Block Diagram
VREF
VFB
COMP
VCOMP Discharge
VOVP
VOLP
Q
S
R1
ISNS
Vm
OSCILLATOR
COM
VCC
GATE
RESET
OVP
V BIAS
V BIAS
V BIAS
V BIAS
V BIAS
VBIAS
MAX
DUTY CYCLE
LIMIT
Blanking
Pulse at Ton
V BIAS
V BIAS
VCC
Q
RQ
S1
250mV
VISNS(PK)
OVP
VSLEEP
Enable
Comparator
(SLEEP MODE)
VBIAS
FREQ
RAMP
+
-
VSUMMER
V BIAS
UVLO
VOVP = 106% VREF
VREF
VOLP = 19%VREF
Internal Rail
&
Precision
Reference
250mV
VSLEEP
VOUV = 50% VREF
80% VREF
OVP
VCC OK
PWM OFF
GATE OFF
GATE OFF
RESET
SET
MAX
DUTY
OCP
OSC
BLANK
0
VCOMP
Open Loop
Comparator
(Stand-By Mode)
SLEEP
(POWER
OFF)
UVLO/SLEEP
STNDBY
VCOMP Discharge
Threshold
Comparator
Overvoltage
Comparator
Peak
Overcurrent
Comparator
SLEEP
IR1155S
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State & Transition Diagrams
Note: Soft-Start & Normal modes are essentially the same (differentiation above is for purpose of clarity
only)
IR1155S
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V
CC(ON)
V
CC(UVLO)
NORMAL UVLOUVLO
VCC Undervoltage Lockout
Vol tage on VCC pi n
V
CC(ON)
V
CC(UVLO)
NORMAL UVLOUVLO
VCC Undervoltage Lockout
Vol tage on VCC pi n
Timing Diagrams
106.5% VREF
19% VREF
SOFT
START (OLP)
STAND_BY
(OLP)
Output Protection
100% VREF
OVP NORMAL
102.2% VREF
STAND-BY
IR1155S
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IR1155 General Descripti on
The μPFC IR1155 IC is intended for power factor
correction in continuous conduction mode Boost
PFC converters operating at fixed switching
frequency with average current mode control.
The switching frequency is programmable any
where from 48kHz to 200khz. The IC operates
according to IR's proprietary "One Cycle Control"
(OCC) PFC algorithm, which is based on the re-
settable integrator principle. When operating a
AC-DC Boost converter, power factor correction
can be achieved using this algorithm without AC
input line sensing.
Theory of Operation
The OCC algorithm works using two loops - a
slow outer voltage loop and a fast inner current
loop. The outer voltage loop monitors the VFB
pin to maintain regulation of boost converter
output voltage and generates a constant error
signal. The inner current loop exploits the
embedded input voltage information in the boost
converter duty cycle to generate a current
reference for power factor correction. The
combination of the two control elements forces
the amplitude and shape of the input current to
be proportional to and in phase with the input
voltage while maintaining output voltage
regulation. This is true so long as operation in
continuous conduction mode is maintained.
Average current mode operation is envisaged by
filtering the switching frequency ripple from the
current sense signal in the current loop using an
on-chip filter.
The IC determines the boost converter
instantaneous duty cycle using the voltage
feedback loop error signal Vm and the current
sense signal VISNS, which is the voltage at the
current sense pin of the IC. The PWM ramp is
generated using a resettable integrator that
tracks Vm every switching cycle. The current
sense signal is amplified by the current amplifier
averaged to remove the ripple component and
fed into the summing node where it is subtracted
from the voltage error signal, Vm. The resulting
voltage (Vm - gDC.VISNS) is compared with the
PWM ramp signal by the PWM comparator to
determine the gate drive duty cycle. The
instantaneous duty cycle is mathematically given
by:
D = (Vm - gDC.VISNS) /Vm
A more detailed description of IR1155 theory of
operation is available in Application Note.
Feature set
The IR1155 offers a host of advanced features and
system protections functions, which makes it the
most feature-intensive IC in PFC market in a
compact 8-pin package.
User-Programmable Switchin g Frequency
IR1155 IC operates under fixed switching
frequency. The switching frequency is user-
programmed by inserting a capacitor between
FREQ & COM pins. A pair of current sources inside
the IC source/sink current in/out of the capacitor
alternately thus generating a constant-slope saw-
tooth ramp signal between a pre-determined peak &
valley voltage pair (typically between 2V to 4V). This
saw-tooth signal is the oscillator signal of the IC.
The frequency of operation of the IC can be
programmed anywhere between 48kHz and 200kHz
by suitably sizing the capacitor. The oscillator signal
is a key control signal and is used by the resettable
integrator block of the IC to generate the internal
PWM ramp every switching cycle.
IC Supply Circuit & Low start-up current
The IR1155 UVLO circuit maintains the IC in UVLO
mode during start-up if VCC pin voltage is less than
the VCC turn-on threshold, VCC,ON and current
consumption is less than ICC,START. Should VCC pin
voltage should drop below UVLO threshold VCC, UVLO
anytime after start-up, the IC is pushed back into
UVLO mode (VCOMP pin is discharged) and VCC
pin has to exceed VCC,ON again to re-start operation.
It is noted that there is no internal clamping of the
VCC pin.
User initiated Micropower Sleep mode
The IC can be actively pushed into a micropower
sleep mode where current consumption is less than
ICC,SLEEP by pulling OVP/EN pin below the Sleep
threshold, VSLEEP(OFF), even while VCC is above
VCC,ON. This allows the user to disable PFC during
application stand-by situations in order to meet
regulations (Blue Angel, Green Power etc). When
OVP/EN pin is pulled low, the VCOMP pin of the IC
is actively discharged as the IC is relegated to the
Sleep mode. This enables the IC to go through soft-
start when the IC is re-enabled. Since VSLEEP(OFF) is
less than 1V, even logic level signals can be
employed to disable and enable the IC.
IR1155S
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IR1155 General Descripti on
Programmable Soft Start
The soft start process controls the rate of rise of
the voltage feedback loop error signal thus
providing a linear control on RMS input current
that the PFC converter will admit. The soft start
time is essentially controlled by voltage error
amplifier compensation components selected and
is therefore user programmable to some degree
based on desired loop crossover frequency.
Gate Drive Capability
The gate drive output stage of the IC is a totem
pole driver with 1.5A peak current drive
capability. The gate drive is internally clamped at
13V (Typ). Gate drive buffer circuits can be easily
driven with the GATE pin of the IC to suit any
system power level.
System Protection Features
IR1155 protection features include DC bus
Overvoltage protection (OVP) via a dedicated pin,
Open-loop protection (OLP), Cycle-by-cycle peak
current limit (IPK LIMIT), Soft-current limit and
VCC under voltage lock-out (UVLO).
- Overvoltage voltage protection (OVP) feature in
IR1155 is achieved using a dedicated pin called
the OVP/EN pin. The input of OVP comparator is
connected the OVP pin. When the OVP pin
voltage exceeds VOVP, an overvoltage situation is
detected and the gate drive is immediately
terminated. The gate drive is re-enabled only
after OVP pin voltage drops below VOVP(RST). The
use of a dedicated OVP/EN pin ensures that the
system is protected from catastrophic
overvoltages, even if the feed-back loop
(connected to the VFB pin) encounters any
failure. This ensures the best possible system
overvoltage protection against extremes of
situations.
- Open Loop Protection (OLP) is activated
whenever the VFB pin voltage falls below VOLP
threshold. The gate drive is then immediately
disabled, VCOMP is actively discharged and the
IC is pushed into Stand-by mode. The IC will re-
start (with soft-start) once the VFB pin voltage
exceeds VOLP again. There is no voltage
hysteresis associated with this feature. During
start-up the IC is held in Stand-by until this pin
exceeds VOLP.
- Soft-current limit is an output voltage fold-back type
protection feature that is encountered when the RMS
current in the PFC converter exceeds a certain
magnitude that causes the internal error signal of the
voltage feedback, Vm to saturate at its highest value.
Amplitude of Vm signal is directly proportional to the
RMS input current admitted into the PFC converter.
In effect, once Vm saturates, the maximum RMS
current admissible into the PFC converter has been
encountered. Any attempt to increase the RMS
current beyond this limit causes the IC to limit the
duty cycle delivered to the PFC converter, which then
has the effect of causing the DC bus voltage to droop
i.e. output voltage folds-back. The current level at
which Vm saturates is closely related to the value of
the current sense resistor selected for the PFC
converter. In one way, this feature can be perceived
to offer an overpower limitation of sorts at the
conditions at which current sense design is
performed (minimum VAC & maximum output
power). For details, please refer to IR1155
Application Note.
- Cycle-by-cycle peak current limit protection
instantaneously turns-off the gate output whenever
the ISNS pin voltage exceeds VISNS(PK) threshold in
magnitude. The gate drive output is re-enabled only
after the magnitude of the ISNS pin voltage drops
below the VISNS(PK) threshold. It is clarified that even
though the IC operates based on average current
mode control, since the averaging circuit is
decoupled from the peak current limit comparator
input, the IC is still able to provide instantaneous
response to a system overcurrent condition. This
protection feature incorporates a leading edge
blanking circuit following the comparator to improve
noise immunity.
- VCC Under Voltage Lockout protection maintains
the IC in a low current consumption, UVLO mode
during start-up if VCC pin voltage is less than the
VCC turn-on threshold, VCC,ON. In UVLO mode the
current consumption is less than ICC,START which is
typically about 200uA. Should VCC pin voltage
should drop below UVLO threshold VCC, UVLO anytime
after start-up, the IC is pushed back into UVLO mode
(VCOMP pin is discharged) and VCC pin has to
exceed VCC,ON again to re-start operation.
IR1155S
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IR1155 Pin Description
Pin COM: This is ground potential pin of the IC.
All internal devices are referenced to this point. A
star-connection point, very close to this pin, is
recommended in PCB lay-out in order to
reference the return traces of the various control
loops to the COM potential of the IC.
Pin COMP: External circuitry from this pin to
ground compensates the system voltage loop and
programs the soft start time. The COMP pin is
essentially the output of the voltage error
amplifier. VCOMP is actively discharged using an
internal switch & resistance inside the IC
whenever the IC is pushed into Stand-by mode
(Open Loop Condition) or UVLO/Sleep mode. The
IC is designed not to start-up (from UVLO, Sleep
or Stand-by modes) when there is a pre-bias on
VCOMP pin that is greater than VCOMP,START. The
VCOMP-COM loop represents a very important
control loop to the IC and hence a dedicated PCB
trace loop is recommended for layout (star-
connection to GND potential) for noise free, stable
operation.
Pin ISNS: ISNS pin is the inverting input to the
current sense amplifier of the IC. The voltage at
this pin is the negative voltage drop sensed
across the system current sense resistor and thus
represents the inductor current sense signal to the
IC for determining gate drive duty cycle. ISNS pin
is also the inverting input to the cycle-by-cycle
peak current limit comparator. Whenever this pin
voltage exceeds VISNS(PK) threshold in magnitude,
the gate drive is instantaneously disabled. Any
external filtering of the ISNS pin must be
performed carefully in order to ensure that the
integrity of the current sense signal is maintained
for cycle-by-cycle protection.
Pin FREQ: This is the user-programmable
frequency pin. The switching frequency is
programmed by inserting a capacitor between
FREQ & COM pins. A pair of current sources
inside the IC source/sink current in/out of the
capacitor alternately thus generating a constant-
slope saw-tooth ramp signal between a pre-
determined peak & valley voltage pair (typically
between 2V to 4V). This saw-tooth signal is the
oscillator signal of the IC. The frequency of
operation of the IC can be programmed anywhere
between 48kHz and 200kHz by suitably sizing the
capacitor.
The FREQ-COM loop represents yet another very
important control loop to the IC and hence a
dedicated PCB trace loop is recommended in lay-
out (star-connection to GND potential) for noise
free, stable operation.
Pin OVP/EN: The OVP/EN pin is connected to the
input of the overvoltage comparator and is used to
detect output overvoltage situations. The output
voltage information is communicated to the OVP pin
using a resistive divider. This pin also serves the
second purpose of an ENABLE pin. The OVP/EN
pin can be used to activate the IC into “micropower
sleep” mode by pulling the voltage on this pin below
the VSLEEP threshold.
Pin VFB: The converter output voltage is sensed
via a resistive divider and fed into this pin. VFB pin
is the inverting input of the output voltage error
amplifier. The non-inverting input of this amplifier is
connected to an internal 5V reference. The
impedance of the divider string must be low enough
that it does not introduce substantial error due to the
input bias currents of the amplifier, yet high enough
to minimize power dissipation. Typical value of
external divider impedance will be 1MΩ. VFB pin is
also the inverting input to the Open Loop
comparator. The IC is held in Stand-by Mode
whenever VFB pin voltage is below VOLP threshold.
Pin VCC: This is the supply voltage pin of the IC
and sense node for the under-voltage lock out
circuit. It is possible to turn off the IC by pulling this
pin below the minimum turn off threshold voltage,
VCC,UVLO without damage to the IC. This pin is not
internally clamped.
Pin GATE: This is the gate drive output of the IC.
This drive voltage is internally clamped to 13V(Typ)
and provides a drive current of ±1.5A peak with
matched rise and fall times.
IR1155S
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IR1155 Modes of operation (refer to States & Transitions Diagram)
UVLO/Sleep Mode: The IC is in the UVLO/Sleep
mode when either the VCC pin voltage is below
VCC,UVLO and/or the OVP/EN pin voltage is below
VSLEEP. The UVLO/Sleep mode is accessible from
any other state of operation. This mode can be
actively invoked by pulling the OVP/EN pin below
the Sleep threshold VSLEEP even if VCC pin
voltage is above VCC,ON. In the UVLO/Sleep state,
the gate drive circuit is inactive, most of the
internal circuitry is unbiased and the IC draws a
quiescent current of ISLEEP which is typically 200uA
or less. Also, the internal logic of the IC ensures
that whenever the UVLO/Sleep mode is actively
invoked, the COMP pin is actively discharged
below VCOMP,START prior to entering the sleep
mode, in order to facilitate soft-start upon
resumption of operation.
Stand-by Mode: The IC is placed in Stand-by
mode whenever an Open-loop situation is
detected. An open-loop situation is sensed
anytime VFB pin voltage is less than VOLP. All
internal circuitry is biased in the Stand-by Mode,
but the gate is inactive and the IC draws a few mA
of current. This state is accessible from any other
state of operation of the IC. COMP pin is actively
discharged to below VCOMP,START whenever this
state is entered from normal operation in order to
facilitate soft-start upon resumption of operation.
Soft Start Mode: During system start-up, the soft-
start mode is activated once the VCC voltage has
exceeded VCC,ON, the VFB pin voltage has
exceeded VOLP and OVP pin voltage has
exceeded VSLEEP(ON). The soft start time is the time
required for the VCOMP voltage to charge
through its entire dynamic range i.e. through
VCOMP,EFF. As a result, the soft-start time is
dependent upon the component values selected
for compensation of the voltage loop on the
COMP pin. As VCOMP voltage raises gradually,
the IC allows a higher and higher RMS current
into the PFC converter. This controlled increase
of the input current amplitude contributes to
reducing system component stress during start-
up. It is clarified that, during soft-start, the IC is
capable of full duty cycle modulation (from 0% to
MAX DUTY), based on the instantaneous ISNS
signal from system current sensing. .
For all practical purposes, the Soft-start mode of
the IC is the same as the Normal mode (only
difference being that the DC bus voltage is
approaching the regulation point). All protection
functions of the IC are active during soft-start
mode.
Normal Mode: The IC enters the normal operating
mode seamlessly following conclusion of soft-start.
At this point the DC bus is well regulated and all
protection functions of the IC are active. If, from
the normal mode, the IC is pushed into either a
Stand-by mode or Sleep mode then COMP pin is
actively discharged below VCOMP,START and system
will go through soft-start upon resumption of
operation.
OVP Mode: The IC enters OVP fault mode
whenever an overvoltage condition is detected. A
system overvoltage condition is recognized when
OVP/EN pin voltage exceeds VOVP threshold. When
this happens the IC immediately disables the gate
drive. The gate drive is re-enabled only when
OVP/EN pin voltage is less than VOVP(RST)
threshold. This state is accessible from both the
soft start and normal modes of operation.
IPK LIMIT Mode: The IC enters IPK LIMIT fault
mode whenever the magnitude of ISNS pin voltage
exceeds the VISNS(PK) threshold triggering cycle-by-
cycle peak over current protection. When this
happens, the IC immediately disables the gate
drive. Gate drive is re-enabled when magnitude of
ISNS pin voltage drops below VISNS(PK) threshold.
This state is accessible from both the soft start and
normal modes of operation.
IR1155S
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0.01
0.1
1
10
7.0 V 9.0 V 11.0 V 13.0 V 15.0 V 17.0 V
I
SUPPLY
(mA)
Supply voltage
Figure 1: Supply Current vs.
Supply Voltage
9.0 V
9.5 V
10.0 V
10.5 V
11.0 V
11.5 V
12.0 V
-50 °C 0 °C 50 °C 100 °C 150 °C
VCC UVLO Thresholds
Te m p e r a t u r e
VCC UV+
VCC UV-
Figure 2: Undervoltage Lockout vs.
Temperature
8.7
8.8
8.9
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
-50 °C 0 °C 50 °C 100 °C 150 °C
I
CC
Supply Current (mA)
Temperature
Icc @ C
LOAD
=1nF
Figure 3: Icc Current vs. Temperature
(@181kHz frequency)
50.0
70.0
90.0
110.0
130.0
150.0
170.0
-50 °C 0 °C 50 °C 100 °C 150 °C
Current (uA)
Te m p e r a tu r e
I
CCSTART
and I
SLEEP
ISLEEP
ICCSTART
Figure 4: Startup Current and Sleep
Current vs. Temperature
IR1155S
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20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
180.0
200.0
-50 °C 0 °C 50 °C 100 °C 150 °C
Switching Frequency (KHz)
Te m p e r a t u r e
CT=500pF
CT=2nF
Figure 5: Switching Frequency vs.
Temperature
4.95
4.97
4.99
5.01
5.03
5.05
-50 °C 0 °C 50 °C 100 °C 150 °C
Reference Voltage (V)
Temperature
Figure 6: Reference Voltage vs.
Temperature
40.0
42.0
44.0
46.0
48.0
50.0
52.0
54.0
-50 °C 0 °C 50 °C 100 °C 150 °C
EA Transconductance g
m
(uS)
Te m p e r a t u r e
Figure 7: Voltage Error Amplifier
Transconductance vs. Temperature
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
-50 °C 0 °C 50 °C 100 °C 150 °C
Error Amplifier Sou rce/Sin k Curren t (uA)
Temperature
Source
|Sink|
Figure 8: Voltage Error Amplifier Source
& Sink Current vs. Temperature
IR1155S
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3.00
3.05
3.10
3.15
3.20
3.25
3.30
-50 °C 0 °C 50 °C 100 °C 150 °C
Current Sense Amplifier DC Gain g
DC
(V/V)
Temperature
Figure 9: Current Amplifier DC Gain vs.
Temperature
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-50 °C 0 °C 50 °C 100 °C 150 °C
Peak Current Limit Threshold (V)
Temperature
Figure 10: Peak Current Limit Threshold
VISNS(PK) vs. Temperature
1.00
1.02
1.04
1.06
1.08
1.10
-50 °C 0 °C 50 °C 100 °C 150 °C
OVP Threshold (%Vref)
Te m p e r a t u r e
VOVP
VOVP(RST)
Figure 11: Over Voltage Protection
Thresholds vs. Temperature
40.00
60.00
80.00
100.00
120.00
140.00
160.00
180.00
200.00
400 650 900 1150 1400 1650 1900
Frequency(KHz)
CT(pF)
Frequencyvs.CT
Figure 12: Oscillator Frequency vs.
Programming Capacitor
IR1155S
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Package Details: SOIC8N
IR1155S
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Tape and Reel Details: SOIC8N
E
F
A
C
D
G
A
BH
N
OTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A 7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D 5.45 5.55 0.214 0.218
E 6.30 6.50 0.248 0.255
F 5.10 5.30 0.200 0.208
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 18.40 n/a 0.724
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566
Metric Imperial
IR1155S
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Part Marking Information
IR1155S
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Ordering Information
Standard Pack
Base Part Number Package Type Form Quantity Complete Part Number
Tube/Bulk 95 IR1155SPBF
IR1155S SOIC8N
Tape and Reel 2500 IR1155STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no
responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement
of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or
otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to
change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
