(R) DEVICE SPECIFICATION BiCMOS PLL CLOCK GENERATORS S4402/S4403 FEATURES APPLICATIONS * Generates six clock outputs from 20 MHz to 80 MHz (the S4403 generates ten outputs and HFOUT generates 10MHz to 40MHz) * 21 selectable phase/frequency relationships for the clock outputs * Compensates for clock skew by allowing output delay adjustment down to 3.125 ns increments * TTL outputs have less than 400 ps maximum skew * Lock Detect output indicates loop status * Internal PLL with VCO operating at 160 to 320 MHz * Test Enable input allows VCO bypass for openloop operation in board test * Maximum 1.0 ns of phase error (750 ps from part to part) * Proven 1.0 micron BiCMOS technology * Single +5V power supply operation * 28/44 PLCC packages * CMOS ASIC Systems * High-speed Microprocessor Systems * Backplane Clock Deskew and Distribution GENERAL DESCRIPTION The S4402/S4403 BiCMOS clock generators allow the user to generate multiphase TTL clocks in the 10-80 MHz range with less than 400 ps of skew. Use of a single off-chip filter allows an entire 160-320 MHz phase-locked loop (PLL) to be implemented onchip. Divide-by-two and times-two outputs allow the ability to generate output clocks at half, equal to, or twice the reference clock input frequency. By using the programmable divider and phase selector, the user can select from up to 21 different output relationships. The outputs can be phase-adjusted in increments as small as 3.125 ns to tailor the clocks to exact system requirements. Implemented in AMCC's proven 1.0 micron BiCMOS technology, the S4402 generates six TTL outputs, while the S4403 provides those six plus four duplicates (FOUT0A-FOUT3A) for a total of ten. Output enables are provided for the various banks, allowing clock control for board and system tests. Figure 1. Clock Generator Block Diagram REFCLK NOTE: FOUT0A, FOUT1A, FOUT2A, FOUT3A, and OUTEN2 apply only to the S4403. FBCLK PHASE DETECTOR LOCK CHARGE PUMP FILTER X2FOUT VCO /2 I0 I1 MUX TSTEN Digital SELECT HFOUT DIVIDER AND PHASE CONTROL LOGIC FOUT0A FOUT0 FOUT1A FOUT1 DIVSEL +5V PHSEL0 0V PHSEL1 FOUT2A FOUT2 RESET FOUT3A FOUT3 Analog OUTEN0 +5V OUTEN1 0V OUTEN2 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 1 S4402/S4403 BiCMOS PLL CLOCK GENERATOR FUNCTIONAL DESCRIPTION Frequency and Phase Controls The S4402/S4403 clock generators provide multiple outputs that are synchronized in both frequency and phase to a periodic clock input. Two select pins and an external feedback path allow the user to phaseadjust the six outputs (FOUT0-FOUT3, HFOUT, and X2FOUT) relative to the input clock REFCLK, as well as control their frequency. The DIVSEL input controls the programmable divider that follows the voltage controlled oscillator (VCO). This doubles the lock range of the PLL by allowing the user to select a VCO frequency divided by four (DIVSEL Low) or by eight (DIVSEL High). The frequency of the four FOUT0-FOUT3 outputs (and the duplicate set of the four FOUT0A- FOUT3A outputs on the S4403) is determined by the REFCLK clock frequency and the output that is tied back to the FBCLK input. In addition, the X2FOUT TTL output provides a clock signal identical to the FOUT0 output in the divide-by-four mode, and twice the FOUT0 frequency (maximum frequency of 80 MHz) in the divide-by-eight mode. The HFOUT TTL output provides a clock signal that is in phase with the FOUT0 output, but at half the FOUT0 frequency in both the divide-by-four and divide-by-eight modes. Refer to the Output Select Matrix in Table 3 for the specific relationships. Phase adjustments can be made in increments as small as 3.125 ns. The minimum phase delay between FOUT0-FOUT3 signals is a function of the VCO frequency. The VCO frequency can be determined by multiplying the output frequency by the divide-by ratio of four or eight, controlled by DIVSEL. The minimum phase delay t is equal to the period of the VCO frequency: t = 1 / VCO freq Since the VCO can operate in the 160 MHz to 320 MHz range, minimum phase delay values can range from 6.25 ns to 3.125 ns. Table 1 shows various FOUT/VCO frequencies and the associated phase resolution. The PHSEL1 and PHSEL0 inputs allow the user to select several phase relationships among the four FOUT0-FOUT3 TTL clock outputs. These choices can be seen in Table 2, and the Output Select Matrix provided in Table 3 describes the 21 output configurations available to the user. The two "Select Pins" columns specify the signal levels on the pins PHSEL0 and PHSEL1. These are active High signals. The column entitled "Output Fed to FBCLK" indicates which output (FOUT0-FOUT3, Page 2 HFOUT, or X2FOUT) is externally connected to the feedback input (FBCLK) to produce the resulting waveforms shown in the appropriate row in the table. The last seven columns specify the resulting phase and frequency relationships of each output to the user clock input (REFCLK). A negative value indicates the time by which the output rising edge precedes the input (REFCLK) rising edge. A positive value is the time by which the rising edge of the output follows the rising edge of the input clock. Table 1. Example Phase Resolution FOUT0-3 Divider VCO Min Phase Freq Select Freq Resolution 80 MHz 66 MHz 50 MHz 40 MHz 40 MHz 33 MHz 25 MHz 20 MHz 4 4 4 4 8 8 8 8 320 MHz 266 MHz 200 MHz 160 MHz 320 MHz 266 MHz 200 MHz 160 MHz 3.125 ns 3.75 ns 5.0 ns 6.25 ns 3.125 ns 3.75 ns 5.0 ns 6.25 ns Table 2. Phase Selections PHSEL1 PHSEL0 Phase Relationship 0 0 0 1 1 0 1 1 All at same phase FOUT0-FOUT3 outputs skewed by 90 degrees from each other FOUT1 leads FOUT0 by minimum phase, FOUT2 lags FOUT0 by minimum phase, and FOUT3 lags FOUT0 by 90 degrees FOUT1 lags FOUT0 by minimum phase, FOUT2 lags FOUT1 by minimum phase, and FOUT3 lags FOUT2 by minimum phase Example: In a typical system, designers may need several low-skew outputs, one early clock, one late clock, a clock at half the input clock frequency, and one at twice the input clock frequency. This system requirement can be met by setting PHSEL1 to 1, PHSEL0 to 0, and feeding back FOUT0 to the FBCLK input (Row 10 of Table 3). The result is that FOUT0 will be phase-aligned to REFCLK, FOUT1 will lead REFCLK by a minimum phase delay, FOUT2 will lag REFCLK by a minimum phase delay, FOUT3 will phase-lag REFCLK by 90, HFOUT will be phase-aligned with REFCLK but at half the frequency, and X2FOUT will be either phase-aligned at the same frequency as the reference clock if DIVSEL = 0, or at twice the frequency if DIVSEL = 1. Several other waveform examples and typical applications are provided on pages 7-8 and 7-9. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 BiCMOS PLL CLOCK GENERATOR S4402/S4403 Enabling Outputs Power Supply Considerations The S4402 has two output-enable inputs that control which outputs toggle. (The S4403 has three output-enable inputs.) When held LOW, OUTEN0 controls the frequency doubler output X2FOUT and the half-frequency output HFOUT. OUTEN1 controls the FOUT0-FOUT3 outputs. The third input on the S4403, OUTEN2, controls the duplicate set of four outputs FOUT0A-FOUT3A. When an output enable pin is held High, its associated outputs are disabled and held in a High state. Power for the analog portion of the S4402/S4403 chips must be isolated from the digital power supplies to minimize noise on the analog power supply pins. This isolation between the analog and digital power supplies can be accomplished with a simple external power supply filter (Figure 3). The analog power planes are connected to the digital power planes through single ferrite beads (FB1 and FB2) or inductors capable of handling 25 mA. The recommended value for the inductors is in the range from 5 to 100H, and depends upon the frequency spectrum of the digital power supply noise. The ferrite beads should exhibit 75 impedance at 10 MHz. Filter The FILTER output is a tap between the analog output of the phase detector and the VCO input. This pin allows a simple external filter (Figure 2) to be included in the PLL. AMCC recommends the use of the filter component values shown. This filter was chosen for its ability to reduce the output jitter and filter out noise on the REFCLK input. The filter components should be in surface mounted packages with minimum lead inductance. Decoupling capacitors are also very important to minimize noise. The decoupling capacitors must have low lead inductance to be effective, so ceramic chip capacitors are recommended. Decoupling capacitors should be located as close to the power pins as physically possible. And the decoupling should be placed on the top surface of the board between the part and its connections to the power and ground planes. Figure 2. External PLL Filter Figure 3. External Power Supply Filter 20 A VCC A +5V 0.1F FB1 ANALOG +5V 0.1 F S4402 1.5k FILTER 19 DIGITAL +5V 10 F Tantalum (optional) FB2 ANALOG GND DIGITAL GND Reset Test Capabilities When the RESET pin is pulled low, all the internal states go to zero one clock cycle (from the VCO or REFCLK in the test mode) before the outputs go low. After the chip is reset, the PLL requires a resynchronization time of 5ms before lock is again achieved. The TSTEN input puts the S4402/S4403 into a test mode and allows users to bypass the VCO and provide their own clock through the REFCLK input. When TSTEN is High, the VCO is turned off and the REFCLK signal drives the divider/phase adjust circuitry, directly sequencing the outputs. The TSTEN and REFCLK inputs join the divider circuitry after the initial divide-by-two stage. Therefore, REFCLK is divided by two in the divide-by-four mode and divided by four in the divide-by-eight mode. Lock Detect A lock detect function is provided by the LOCK output. When REFCLK and FBCLK are within 2-4 ns of each other, the PLL is in lock, and the LOCK output goes High. Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 3 S4402/S4403 BiCMOS PLL CLOCK GENERATOR PIN DESCRIPTIONS Input Signals Output Signals REFCLK. Frequency reference supplied by the user that, along with the output tied to the FBCLK input, determines the frequency of the FOUT0-FOUT3 outputs. Also replaces the VCO output when TSTEN is high (after first divide-by-two stage in divider phase control logic). See TSTEN. FILTER. A tap between the analog output of the phase detector and the VCO input. Allows a simple external filter (a single resistor and one capacitor) to be included in the PLL. FBCLK. Feedback clock that, along with the REFCLK input, determines the frequency of the FOUT0-FOUT3 outputs. One output is selected to feed back to this input. (See Table 3.) DIVSEL. Controls the divider circuit that follows the VCO. When DIVSEL is low, the VCO frequency is divided by four. When DIVSEL is high, the VCO frequency is divided by eight. (See Tables 1 and 3.) PHSEL0. This input, along with PHSEL1, allows selection of the phase relationship among the four FOUT0-FOUT3 outputs. See Tables 2 and 3 for the selection choices. PHSEL1. Along with PHSEL0, allows selection of the phase relationship among the four FOUT0-FOUT3 outputs. See Tables 2 and 3 for the selection choices. OUTEN0. Active Low. Output enable signal that controls which outputs toggle. Controls the frequency doubler output (X2FOUT) and the half-frequency output (HFOUT). OUTEN1. Active Low. Output enable signal that controls which outputs toggle. Controls the FOUT0- FOUT3 outputs. X2FOUT. Provides a clock signal identical to the FOUT0 output in the divide-by-four mode and twice the FOUT0 frequency (maximum of 80 MHz) in the divide-by-eight mode. FOUT0. Clock output. FOUT1. Clock output. FOUT2. Clock output. FOUT3. Clock output. HFOUT. Provides a clock signal in phase with the FOUT0 output, but at half the FOUT0 frequency in both the divide-by-four and divide-by-eight modes. LOCK. Goes high when REFCLK and FBCLK are within 2-4 ns of each other, demonstrating that the PLL is in lock. FOUT0A. (S4403 only.) Clock output--duplicates FOUT0. FOUT1A. (S4403 only.) Clock output--duplicates FOUT1. FOUT2A. (S4403 only.) Clock output--duplicates FOUT2. FOUT3A. (S4403 only.) Clock output--duplicates FOUT3. OUTEN2. (S4403 only.) Active Low. Controls the duplicate set of outputs to FOUT0-FOUT3 (FOUT0A, FOUT1A, FOUT2A, AND FOUT3A). RESET. Active Low. Initializes internal states for test purposes. TSTEN. Active High. Allows REFCLK to drive the divider phase adjust circuitry, after the first divide-bytwo stage. Therefore, REFCLK is divided by two in the divide-by-four mode, and divided by four in the divide-by-eight mode, and used to directly sequence the outputs. Page 4 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 S4402/S4403 BiCMOS PLL CLOCK GENERATOR Table 3. Output Select Matrix Configuration Number Select Pins Output Fed to FBCLK PHSEL1 PHSEL0 Output Phase Relationships FOUT0 FOUT1 /4 FOUT2 FOUT3 HFOUT 1 2 3 4 5 6 7 8 9 10 11 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 FOUT0-FOUT3 HFOUT X2FOUT (/8) FOUT0 FOUT1 FOUT2 FOUT3 HFOUT X2FOUT (/8) FOUT0 FOUT1 0 2(0) 0/2 0 -Q -2Q -3Q 2(0) 0/2 0 t 0 2(0) 0/2 Q 0 -Q -2Q 2(Q) Q/2 -t 0 0 2(0) 0/2 2Q Q 0 -Q 2(2Q) 2Q/2 t 2t 0 2(0) 0/2 3Q 2Q Q 0 2(3Q) 3Q/2 Q Q+t 0/2 0 0/4 0/2 -Q/2 -2Q/2 -3Q/2 0 0/4 0/2 t/2 12 13 14 15 16 17 18 19 20 21 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 FOUT2 FOUT3 HFOUT X2FOUT (/8) FOUT0 FOUT1 FOUT2 FOUT3 HFOUT X2FOUT (/8) -t -Q 2(0) 0/2 0 -t -2t -3t 2(0) 0/2 -2t -Q-t 2(-t) -t/2 t 0 -t -2t 2(t) t/2 0 -Q+t 2(t) t/2 2t t 0 -t 2(2t) 2t/2 Q-t 0 2(Q) Q/2 3t 2t t 0 2(3t) 3t/2 -t/2 -Q/2 0 0/4 0/2 -t/2 -2t/2 -3t/2 0 0/4 Notes: 1. 2. 3. 4. 5. 6. /8 X2FOUT 0 2(0) 0 -Q -2Q -3Q 2(0) 0 t -t -Q 2(0) 0 -t -2t -3t 2(0) 2(0) 4(0) 0 2(0) 2(-Q) 2(-2Q) 2(-3Q) 4(0) 0 2(0) 2(t) 2(-t) 2(-Q) 4(0) 0 2(0) 2(-t) 2(-2t) 2(-3t) 4(0) 0 "0" implies the output is aligned with REFCLK. "t" implies the output lags REFCLK by a minimum phase delay. "Q" implies the output lags REFCLK by 90 of phase "-t" implies the output leads REFCLK by a minimum phase delay. "-Q" implies the output leads REFCLK by 90 of phase. "2( )" implies the output is at twice the frequency of REFCLK. Legend Table entry Waveform Table entry Waveform Table entry REFCLK REFCLK REFCLK 0 Q 2(0) t 2Q 0/2 2t -Q 4(0) Waveform 0/4 -t -t 0 t 2t Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 -90 0 90 180 Page 5 S4402/S4403 EXAMPLES Figure 4. Configuration Examples FBCLK = FOUT0 PHSEL1 = 0 PHSEL0 = 0 REFCLK FOUT0 FOUT1 FOUT2 (a) S4402 Input Low Low REFCLK X2FOUT HFOUT PHSEL0 FOUT0 PHSEL1 FOUT1 FOUT2 FOUT3 FOUT3 HFOUT (DIVSEL = 0) X2FOUT FBCLK (DIVSEL = 1) X2FOUT FBCLK = HFOUT PHSEL1 = 0 PHSEL0 = 0 REFCLK FOUT0 FOUT1 FOUT2 (b) S4402 Input Low Low REFCLK X2FOUT HFOUT PHSEL0 FOUT0 PHSEL1 FOUT1 FOUT2 FOUT3 FOUT3 HFOUT (DIVSEL = 0) X2FOUT FBCLK (DIVSEL = 1) X2FOUT FBCLK = HFOUT PHSEL1 = 1 PHSEL0 = 1 REFCLK FOUT0 FOUT1 FOUT2 S4402 Input High High REFCLK X2FOUT HFOUT PHSEL0 FOUT0 PHSEL1 FOUT1 FOUT2 FOUT3 FBCLK (c) FOUT3 HFOUT (DIVSEL = 0) X2FOUT (DIVSEL = 1) X2FOUT 0 t 2t 3t Page 6 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 BiCMOS PLL CLOCK GENERATOR S4402/S4403 TYPICAL APPLICATIONS The S4402/S4403 chips are designed to meet a large variety of system clocking requirements. Several typical applications are provided below. Application 1. High-Frequency, Low-Skew Clock Generation XTAL Clock Outputs at twice, equal to, or half the input frequency REFCLK S4402 One of the most basic capabilities of the S4402/ S4403 devices is generating multiple phasealigned low-skew clocks at various multiples of the input clock frequency. For example, in a multipleboard system a half-frequency clock can be generated for use across the backplane, where it is simpler to route a low-speed signal. This signal can then be doubled on the boards, and synchronization will be maintained. Application 2. Low-Skew Clock Distribution One common problem in clocking high-speed systems is that of distributing several copies of a system clock while maintaining low skew throughout the system. The S4402/S4403 devices guarantee low skew among all the clocks in the system, as they have effectively zero delay between their input and output signals, with an output skew of less than 400 ps. The user can also adjust the phases of the outputs in increments as small as 3.125 ns, for load and trace length matching. XTAL REFCLK S4402 REFCLK S4402 REFCLK S4402 S4402 Application 3. Delay Compensation REFCLK S4402 ASIC Common bus Since the relative edges of the S4402/S4403 outputs can be precisely controlled, these chips can be used to compensate for different delays due to trace lengths or to internal chip delays, simplifying board layout and bus timing. In the example shown, the two ASICs have a difference of several nanoseconds in their propagation delays. The S4402s ensure that the output signals are aligned, so that the data valid uncertainty on the common bus is minimized. REFCLK Input Clock REFCLK S4402 ASIC Clock tree output Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 7 BiCMOS PLL CLOCK GENERATOR S4402/S4403 ABSOLUTE MAXIMUM RATINGS Commercial TTL Supply Voltage VCC (VEE = 0) 7.0 V TTL Input Voltage (VEE = 0) 5.5 V Operating Temperature 0C to 70C ambient Operating Junction Temperature TJ + 130C Storage Temperature -65C to +150C RECOMMENDED OPERATING CONDITIONS Commercial Parameter Min Nom Max Units TTL Supply Voltage (VCC) 4.75 5.0 5.25 V 0 -- 70 C Operating Temperature (ambient) Junction Temperature (ambient) -- -- 130 C DC CHARACTERISTICS Symbol Parameter DC Test Conditions VIH2 Input HIGH voltage Guaranteed input HIGH voltage for all inputs VIL2 Input LOW voltage Guaranteed input LOW voltage for all inputs VIK Input clamp diode voltage VCC = Min, IIN = -18mA Min 2.4 2.0 VCC = Min VOL Output LOW voltage VCC = Min IIH Input HIGH current VCC = Min, VIN = 2.4V II Input HIGH current at max VCC = Max, VIN = VCC IIL Input LOW current VCC = Min, VIN = 0.5V IOS4 Output short circuit current Units V -0.8 IOH = -24mA3 (COM) IOL = 24mA3 (COM) Output HIGH voltage Max 2.0 IOH = -12mA3 (COM) VOH Typ1 0.8 V -1.2 V V V 0.5 V -200 A 50 A 1.0 mA OUTEN2 -500 A Other -50 A -100 mA OUTEN2 Other VCC = Max, VOUT = 0V -25 ICC Static VCC = Max COM 70 mA ICC Total ICC (Dynamic and Static) VLOAD = 25pF at 50 MHz COM 190 mA 1. Typical limits are at 25C, VCC = 5.0V. 2. These input levels should only be tested in a static, noise-free environment. 3. IOH/IOL values indicated are for DC test correlation. Actual dynamic currents are significantly higher and are optimized to balance rise and fall times. 4. Maximum test duration is one second. Page 8 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 S4402/S4403 BiCMOS PLL CLOCK GENERATOR Table 4. AC Specifications S4402/3-66 Symbol S4402/3-80 Description Min Max Min Max fVCO VCO Frequency 160 266 160 320 MHz fREF REFCLK Frequency 10 66 10 80 MHz REFCLK Minimum Pulse Width 7.0 tPE Phase Error between REFCLK and FBCLK -1.0 tPED Phase Error Difference from Part to Part1 MPWREF tSKEW 6.0 ns 0 -1.0 0 ns 0 750 0 750 ps ps 0 400 0 400 tDC Output Duty Cycle3 45 55 45 55 % fFOUT FOUT Frequency4 20 66 20 80 MHz fHFOUT HFOUT Frequency4 10 33 10 40 MHz f2XFOUT tPS tPSJ Output Skew2 Units 2XFOUT Frequency4 40 Nominal Phase Shift Increment Phase Shift Variation5 66 40 80 MHz 3.75 6.25 3.125 6.25 ns -250 +250 -250 +250 ps tOFD Tpd OUTEN0-2 to FOUTs, Disable 2 7 2 7 ns tOFE Tpd OUTEN0-2 to FOUTs, Enable 2 7 2 7 ns tIRF Input Rise/Fall Time tORF FOUT Rise/Fall Time6 tLOCK tj 1. 2. 3. 4. 5. 6. 7. 8. Loop Acquisition Clock 1 0.5 Time7 Stability8 3 1 3 ns 1.5 0.5 1.5 ns 5 5 ms 500 500 ps Difference in phase error between two parts at the same voltage, temperature and frequency. Output skew guaranteed for equal loading at each output. Outputs loaded with 35pF, measured at 1.5V. CLOAD = 35 pF. All phase shift increments and variation are measured relative to FOUT0 at 1.5V. With 35 pF output loading (0.8 V to 2.0 V transition). Depends on loop filter chosen. (Number given is for example filter.) Clock period jitter with all FOUT outputs operating at 66 MHz and loaded with 25pF using loop filter shown. Parameter guaranteed, but not tested. Figure 5. Timing Waveforms MPW REF MPW REF REFCLK t PE t PE FBCLK t SKEW t SKEW FOUT0-3 HFOUT, X2FOUT FOUT0-3 HFOUT, X2FOUT Output Valid Disabled t OFD t OFE OUTEN0-2 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 9 BiCMOS PLL CLOCK GENERATOR S4402/S4403 BOARD LAYOUT CONSIDERATIONS * No dynamic signal lines should pass through or beneath the filter circuitry area (enclosed by dashed lines in Figure 6) to avoid the possibility of noise due to crosstalk. * The S4402/S4403 chips are sensitive to noise on the Analog +5 V and Filter pins. Care should be taken during board layout for optimum results. * The analog VCC supply can be a filtered digital VCC supply as shown below. The ferrite beads or inductors, FB1 and FB2, should be placed within three inches of the chip. * All decoupling capacitors (C1-C4 = 0.1 F) should be bypassed between VCC and GND, and placed as close to the chip as possible (preferably using ceramic chip caps) and placed on top of board between S4402/S4403 and the power and ground plane connections. * The analog VCC plane should be separated from the digital VCC and ground planes by at least 1/8 inch. Figure 6. Board Layout (S4402 shown) +5 D C2 4 3 2 1 28 27 26 5 25 6 FB2 7 C3 22 9 GND D 21 20 19 11 12 13 14 15 16 17 18 +5 D A GND 23 8 10 24 C1 C6 FB1 R1 +5 A +5 D C4 No signals should pass through the area enclosed by dashed lines Page 10 Component Description C1-C4 0.1 F ceramic capacitor C6 0.1 F ceramic capacitor R1 1.5 K 10% resistor FB1,FB2 Ferrite bead or inductor Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 S4402/S4403 BiCMOS PLL CLOCK GENERATOR DGND 2 RESET FBCLK 3 REFCLK FOUT3 4 LOCK DGND Figure 7. S4402 28 PLCC Package and Pinout 1 28 27 26 D +5V 5 25 DIVSEL FOUT2 6 24 PHSEL0 D +5V 7 23 PHSEL1 DGND 8 FOUT1 S4402A +5V ANALOG 19 FILTER 12 13 14 15 16 17 18 D +5V 20 11 TSTEN 10 D +5V OUTEN1 FOUT0 OUTEN0 +5V ANALOG HFOUT 21 DGND GND-ANALOG 9 X2FOUT 22 All dimensions nominal in inches. 28 PLCC Thermal Resistance Still Air 100 Linear Ft./Min 200 Linear Ft./Min 60C/Watt 50C/Watt 45C/Watt Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 11 S4402/S4403 BiCMOS PLL CLOCK GENERATOR 44 43 42 41 40 DGND 1 RESET 2 NC 3 LOCK FBCLK 4 REFCLK FOUT3A 5 D +5V FOUT3 6 DGND DGND Figure 8. S4403 44 PLCC Package and Pinout D +5V 7 39 D +5V FOUT2A 8 38 DIVSEL FOUT2 9 37 PHSEL0 NC 10 36 PHSEL1 D +5V 11 DGND 12 S4403B 35 NC 34 GND-ANALOG 17 29 18 19 20 21 22 23 24 25 26 27 28 D +5V DGND TSTEN NC D +5V NC FILTER 30 OUTEN2 31 16 OUTEN1 15 FOUT0 OUTEN0 FOUT0A D +5V +5V ANALOG DGND +5V ANALOG 32 HFOUT 33 14 DGND 13 FOUT1 X2FOUT FOUT1A All dimensions nominal in inches. Ordering Information AMCC clock driver products are available in several output skew and shipping configurations. The order number is formed by a combination of: * Device Number * Package Type * Speed Option * Optional Shipping Configuration S4402/03 A - 66 /TD Optional Shipping Configuration Blank = tube /D = dry pack /TD = tape, reel and dry pack Speed Option - 66 = 66 MHz - 80 = 80 MHz Package Option A = 28-pin PLCC (S4402) B = 44-pin PLCC (S4403) Device Number S4402 S4403 Example: S4402A-66/D 28-pin PLCC package, shipped dry packed in the standard tube. Page 12 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 AMCC reserves the right to change specifications for this product in any manner without notice, and substitute devices manufactured to higher grade levels than ordered. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1996 Applied Micro Circuits Corporation Printed in U.S.A./01-03-96 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 13