EK42851-03 - Peregrine Semiconductor

Page 1 of 12

Figure 1. Package Type

32-lead 5 × 5 mm QFN

Product Description

The PE42851 is a HaRP™ technology-enhanced SP5T

high power RF switch supporting wireless applications

up to 1 GHz. It offers maximum power handling of

42.5 dBm continuous wave (CW). It delivers high

linearity and excellent harmonics performance. It has

both a standard and attenuated RX mode. No blocking

capacitors are required if DC voltage is not present on

the RF ports.

The PE42851 is manufactured on Peregrine’s

UltraCMOS® process, a patented variation of silicon-on-

insulator (SOI) technology on a sapphire substrate,

offering the performance of GaAs with the economy and

integration of conventional CMOS.

Product Specification

UltraCMOS® SP5T RF Switch

100–1000 MHz

PE42851

Features

 Dual mode operation: SP5T or SP3T

 HaRP™ technology enhanced

 Fast settling time

 No gate and phase lag

 No drift in insertion loss and phase

 Up to 45 dBm instantaneous power

in 50Ω

 Up to 40 dBm instantaneous power

< 8:1 VSWR

 36 dB TX to RX isolation

 Low harmonics of 2fo and 3fo = –80 dBc

(1.15:1 VSWR)

 ESD performance

 1.5 kV HBM on all pins

 1 kV CDM on all pins

Figure 2. Functional Diagram of SP3T

Configuration

ANT can be tied to TX1 and TX2 or TX3 and TX4

Figure 3. Functional Diagram of SP5T

Configuration

SP5T, standard configuration DOC-02178

Product Specification

PE42851

Page 2 of 12

Table 1. Electrical Specifications @ –40 to +85 °C, VDD = 2.3–5.5V, VSS_EXT = 0V or VDD = 3.4–5.5V,

VSS_EXT = –3.4V (ZS = ZL = 50Ω), unless otherwise noted1

Parameter Path Condition Min Typ Max Unit

Operating frequency 100 1000 MHz

Insertion loss2 ANT–TX

Active TX port 1, 2, 3 or 4 @ rated power (–40 °C, +25 °C)

100–520 MHz

520–1000 MHz

0.25

0.40

0.35

0.55

dB

Active TX port 1, 2, 3 or 4 @ rated power (+85 °C)

100–520 MHz

520–1000 MHz

0.30

0.50

0.40

0.60

dB

Insertion loss2

(un-attenuated state) ANT–RX

Active RX port (–40 °C, +25 °C)

100–520 MHz

520–1000 MHz

0.60

0.70

0.90

dB

Active RX port (+85 °C)

100–520 MHz

520–1000 MHz

0.70

0.80

1.00

dB

1575 MHz for GPS RX, < –10 dBm, +25 °C 1.2 1.3 dB

Insertion loss2 (attenuated state) ANT–RX Active RX port

100–1000 MHz

15.2

16

16.8

dB

Isolation (supply biased) TX–TX 100–520 MHz

520–1000 MHz 33

29 36

30 dB

dB

Isolation (supply biased) TX–RX 100–520 MHz

520–1000 MHz 34

29 36

30 dB

dB

Unbiased isolation

VDD, V1, V2, V3 = 0V ANT–TX +27 dBm 6 dB

Unbiased isolation

VDD, V1, V2, V3 = 0V ANT–RX +27 dBm 14 dB

Return loss2 ANT–RX

Un-attenuated state

100–520 MHz

520–1000 MHz

22

18

27

22

dB

Un-attenuated state, 1575 MHz for GPS RX, < –10 dBm, +25 °C 10 14 dB

Attenuated state, optimized without attenuator engaged

100–520 MHz

520–1000 MHz

16

13

21

18

dB

Return loss2 ANT–TX

100–520 MHz

520–1000 MHz 21

15 28

17 dB

dB

2nd and 3rd harmonic

(< 1.15:1 VSWR) TX 100–520 MHz @ +40.0 dBm

521–870 MHz @ +38.5 dBm

871–1000 MHz @ +37.5 dBm –80 –78 dBc

2nd and 3rd harmonic

(< 8:1 VSWR) TX 100–520 MHz @ +40.0 dBm (pulsed signal, at 10% duty cycle3)

521–870 MHz @ +38.5 dBm (pulsed signal, at 10% duty cycle3)

871–1000 MHz @ +37.5 dBm (pulsed signal, at 10% duty cycle3) –76 –70 dBc

IIP3 RX

Un-attenuated state

Attenuated state 42

38

dBm

Settling time From 50% control until harmonics within specifications 15 µs

2nd and 3rd harmonic

(50Ω source/load impedance) TX 100–1000 MHz @ +42.5 dBm (CW) –78 –74 dBc

2nd and 3rd harmonic

(50Ω source/load impedance) TX 100–1000 MHz @ +45.0 dBm (pulsed signal, at 10% duty cycle3) –76 –70 dBc

Switching time in bypass mode4

(VSS_EXT = –3.4V) 50% CTRL to 90% or 10% of RF 4 µs

Input 0.1dB compression point5 ANT–TX 1000 MHz 45.5 dBm

Switching time in normal mode4

(VSS_EXT = 0V) 50% CTRL to 90% or 10% of RF 6 µs

Notes: 1. In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and TX4 are tied respectively. Refer to Application Note AN35 for SP3T performance data.

2. Narrow trace widths are used near each port to improve impedance matching. Refer to evaluation board layouts (Figure 23) and schematic (Figure 24) for details.

3. 10% of 4620 µs period.

4. Normal mode: connect VSS_EXT (pin 16) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. Bypass mode: use VSS_EXT (pin 16) to bypass and

disable internal negative voltage generator.

5. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PIN.

Product Specification

PE42851

Page 3 of 12

Table 2. Pin Descriptions

Figure 4. Pin Configuration (Top View)*

Pin # Pin Name Description

1, 3, 5–7, 9–

11, 17–20,

22, 24–27,

29–32

GND Ground

2 TX12 Transmit pin 1

4 TX21,2 Transmit pin 2

8 RX2 Receive pin

12 VDD Supply voltage (nominal 3.3V)

13 V3 Digital control logic input 3

14 V2 Digital control logic input 2

15 V1 Digital control logic input 1

16 VSS_EXT3 External VSS negative voltage control

21 TX32 Transmit pin 3

23 TX41,2 Transmit pin 4

28 ANT2 Antenna pin

Pad GND Exposed pad: ground for proper operation

Notes: 1. To operate the part as a 2TX–1RX SP3T, tie TX1 to TX2 and TX3

to TX4 respectively. Refer to Application Note AN35 for SP3T

performance data.

2. RF pin s 2, 4, 8, 21, 23 and 28 must be at 0 VDC. The RF pins do

not require DC blocking capacitors for proper operation if the 0 VDC

requirement is met.

3. Use VSS_EXT (pin 16) to bypass and disable internal negative

voltage generator. Connect VSS_EXT (pin 16) to GND (VSS_EXT = 0V) to

enable internal negative voltage generator.

Table 3. Operating Ranges1

Parameter Symbol Min Typ Max Unit

Supply voltage (normal

mode, VSS_EXT = 0V) VDD 2.3 5.5 V

Supply voltage (bypass

mode, VSS_EXT = –3.4V,

VDD ≥ 3.4V for full spec.

compliance)

VDD 2.7 3.4 5.5 V

Negative supply voltage

(bypass mode) VSS_EXT –3.6 –3.2 V

Supply current (normal

mode, VSS_EXT = 0V) IDD 130 200 µA

Supply current (bypass

mode, VSS_EXT = –3.4V) IDD 50 80 µA

Negative supply current

(bypass mode, VSS_EXT =

–3.4V) ISS –40 –16 µA

Digital input high

(V1, V2, V3) VIH 1.17 3.6 V

Digital input low

(V1, V2, V3) VIL –0.3 0.6 V

TX RF input power2,3

(VSWR ≤ 8:1) PIN–TX 40 dBm

TX RF input power2,3

(50Ω source/load

impedance) PIN–TX 45 dBm

TX RF input power2

(50Ω source/load

impedance, CW) PIN–TX 42.5 dBm

ANT RF input power,

unbiased (VSWR ≤ 8:1) PIN–ANT 27 dBm

RX RF input power2

(VSWR ≤ 8:1) PIN–RX 27 dBm

Operating temperature

range (case) TOP –40 85 °C

Operating junction

temperature Tj 135 °C

Notes: 1. In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3

and TX4 are tied respectively. Refer to Application Note AN35 for

SP3T performance data.

2. Supply biased.

3. Pulsed, 10% duty cycle of 4620 µs period.

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

GND

VDD

V3

V2

V1

VSS_EXT

GND

ANT

GND

Note: * Pins 1, 3, 5, 7, 9, 10, 17, 19, 20, 22, 24, 26, 27, 29, 30 and 31 can be

N/C if deemed necessary by the customer

Product Specification

PE42851

Page 4 of 12

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS

devices are immune to latch-up.

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the

5x5 mm QFN package is MSL3.

Table 5. Truth Table

Path V3 V2 V1

ANT – RX Attenuated L L L

ANT – TX1 L L H

ANT – TX2 L H L

ANT – TX1 and TX2* L H H

ANT – RX H L L

ANT – TX3 H L H

ANT – TX4 H H L

ANT – TX3 and TX4* H H H

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be

restricted to the limits in the Operating Ranges

table. Operation between operating range

maximum and absolute maximum for extended

periods may reduce reliability.

Table 4. Absolute Maximum Ratings

Parameter/Condition Symbol Min Max Unit

Supply voltage VDD –0.3 5.5 V

Digital input voltage

(V1, V2, V3) VCTRL –0.3 3.6 V

TX RF input power1(50Ω

source/load impedance) PIN–TX 45 dBm

TX RF input power1

(VSWR ≤ 8:1) PIN–TX 40 dBm

ANT RF input power, unbiased

(VSWR ≤ 8:1) PIN–ANT 27 dBm

RX RF input power1

(VSWR ≤ 8:1) PIN–RX 27 dBm

Storage temperature range TST –65 150 °C

Maximum case temperature TCASE 85 °C

Peak maximum junction

temperature

(10 seconds max) Tj 200 °C

ESD voltage HBM2, all pins VESD,HBM 1500 V

ESD voltage MM3, all pins VESD,MM 200 V

ESD voltage CDM4, all pins VESD,CDM 1000 V

Notes: 1. Supply biased

2. Human Body Model (MIL-STD 883 Method 3015)

3. Machine Model (JEDEC JESD22-A115)

4. Charged Device Model (JEDEC JESD22-C101)

Switching Frequency

The PE42851 has a maximum 10 kHz switching

rate when the internal negative voltage generator

is used (pin 16 = GND). The rate at which the

PE42851 can be switched is only limited to the

switching time (Table 1) if an external negative

supply is provided (pin 16 = VSS_EXT).

Switching frequency describes the time duration

between switching events. Switching time is the

time duration between the point the control signal

reaches 50% of the final value and the point the

output signal reaches within 10% or 90% of its

target value.

Spurious Performance

The typical spurious performance of the PE42851

is –130 dBm when VSS_EXT = 0V (pin 16 = GND). If

further improvement is desired, the internal

negative voltage generator can be disabled by

setting VSS_EXT = –3.4V.

Optional External VSS Control (VSS_EXT)

For proper operation, the VSS_EXT control pin must

be grounded or tied to the Vss voltage specified in

Table 3. When the VSS_EXT control pin is grounded,

FETs in the switch are biased with an internal

voltage generator. For applications that require the

lowest possible spur performance, VSS_EXT can be

applied externally to bypass the internal negative

voltage generator.

Note: * In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and

TX4 are tied respectively. Refer to Application Note AN35 for SP3T

performance data.

Product Specification

PE42851

Page 5 of 12

Typical Performance Data @ +25 °C and VDD = 3.4V, unless otherwise specified

Figure 5. Insertion Loss vs. Temp (TX) Figure 6. Insertion Loss vs. VDD (TX)

Figure 8. Insertion Loss vs. VDD

(RX, Un-Attenuated)

Figure 7. Insertion Loss vs. Temp

(RX, Un-Attenuated)

Figure 9. Insertion Loss vs. Temp

(RX, Attenuated) Figure 10. Insertion Loss vs. VDD

(RX, Attenuated)

Product Specification

PE42851

Page 6 of 12

Typical Performance Data @ +25 °C and VDD = 3.4V, unless otherwise specified

Figure 11. Return Loss vs. Temp (ANT) Figure 12. Return Loss vs. VDD (ANT)

Figure 13. Return Loss vs. Temp (TX) Figure 14. Return Loss vs. VDD (TX)

Figure 15. Return Loss vs. Temp

(RX, Attenuated) Figure 16. Return Loss vs. VDD

(RX, Attenuated)

Product Specification

PE42851

Page 7 of 12

Typical Performance Data @ +25 °C and VDD = 3.4V, unless otherwise specified

Figure 19. Isolation vs. Temp (TX–TX) Figure 20. Isolation vs. VDD (TX–TX)

Figure 21. Isolation vs. Temp (TX–RX) Figure 22. Isolation vs. VDD (TX–RX)

Figure 17. Return Loss vs. Temp

(RX, Un-Attenuated) Figure 18. Return Loss vs. VDD

(RX, Un-Attenuated)

Product Specification

PE42851

Page 8 of 12

Thermal Data

Though the insertion loss for this part is very low,

when handling high power RF signals, the junction

temperature rises significantly.

VSWR conditions that present short circuit loads to

the part can cause significantly more power

dissipation than with proper matching.

Special consideration needs to be made in the

design of the PCB to properly dissipate the heat

away from the part and maintain the +85 °C

maximum case temperature. It is recommended to

use best design practices for high power QFN

packages: multi-layer PCBs with thermal vias in a

thermal pad soldered to the slug of the package.

Special care also needs to be made to alleviate

solder voiding under the part.

Table 6. Theta JC

Parameter Min Typ Max Unit

Theta JC (+85 °C) 20 C/W

Product Specification

PE42851

Page 9 of 12

Evaluation Kit

The PE42851 Evaluation Kit board was designed

to ease customer evaluation of the PE42851 RF

switch.

The evaluation board in Figure 23 was designed

to test the part in the 5T configuration. DC power

is supplied through J10, with VDD on pin 9, and

GND on the entire lower row of even numbered

pins. To evaluate a switch path, add or remove

jumpers on V1 (pin 3), V2 (pin 5), and V3

(pin 7) using Table 5 (adding a jumper pulls the

CMOS control pin low and removing it allows the

on-board pull-up resistor to set the CMOS control

pin high). Pins 11 and 13 of J10 are N/C.

The ANT port is connected through a 50Ω

transmission line via the top SMA connector, J1.

RX and TX paths are also connected through 50Ω

transmission lines via SMA connectors. A

50Ω through transmission line is available via

SMA connectors J8 and J9. This transmission line

can be used to estimate the loss of the PCB over

the environmental conditions being evaluated. An

open-ended 50Ω transmission line is also provided

at J7 for calibration if needed.

Narrow trace widths are used near each part to

improve impedance matching.

Figure 23. Evaluation Board Layouts

PRT-50283

Product Specification

PE42851

Page 10 of 12

Figure 24. Evaluation Board Schematic

DOC-13027

Notes: 1. Use 101-0316-02 PCB

2. 32 mil Width, 10 mil Gaps, 28 mil Core, 4.3 Er, and 2.1 mil Cu

Product Specification

PE42851

Page 11 of 12

TO P VIEW BOT TOM VIEW

SIDE VIEW

RECOMMENDED LAND PATTERN

A0.10 C

(2X)

C

0.10 C

0.05 C

SEATI NG PLAN E

B

0.10 C

(2X)

0.10 C A B

0.05 C

ALL FEATURES

Pin #1 Corner

5.00

5.00 3.30±0.05

3.30±0.053.50

3.50

0.50

0.24±0.05

(X32)

0.375±0.05

(X32)

0.203

Ref. 0.05

0.85±0.05

0.575

(x32)

0.290

(x32)

3.35

5.20

3.35

5.20

0.50

(X28)

DETAIL A

1

8

9

16

17 24

25

32

0.18

0.15

0.10

DETAIL A

DOC-01872

Figure 25. Package Drawing

32-lead 5x5 mm QFN

Figure 26. Top Marking Specification

42851

YYWW

ZZZZZZ

17-0085

= Pin 1 designator

YYWW = Date code, last two digits of the year and work week

ZZZZZZ = Six digits of the lot number

Product Specification

PE42851

Page 12 of 12

Table 7. Ordering Information

Figure 27. Tape and Reel Drawing

Order Code Description Package Shipping Method

PE42851MLBA-X PE42851 SP5T RF switch Green 32-lead 5 × 5 mm QFN 500 units / T&R

EK42851-03 PE42851 Evaluation kit Evaluation kit 1 / Box

Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.02.

2. Camber not to exceed 1 mm in 100 mm.

3. Material: PS + C.

4. Ao and Bo measured as indicated.

5. Ko measured from a plane on the inside bottom of the

pocket to the top surf ace of the ca rrier.

6. Pocket position relative to sprocket hole measured as

true position of pocket, not pocket hole.

Ao = 5.25 mm

Bo = 5.25 mm

Ko = 1.1 mm

Device Orientation in Tape

Top of

Device

Pin 1

Tape Feed Direction

Advance Information:

The product is in a formative or design stage. The datasheet contains design target

specifications for product development. Specifications and features may change in any manner without notice.

Preliminary Specification:

The datasheet contains preliminary data. Additional data may be added at a later

date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best

possible product.

Product Specification:

The datasheet contains final data. In the event Peregrine decides to

change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer

Notification Form).

The informatio n in this datasheet i s believed to b e reliable. Ho wever, Peregrin e assume s no liability for the us e

of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.

No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,

or in other applications intended to support or sustain life, or in any application in which the failure of the

Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no

liability for damages, including consequential or incidental damages, arising out of the use of its products in

such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE

are trademarks of Peregrine Semiconductor Corp.

Peregrine products are protected under one or more of

the following U.S. Patents: http://patents.psemi.com.

Sales Contact and Information

For sales and contact information please visit www.psemi.com.