THC7984_Rev.2.0_E THC7984 10-bit 3-channel Video Signal Digitizer General Description Features The THC7984 integrates all the functions to digitize analog video signals on a single chip. 170 MSPS 10-bit ADC - Internal 14-bit ADCs - Oversampling functions (2x, 4x, and 8x) Line-locked PLL with low jitter - Phase adjustment: 64 steps Fine clamp / preamp - Pedestal / center clamp - Clamp level auto adjust - Very low gain mismatch - Gain adjustment: 2048 steps Video Filter (LPF) - Bandwidth adjustment: 28 steps (6MHz - 310MHz) Sync Processor - 2-level / 3-level sync slicer - Advanced sync detection / measurement - Automatic sync processing mode - IRQ Output 2-wire serial interface LQFP 80-pin package Acceptable Signals PC Graphics (RGB) : VGA-UXGA - Separate Sync - Composite Sync - Sync on Green Component Video (YPbPr) : - SDTV (480i / 480p) 2-level Sync - HDTV (1080i / 720p / 1080p) 3-level Sync - Protection Signal Applications LCD TV / PDP TV Rear-Projection TV LCD Display / PDP Display Front Projector etc. Block Diagram Auto Clamp Level Adjust RAIN0 RAIN1 2:1 Switch Decimation 10-bit Filter Clamp PGA LPF ADC RED0-9 & Output Auto Clamp Level Adjust GAIN0 GAIN1 2:1 Switch Formatter 10-bit Clamp PGA LPF ADC LPF ADC GREEN0-9 Auto Clamp Level Adjust BAIN0 BAIN1 SOGIN0 SOGIN1 2:1 Switch 10-bit Clamp PGA BLUE0-9 DATACK SOG Slicer HSYNC0 HSYNC1 VSYNC0 SOGOUT SYNC Processing & Clock Generation O/E FIELD HSOUT VSOUT/A0 VSYNC1 REFHI EXTCLK/COAST CLAMP 1 / 45 SCL RST Copyright(c)2013 THine Electronics, Inc. REFCM REFLO SDA Serial I/F Control FILT Voltage Reference THine Electronics, Inc. THC7984_Rev.2.0_E Specifications V D = 1 .8 V , V D D = 3 .3 V , P V D = 1 .8 V , D A V D D = 1 .8 V , A D C C lo c k = M a x im u m C o n v e rs io n R a te , F u ll T e m p e ra tu re R a n g e = 0 C to 7 0 C A n a lo g In p u t V o lta ge = 0 .5 to 1 .0 V p p T e st THC 7984-17 U n it P a ra m e te r Tem p Level M in Typ M ax N u m b e r o f B its 10 B its R E S O L U T IO N L S B S iz e 0 .0 9 8 %FS DC ACCURACY D iffe re n tia l N o n lin e a rity 25 C I 0 .7 5 1 LSB F u ll VI - 1 .0 / + 1 .2 5 LSB In te gra l N o n lin e a rity 25 C I 1 .5 3 LSB F u ll VI 4 LSB N o M is s in g C o d e 25 C I G u a ra n te e d A N A L O G IN P U T M in im u m In p u t V o lta ge F u ll VI 0 .5 V p-p M a xim u m In p u t V o lta g e F u ll VI 1 .0 V p-p G a in T e m p c o 25 C V 100 ppm / C 25 C IV 1 A In p u t B ia s C u rre n t * 1 F u ll IV 1 A In p u t O ffs e t V o lta ge F u ll VI 1 LSB In p u t F u ll- S c a le M a tc h in g F u ll VI 0 .2 0 .8 % B e tw e e n C h a n n e ls O ffse t A d ju stm e n t R a n ge F u ll VI 50 %FS M a x im u m C o n v e rs io n R a te F u ll VI 170 MSPS S W IT C H IN G M in im u m C o n v e rs io n R a te F u ll IV 10 MSPS PERFORM ANCE F u ll IV 0 .4 8 T p ix e l- 2 .1 ns D a ta S e tu p T im e to C lo c k * 2 F u ll IV 0 .4 8 T p ix e l- 0 .4 ns D a ta H o ld T im e to C lo c k * 2 F u ll IV 40 50 60 % D u ty C y c le , D A T A C K * 2 H S Y N C In p u t F re q u e n c y F u ll IV 15 110 kH z M a x im u m P L L C lo c k R a te F u ll VI 170 MHz M in im u m P L L C lo c k R a te F u ll IV 10 MHz 25 C V 500 ps p-p P L L J itte r * 3 S a m p lin g P h a s e T e m p c o F u ll IV 15 p s/ C 2 - W IR E S E R IA L S C L C lo c k F re q u e n c y ( fS C L ) F u ll IV 100 kH z IN T E R F A C E tB U F F F u ll IV 4 .7 s tS T A H F u ll IV 4 .0 s tD H O F u ll IV 0 3 .4 5 s tD A L F u ll IV 4 .7 s tD A H F u ll IV 4 .0 s tD S U F u ll IV 250 ns tS T A S U F u ll IV 4 .7 s tS T O S U F u ll IV 4 .0 s Tr F u ll IV 1000 ns Tf F u ll IV 150 ns C a p a c itiv e L o a d ( C b ) F u ll IV 400 pF N o ise m a rg in a t th e L O W le v e l ( V n L ) F u ll IV 0 .2 V N o is e m a rg in a t th e H IG H le v e l ( V n H ) F u ll IV 0 .2 5 V D IG IT A L IN P U T S In p u t V o lta g e , H ig h (V IH ) F u ll VI 1 .4 V In p u t V o lta g e , L o w (V IL ) F u ll VI 0 .8 V In p u t C u rre n t, H ig h (IIH ) F u ll V 10 A In p u t C u rre n t, L o w (IIL ) F u ll V 10 A In p u t C a p a c ita n c e 25 C V 2 pF O u tp u t V o lta ge , H igh (V O H ) F u ll VI V D D - 0 .2 V D IG IT A L O U T P U T S O u tp u t V o lta g e , L o w (V O L ) F u ll VI 0 .2 V O u tp u t C o d in g B in a ry V D S u p p ly V o lta g e F u ll IV 1 .7 1 .8 1 .9 V POW ER SUPPLY V D D S u p p ly V o lta ge F u ll IV 2 .3 3 .3 3 .4 5 V P V D S u p p ly V o lta g e F u ll IV 1 .7 1 .8 1 .9 V D A V D D S u p p ly V o lta ge F u ll IV 1 .7 1 .8 1 .9 V ID S u p p ly C u rre n t (V D ) 25 C V 295 mA 25 C V 180 mA ID D S u p p ly C u rre n t (V D D ) * 4 IP V D S u p p ly C u rre n t (P V D ) 25 C V 30 mA ID A V D D S u p p ly C u rre n t (D A V D D ) 25 C V 65 mA T o ta l P o w e r D iss ip a tio n F u ll VI 1350 mW P o w e r- D o w n S u p p ly C u rre n t F u ll VI 10 20 mA P o w e r- D o w n D is sip a tio n F u ll VI 20 40 mW THERMAL O p e ra tin g A m b ie n t T e m p e ra tu re IV 0 70 C C H A R A C T E R IS T IC S J C J u n c tio n - to - C a se 25 C V 4 C /W T h e rm a l R e sista n c e J A J u n c tio n - to - A m b ie n t 25 C V 37 C /W T h e rm a l R e s is ta n c e * 1 In p u t B ia s V o lta ge : 0 .0 5 V to V D - 0 .0 5 V * 2 S e e " D a ta / C lo c k O u tp u t T e s t C o n d itio n " . *3 THC 7984-17: UXG A@ 60Hz * 4 O u tp u t L o a d C a p a c ita n c e p e r P in : 1 5 p F EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at +25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25C; guaranteed by design and characterization testing. Copyright(c)2013 THine Electronics, Inc. 2 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E < Data Setup/Hold Time to Clock > < Data /Clock Output Test Condition > Tpixel THC7984 DATACK 33ohm Probe 10pF 50 DATACK: Pixel Clock DATACK Phase: 4 Output Format: Normal (not DDR) Output Drive Strength (VDD=3.3V) : Medium VDD 80 DATA 20 GND Data Setup Time *DATACK output phase is register programmable. Data Hold Time Absolute Maximum Ratings Parameter VD VDD PVD DAVDD Analog Inputs Digital Inputs Storage Temperature Maximum Junction Temperature *1 Smaller Value is adopted. Min Max 2.1 3.8 2.1 2.1 VD+0.2 or 2.1 *1 PVD+3.6 or 5.5V *1 150 125 -0.2 -0.3 -55 Unit V V V V V V C C VDD BLUE<0> BLUE<1> BLUE<2> 64 63 62 61 SDA GND 67 65 SCL 68 66 VSYNC1 HSYNC1 69 VSYNC0 HSYNC0 70 73 71 PVD CLAMP 74 72 EXTCLK/COAST PVD GND 75 GND 77 76 PVD FILT 78 GND 79 80 Pin Configuration VD 1 60 BAIN0 2 59 BLUE<4> GND 3 58 BLUE<5> BAIN1 4 57 BLUE<6> VD GAIN0 5 56 BLUE<7> 6 55 BLUE<8> GND BLUE<3> 7 54 BLUE<9> SOGIN0 8 53 GND 9 52 VDD 51 GREEN<0> 50 GREEN<1> VD THC7984 GAIN1 10 GND Top View 11 SOGIN1 12 49 GREEN<2> 13 VD RAIN0 14 48 GREEN<3> GND 47 GREEN<4> 46 GREEN<5> 15 RAIN1 16 RST 45 GREEN<6> 44 GREEN<7> 17 REFLO 18 REFCM 19 42 GREEN<9> 20 39 40 34 RED<3> GND 33 RED<4> GND 32 RED<5> 37 31 RED<6> 38 30 VDD 29 RED<8> RED<7> RED<0> 28 3 / 45 RED<2> 35 RED<1> 36 27 VDD GND 26 DATACK Copyright(c)2013 THine Electronics, Inc. RED<9> 24 25 SOGOUT HSOUT 23 O/E FIELD 21 41 VSOUT/A0 22 REFHI 43 GREEN<8> DAVDD THine Electronics, Inc. THC7984_Rev.2.0_E Pin List Pin Name VD VDD PVD DAVDD GND BAIN0 BAIN1 GAIN0 SOGIN0 GAIN1 SOGIN1 RAIN0 RAIN1 RST Type P P P P P AI AI AI AI AI AI AI AI DI REFLO REFCM REFHI O/E FIELD DO VSOUT/A0 HSOUT SOGOUT DATACK RED<9:0> GREEN<9:0> BLUE<9:0> SCL SDA HSYNC1 VSYNC1 HSYNC0 VSYNC0 EXTCLK/COAST CLAMP DIO DO DO DO DO DO DO DI DIO DI DI DI DI DI DI FILT P:Power AI:Analog Input Function Analog Power Supply Output Power Supply PLL Power Supply Digital Core Power Supply Ground B-ch Analog Input, Port 0 B-ch Analog Input, Port 1 G-ch Analog Input, Port 0 Sync on Green Input, Port 0 G-ch Analog Input, Port 1 Sync on Green Input, Port 1 R-ch Analog Input, Port 0 R-ch Analog Input, Port 1 Reset Input Low: Normal Operation High: Power Down (Stand-by) High -> Low: Chip Reset Connection for External Capacitor Connection for External Capacitor Connection for External Capacitor Field Parity Output for Interlaced Video <Other Function> Data Enable (DE) Output Sync Processor IRQ Output VSYNC Output / Serial Interface Device Address bit 0 (A0) HSYNC Output SOG Slicer Output Data Clock Output R-ch Data Output G-ch Data Output B-ch Data Output Serial Port Data Clock Input Serial Port Data I/O HSYNC Input, Port 1 VSYNC Input, Port 1 HSYNC Input, Port 0 VSYNC Input, Port 0 External Clock Input / Coast Signal Input External Clamp Pulse Input <Other Function> Reference Clock Input for HSYNC Period Measure Connection for PLL Loop Filter DI:Digital Input DO:Digital Output DIO:Digital Input/Output Copyright(c)2013 THine Electronics, Inc. 4 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Functional Description Digital Input - All digital inputs are 5V tolerant during power-on. Analog Input - The THC7984 has two ports that each include three analog inputs for RGB or YPbPr. The input port can be selected by register. - In case input signals are YPbPr, Y may be input into GAIN0 (or GAIN1) and SOGIN0 (or SOGIN1) , Pr into RAIN0 (or RAIN1) , and Pb into BAIN0 (or BAIN1) . - The THC7984 accommodates analog signals ranging from 0.5 Vpp to 1.0 Vpp. Video Filter (LPF) The THC7984 has 2 kinds of low-pass filters. - 5th-order LPF for YPbPr, whose bandwidth is adjustable from 6 MHz to 92 MHz in 24 steps. - 2nd-order LPF for RGB, whose bandwidth is adjustable in 4 steps (40 MHz, 90 MHz, 170 MHz, and 310 MHz) . Serial Interface - The THC7984 is controlled by 2-wire serial interface. - Serial clock SCL supports up to 100 kHz. Sync Input - The THC7984 has two ports that each include two digital inputs for the separate sync (HSYNC and VSYNC) . The input port can be selected by register. - The THC7984 can process composite sync (CSYNC) . CSYNC may be input into HSYNC0 or HSYNC1. Digital Output - The digital outputs can operate from 2.5 V to 3.3 V (VDD) . - The output drive strength is programmable by 2-bit registers (except SDA) . Clamp - Pedestal clamp for RGB and Y (luminance) clamps black level to 0 with automatic offset cancel. - Midscale clamp for PbPr clamps to 512 with automatic offset cancel. - 256-level clamp for Y (luminance) clamps to 256 with automatic offset cancel. It can be used for A/D conversion of Y including sync signal. In this case, input signal needs to be attenuated to put it within the input rang of A/D converter. - Clamp pulses can be input from CLAMP pin when external clamp is selected. Gain, Offset - Gain is programmable by 11-bit registers (2048 steps) . - Offset from -256 to +255 can be added to the output code. - Gain and offset can be adjusted independently. Reference Voltage - The THC7984 has Band Gap Reference inside and doesn't require external voltage reference. - The internal reference voltages (REFHI, REFCM, and REFLO) must be bypassed to stabilize. Each pin (REFHI, REFCM, and REFLO) is connected to ground through a 10 F capacitor. Copyright(c)2013 THine Electronics, Inc. 5 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Sampling Clock Generation - The THC7984 has PLL to generate the sampling clock from HSYNC. The sampling clock frequency range is from 10MHz to 170 MHz. - PLL divider ratio (the number of horizontal total pixels per line) can be set to the value between 200 to 8191. - The sampling clock Phase can be adjusted in 64 steps of T/64. - The external clock can be used as the sampling clock. - It is required to set VCO Frequency Range and Charge Pump Current according to the input signal format (resolution) . Oversampling - Oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and downsampling to the pixel clock rate with decimation filter, which is effective for improving S/N ratio. - Oversampling ratio can be selected among 1x (normal operation) , 2x, 4x, and 8x. Even if any is selected, output frequency of the output clock and data is same as normal operation. Output Clock (DATACK) - The output clock phase can be selected in 8 steps for the data setup/hold adjustment. - Divide-by-2 clock can be selected as the output clock for the dual edge data clocking at the subsequent stage. It can not be selected when oversampling. SOG Slicer - Sync on Green (SOG) is sliced at the threshold level above the sync tip to extract the sync signal. The threshold level can be set by a register ranging from 15 mV to 240 mV in steps of 15mV. - Low pass filer prior to the slicer can be used to reduce high frequency noise, which can be disabled by a register. - The slicer also has hysteresis (about 30mV) , which can be disabled by a register. - 3-level sync signal can be processed by slicing at the pedestal level. Sync Processor Sync Processor implements VSYNC separation from CSYNC, vertical timing generation, and detection and measurement of the sync signals. The various automatic sync-processing modes are realized by utilizing the sync detection and measurement. The THC7984 can process the copy protection signal. (1) VSYNC Separation Extracting VSYNC from Composite sync (CSYNC) or Sync on Green (SOG) . (2) Vertical Timing Generation - VSYNC Output Generation - PLL COAST Generation - Clamp COAST Generation - V-Blank of DE Generation (3) Sync Detection/Measurement - Input Sync Type Detection (Separate sync, Composite sync, Sync on Green, and No input signal) - HSYNC, VSYNC Input Polarity Detection - 3-level Sync Detection - Interlace Detection - Vertical Total Line Measurement - VSYNC Input Pulse Width Measurement - HSYNC Period Measurement (Reference clock needs to be input into CLAMP pin.) - SYNC Change Detection - HSYNC Edge Detection - Sync Processor IRQ Output Copyright(c)2013 THine Electronics, Inc. 6 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E (4) Automatic Sync Processing Mode (Manual Setting Modes are also available) - Auto Output Mode (All outputs are enabled when input signal is active) - Input Port Auto Select (Selects the port whose input signal is active) - Input Sync Type Auto Select (HSYNC Input, VSYNC Input) - HSYNC, VSYNC Input Polarity Auto Select - HSYNC, VSYNC Output Polarity Auto Select - VSYNC Output Timing Auto Setting - PLL COAST Timing Auto Setting Power Control - The THC7984 can be set to stand-by mode by a register or RST-pin. - In stand-by mode, most of the analog circuits are powered down for low power dissipation. - In stand-by mode, the sync detection and measurement are available nonetheless because SOG Slicer, Sync Processor, and 2-wire serial interface are still power-on. - The THC7984 is set to stand-by mode when RST-pin is set to High. If unused, RST-pin must be pull-down to ground with a resistor. Reset - The logic circuit of the chip is reset when power is applied with RST-pin asserted Low (Power-on Reset) . - The reset can be also triggered by RST-pin (Manual Reset) . The reset is triggered when RST-pin falls from High to Low, that means the reset is triggered whenever the THC7984 gets out of stand-by mode by RST-pin. - Reset after power-up is necessary to access the serial interface. Please power-up with RST-pin asserted Low or make RST-pin High then Low after power-up. If unused, RST-pin must be pull-down to ground with a resistor. - The registers are set to the default values by the reset and the chip becomes stand-by mode and output disable (Hi-Z) . For normal operation, the registers must be set to power-on and output enable by the serial interface. - For Manual Reset, keep RST-pin Low more than 20 us after the transition from High to Low. Min. 100ns RST (Reset Signal) VIH * Reset Timing VIL Min. 20us Device Address - The LSB of 7-bit device address of serial interface (A0) is obtained from VSOUT/A0-pin at the reset. Pull-down to ground with a resistor (10 k) , then Device Address is set to 1001100 Pull-up to VDD with a resistor (10 k) , then Device Address is set to 1001101 - The pull-up resistor must be connected to VDD. Copyright(c)2013 THine Electronics, Inc. 7 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Registers Register Notation The register is notated with "R" added to the head of the address in hexadecimal. e.g. R00: Register of address 0x00 The bit position is notated with "[]". e.g. R04[1:0]: Bit 1 and bit 0 of address 0x04 The register value in hexadecimal is notated with "h" added to the end. e.g. R01=18h The register value in binary is notated with "b" added to the end. e.g. R04[1:0]=11b The register value in decimal is notated without suffix. e.g. R15[7:0]=32 Register Classification < Register Classification> Sign R/W R Category Read/Write Read Only A Auto EVRC Event Recorder Description Registers for configuration and adjustment Registers which report the result of measurement and detection Registers which can be auto-configured - When auto-configuration is enabled, the registers become Read Only and the value auto-configured can be read. - When auto-configuration is disabled, the registers become Read/Write and the value must be set manually. Registers which record the event that has occurred in Sync Processor. - 1 is set when the event occurs. - The value is cleared by writing 1 to the register. Register except below R00, R2CR30, R32R34 R12[3], R12[1:0], R13[5], R13[4], R13[2], R13[1], R20[6:0], R21[5:0], R22[6:0], R23[6:0] R35 Default Value All registers are set to the default values by the reset (Power-on Reset, Manual Reset) . Minus Number Setting Some registers can be configured by two's complement. < Minus Number Setting > Function Clamp Level Offset HSYNC Output Start Position VSYNC Output Start Position Copyright(c)2013 THine Electronics, Inc. Register R0C/R0D, R0E/R0F, R10/R11 R14 R20 8 / 45 Range -256 to +255 -128 to +127 -64 to +63 THine Electronics, Inc. THC7984_Rev.2.0_E Register Map Address Bit R/W Default Value R 00 7 R 0 6 R 0 5 R 1 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1 R 01 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 R 02 7 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 1 1 R/W 1 0 R/W 0 R 03 7 R/W 1 6 R/W 0 5 R/W 0 4 R/W 1 3 R/W 1 2 R/W 0 1 R/W 0 0 R/W 0 R 04 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 R 05 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 R 06 7 6 5 4 3 2 R/W 1 1 R/W 0 0 R/W 0 R 07 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Function Description Revision Code Can be read 21h Chip Power-On Auto Output Enable (All outputs become Enable when input signal is active) Output Enable (Except SOGOUT & IRQ) SOGOUT Output Enable Reserved 0: Power-Down (Stand-by Mode) 1: Power-On (Normal Operation) 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable Must be set to 0 (Default Value) Oversampling 00b: 1x(Normal Operation) 01b: 2x 10b: 4x 11b: 8x PLL Divider Ratio Set the number of horizontal total pixels per line Reserved VCO Frequency Range Must be set to 1 (Default Value) 00b: 1/8 01b: 1/4 10b: 1/2 11b: 1/1 Charge Pump Current 000b: 50uA 001b: 100uA 010b: 150uA 011b: 250uA 100b: 350uA 101b: 500uA 110b: 750uA 111b: 1000uA Sampling Clock Source 00b: Internal Clock 01b: Reserved 10b: External Clock (10-20MHz) 11b: External Clock (20-170MHz) Sampling Clock Phase Set in 64 steps of T/64 *Bigger values mean more delay. R-ch Gain Gain = (Register Value + 1024) / 2048 2048 steps from x0.5 to x1.5 *Bigger values mean higher gain. Copyright(c)2013 THine Electronics, Inc. 9 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 08 R 09 R 0A R 0B R 0C R 0D R 0E R 0F 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0 0 0 0 0 G-ch Gain Gain = (Register Value + 1024) / 2048 2048 steps from x0.5 to x1.5 *Bigger values mean higher gain. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0 0 0 0 0 B-ch Gain Gain = (Register Value + 1024) / 2048 2048 steps from x0.5 to x1.5 *Bigger values mean higher gain. R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 R-ch Clamp Level Offset 1 LSB of offset corresponds to 1 LSB of output code. -256 to +255 *Set in two's complement. R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 G-ch Clamp Level Offset 1 LSB of offset corresponds to 1 LSB of output code. -256 to +255 *Set in two's complement. Copyright(c)2013 THine Electronics, Inc. 10 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 10 R 11 R 12 R 13 R 14 R 15 R 16 R 17 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A R/W A A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 B-ch Clamp Level Offset 1 LSB of offset corresponds to 1 LSB of output code. -256 to +255 *Set in two's complement. Reserved Reserved Input Port Automatic Selection Enable Reserved Input Port Sync Type Automatic Select Enable Sync Type Select Must be set to 0 Must be set to 0 0: Disable 1: Enable Must be set to 0 0: Port-0 1: Port-1 0: Disable 1: Enable 00b: Separate Sync 01b: Composite Sync 10b: Sync on Video (2-lelvel) 11b: Sync on Video (3-lelvel) R/W A A R/W A A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 HSYNC Input, VSYNC Input Polarity Automatic Selection Enable HSYNC Input Polarity VSYNC Input Polarity HSYNC Output, VSYNC Output Polarity Automatic Selection Enable HSYNC Output (HSOUT) Polarity VSYNC Output (VSOUT) Polarity VSYNC Output (VSOUT) Interlace Mode HSYNC Output (HO) Start Position 0: Disable 1: Enable 0: Active-Low 1: Active-High 0: Active-Low 1: Active-High 0: Disable 1: Enable (Output Polarity is conformed to Input Polarity) 0: Active-Low 1: Active-High 0: Active-Low 1: Active-High 0: Disable 1: Enable Set in 1 pixel steps with reference to the leading edge of HSYNC input -128 to +127 *Set in two's complement. HSYNC Output (HO) Pulse Width Set in 1 pixel steps 1 to 255 R/W R/W R/W R/W R/W 0 1 0 1 0 PLL COAST Source PLL/Clamp COAST Input Polarity (If COAST Source is External) Clamp Pulse Source Clamp Pulse Input Polarity (If COAST Source is External) Clamp COAST Source 0: Internal PLL COAST 1: External PLL COAST 0: Active-Low 1: Active-High 0: Internal Clamp Pulse 1: External Clamp Pulse 0: Active-Low 1: Active-High 0: Internal Clamp COAST 1: External Clamp COAST R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0 Clamp Pulse Start Reference Edge (Pedestal Clamp, Midscale Clamp) R-ch Clamp Mode 0: the leading edge of HSYNC Input 1: the trailing edge of HSYNC Input 00b: Pedestal Clamp 01b: Midscale Clamp 10b: Reserved 11b: 256-level clamp 00b: Pedestal Clamp 01b: Midscale Clamp 10b: Reserved 11b: 256-level clamp 00b: Pedestal Clamp 01b: Midscale Clamp 10b: Reserved 11b: 256-level clamp G-ch Clamp Mode B-ch Clamp Mode Copyright(c)2013 THine Electronics, Inc. 11 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 18 R 19 R 1A R 1B R 1C R 1D R 1E R 1F 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 1 1 Clamp Pulse Start Position Set in 1 pixel steps with the reference edge of HSYNC Input (R17[6]). 0 to 255 Clamp Pulse Width Set in 1 pixel steps 1 to 255 SOG Slicer Hysterisis Enable SOG Input Filter 0: Disable 1: Enable 00b: Disable 01b: Enable 10b, 11b: Reserved Set in 15mV steps 15mV to 240mV above the Sync Tip SOG Slicer threshold SOGOUT Output Polarity SOGOUT Output Signal 0: Active-Low 1: Active-High 00b: Raw HSYNC 01b: Regenerated HSYNC 10b: Filtered HSYNC 11b: Reserved Preamp Bandwidth (Low Pass Filter) Output Format Reserved Reserved RGB DATA Output Drive Strength 00b: 4: 4: 4 Output 01b: 4: 4: 4 DDR Output 10b: 4: 2: 2 Output 11b: 4: 2: 2 DDR Output 0: Disable 1: Enable 00b: Pixel Clock 01b: 1/2x Pixel Clock 10b: Internal Oscillator (40MHz) 11b: Reserved Set in T/8 steps 0 to 7/8T *Bigger values mean more delay. Must be set to 0 Must be set to 1 00b: Weak 01b: Medium 10b: Strong 11b: Very Strong Sync (SOGOUT/HSOUT/VSOUT/OEFIELD) Output Drive Strength 00b: Weak 01b: Medium 10b: Strong 11b: Very Strong Clock Output Drive Strength 00b: Weak 01b: Medium 10b: Strong 11b: Very Strong HSOUT Output Signal 00b: HO 01b: Regenerated HSYNC 10b: Raw HSYNC 11b: Filtered HSYNC 4:2:2 Decimation Filter Enable Output Clock (DATACK) Output Clock Phase VSOUT Output Signal 00b: VO 01b: Regenerated VSYNC 10b: Raw VSYNC 11b: Filtered VSYNC O/E FIELD Output Signal 000b: FO 001b: Regenerated FIELD 010b: DE 011b: IRQ 100b to 111b: Reserved O/E FIELD Output Polarity 0: Odd FieldLow/Even Field=High 1: Odd FieldHigh/Even Field=Low Reserved Reserved PLL HSYNC Filter Enable HSYNC Filter Window Width Must be set to 0 Must be set to 0 0: Disable (Raw HSYNC) 1: Enable (Filtered HSYNC) Set in +/-100ns steps +/-100ns to +/-1600ns *Bigger values mean wider window. Copyright(c)2013 THine Electronics, Inc. 12 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 20 R 21 R 22 R 23 R 24 R 25 R 26 R 27 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R/W A A A A A A A 1 0 0 0 0 0 0 0 VSYNC Output Timing Automatic Setting Enable (Except Raw VSYNC) VSYNC Output (VO, Regenerated VSYNC) Start Position 0: Disable 1: Enable Set in 1 line steps -64 to +63 *Set in two's complement. A A A A A A R/W A A A A A A A 0 0 0 0 0 0 1 0 0 0 0 0 0 0 VSYNC Output (VO, Regenerated VSYNC) Pulse Width Set in 1 line steps 1 to 63 PLL COAST Timing Automatic Setting Enable PLL Pre-Coast (PLL COAST Start Position) *PLL free-runs during PLL COAST 0: Disable 1: Enable Set in 1 line steps 0 to 127 *PLL COAST Start Position prior to the leading edge of VSYNC Input. A A A A A A A 0 0 0 0 0 0 1 PLL Post-Coast (PLL COAST End Position) *PLL free-runs during PLL COAST Set in 1 line steps 0 to 127 *PLL COAST End Position after the leading edge of VSYNC Input. R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 1 1 0 Clamp Pre-Coast (Clamp COAST Start Position) *Clamp stops during Clamp COAST Set in 1 line steps 0 to 127 *Clamp COAST Start Position prior to the leading edge of VSYNC Input. R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 1 0 0 Clamp Post-Coast (Clamp COAST End Position) *Clamp stops during Clamp COAST Set in 1 line steps 0 to 127 *Clamp COAST End Position after the leading edge of VSYNC Input. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 1 1 1 0 0 0 0 DE Start Position Set in 1 pixel steps *DE Start Position after the leading edge of HSYNC Input. *VSYNC Output Start Position with reference to the leading edge of VSYNC Input. Copyright(c)2013 THine Electronics, Inc. 13 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 28 R 29 R 2A R 2B R 2C R 2D R 2E R 2F 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 0 0 0 0 0 0 0 DE Width Set in 1 pixel steps R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 V-Blank Front Porch (DE Low Start Position) Set in 1 line steps 0 to 127 *V-Blank Start Position prior to the leading edge of VSYNC Output. R/W R/W R/W R/W R/W R/W R/W R R R R R R R R 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 V-Blank Back Porch (DE Low Start Position) Set in 1 line steps 0 to 127 *V-Blank End Position after the trailing edge of VSYNC Output. R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC Input Polarity Detection HSYNC Input Polarity Detection Sync on Video 2-level/3-level Detection Interlace Detection Vertical Total Line Measurement Reserved Reserved Port-1 Input Sync Type Detection 00b: Separate Sync 01b: Composite Sync 10b: Sync on Video 11b: No Signal 00b: Separate Sync 01b: Composite Sync 10b: Sync on Video 11b: No Signal Port-0 Input Sync Type Detection Copyright(c)2013 THine Electronics, Inc. 0: Active-Low 1: Active-High 0: Active-Low 1: Active-High 0: 2-level 1: 3-level 0: Progressive 1: Interlace Reports the number of vertical total lines on the active input counted in 1/4 line unit. 14 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R 30 R 31 R 32 R 33 R 34 R 35 R 36 R 37 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 2 1 0 7 6 5 4 2 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 VSYNC Input Pulse Width Measurement Reports the number of VSYNC Pulse Width on the active input counted in 1/4 line unit. R/W R/W R/W 0 0 1 Reserved Reference Clock Enable from Clamp-pin for HSYNC Period Measurement HSYNC Period Measurement Run (Must be stop before reading the result) Must be set to 0 0: Disable 1: Enable 0: Stop 1: Run R R R R R R R R R R R R R R R R R R R R EVRC EVRC EVRC EVRC EVRC EVRC EVRC EVRC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSYNC Period Measurement Result Sync Signal Valid Flag Reserved Reserved Port-1 Input Sync Type Change Detection Port-0 Input Sync Type Change Detection Input Signal Format Change Detection Input HSYNC Missing Edge Detection Input HSYNC Extraneous Edge Detection Sync Processor IRQ Output Enable by Event Recorder (R34[7]) Reserved Reserved Sync Processor IRQ Output Enable by Event Recorder (R34[4]) Sync Processor IRQ Output Enable by Event Recorder (R34[3]) Sync Processor IRQ Output Enable by Event Recorder (R34[2]) Sync Processor IRQ Output Enable by Event Recorder (R34[1]) Sync Processor IRQ Output Enable by Event Recorder (R34[0]) Input Signal Format Change Detection - Threshold of Vertical Total Line Change Input Signal Format Change Detection - Threshold of VSYNC Input Pulse Width Input Signal Format Change Detection - Threshold of HSYNC Period Copyright(c)2013 THine Electronics, Inc. 0: Detect 1: Not Detect 0: Detect 1: Not Detect 0: Detect 1: Not Detect 0: Detect 1: Not Detect 0: Detect 1: Not Detect 0: Detect 1: Not Detect 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 000b: 0.5lines 001b: 1line 010b: 2lines 011b: 4lines 100b: 8lines 101b: 16lines 110b: 32lines 111b: Do not watching 00b: 0.5lines 01b: 1line 10b: 4lines 11b: Do not watching 000b: 8 001b: 16 010b: 32 011b: 64 100b: 128 101b: 256 110b: 512 111b: Do not watching 15 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Sync Signal Flow < Sync Processing Block Diagram > R12[3]+R12[1:0] 1/2 x Pixel Clock R1F[4] R1C[4:3] HSYNC0 HSYNC1 MUX HSYNC Filter POL MUX DATACK Pixel Clock R13[5] MUX PLL PLL COAST External Clock Filtered HSYNC SOGOUT Raw HSYNC CSYNC MUX POL R1B[7] R1B[6:5] Internal Oscillator 3-level Sliced SOGIN Regenerated HSYNC Internal Oscillator Clock 2-level Sliced SOGIN1 2-level Sliced SOGIN0 Regenerated HSYNC R1E[7:6] HO Sync Processor SOGIN0 Raw HSYNC MUX POL Filtered HSYNC SOG Slicer SOGIN1 HSOUT R13[2] R1E[5:4] VO R13[1] VSOUT Regenerated VSYNC Raw VSYNC R12[3]+R12[1:0] VSYNC0 POL MUX Filtered VSYNC R13[4] VSYNC1 MUX R1E[0] POL Regenerated FIELD POL CSYNC R1E[0] POL External REFCLK O/E FIELD FO DE IRQ Internal Clamp Pulse R31[1] R1E[3:1] MUX R16[2] R16[1] CLAMP DEMUX MUX POL Clamp Pulse External Clamp Pulse R16[0] Internal Clamp COAST MUX R04[1:0] R16[3] POL POL Polarity Select MUX Multiplexer DEMUX Demultiplexer Clamp COAST External COAST R16[4] DEMUX MUX EXTCLK/COAST PLL COAST Internal PLL COAST External Clock Copyright(c)2013 THine Electronics, Inc. 16 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Register Function R00 Revision Code 21h can be read R01[4] Chip Power-On 1: all the circuits power-on for normal operation. 0: the chip is set to stand-by mode. In stand-by mode, several circuits are active for sync monitoring. Stan-by mode can be triggered by RST-pin. < Power Control > R01[4] RST-pin Status ADC/PLL 1 1 0 0 Low High Low High Normal Operation Stand-by Stand-by Stand-by Power-On Power-Down Power-Down Power-Down Serial Interface Power-On Power-On Power-On Power-On SOG Slicer Power-On Power-On Power-On Power-On Sync Processor Power-On Power-On Power-On Power-On * During the stand-by mode, all the output pins except SOGOUT and SDA are disable (Hi-Z) . R01[3] Auto Output Enable 1: all the output pins are automatically enabled regardless of "Output Enable except SOGOUT (R01[2]) " or "SOGOUT Output Enable (R01[1]) " while input sync is detected. Input sync detection is processed in Sync Processor. * Output Pins are RED<9:0>, GREEN<9:0>, BLUE<9:0>, DATACK, SOGOUT, HSOUT, VSOUT, and O/E FIELD R01[2] Output Enable (Except SOGOUT) 1: Output pins except SOGOUT-pin are enabled. R01[1] SOGOUT Output Enable 1: SOGOUT-pin is enabled. < Output Control > R01[3] R01[2] R01[1] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Input Signal Inactive Active Inactive Active Inactive Active Inactive Active Inactive Active Inactive Active Inactive Active Inactive Active Output Signal except SOGOUT Disable Disable Disable Disable Enable Enable Enable Enable Disable Enable Disable Enable Enable Enable Enable Enable SOGOUT Disable Disable Enable Enable Disable Disable Enable Enable Disable Enable Enable Enable Disable Enable Enable Enable * When disabled, output pins are Hi-Z. * SDA-pin is always enabled. R01[0] Reserved * Must be set to 0 (Default Value: 0) Copyright(c)2013 THine Electronics, Inc. 17 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R02[6:5] Oversampling Oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and downsampling to the pixel clock rate with the decimation filter. When setting it as oversampling, setting of the PLL Divider Ratio (R02 [4:0] /R03 [7:0]) and the Charge Pump Current (R04 [4:2]) is unnecessary, but it's necessary to change the VCO frequency range (R04 [6:5]) . Every time the oversampling setting is increased one step, VCO frequency range also must be increased one step. 00b: Normal operation 01b: 2x Oversampling 10b: 4x Oversampling 11b: 8x Oversampling (ex) In case of 480i (HSYNC Frequency: 15.75kHz / Pixel Clock: 13.51MHz) Oversampling(R02[6:5]) 1x(00b) 2x(01b) 4x(10b) 8x(11b) VCO Range(R04[6:5]) 1/8(00b) 1/4(01b) 1/2(10b) 1/1(11b) Charge Pump(R04[4:2]) 250uA(011b) 250uA(011b) 250uA(011b) 250uA(011b) * Under the output of 4:4:4 DDR (R1C[7:6]=01b) or 4:2:2 DDR (R1C[7:6]=11b), the oversampling function can't be used. * "Internal PLL Divider Ratio" can't be over 8191. "Internal PLL Divider Ratio" = PLL Divider Ratio setting * Oversampling setting * Sampling frequency can't be over 170MHz Sampling frequency = Input HSYNC frequency * PLL Divider Ratio * Oversampling setting * Even if oversampling setting is changed, the output clock frequency and the output data rate don't change. * The latency of the data output changes according to the oversampling setting. R02[4:0]/R03[7:0] PLL Divider Ratio The internal PLL generates sampling clock from HSYNC. Set the number of horizontal total pixels per line according to the input signal. *When the external clock input which is supplied through EXTCLK/COAST-pin is used as sampling clock (R04[1:0]=10b or 11b), PLL Divider Ratio setting is unnecessary. R04[7] Reserved *Must be set to 1 (Default value: 1) R04[6:5] VCO Frequency Range *Set according to "Recommended PLL Settings" R04[4:2] Charge Pump Current *Set according to "Recommended PLL Settings" Copyright(c)2013 THine Electronics, Inc. 18 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R04[1:0] Sampling Clock Source Set to 00b, when the internal PLL generates sampling clock (pixel clock) from the HSYNC input. When an external clock input supplied through EXTCLK/COAST-pin is used and the clock frequency is from 10 to 20MHz, set to 10b. When an external clock input supplied through EXTCLK/COAST-pin is used and the clock frequency is from 20 to 170MHz, set to 11b. * Even though the external clock is used as sampling clock(R04[1:0]=10b or 11b) , setting like a Recommended PLL Settings are necessary. * When the external clock is used as sampling clock(R04[1:0]=10b or 11b) , PLL COAST and Clamp COAST can not be input (R16[4]=1, R16[0]=1) . < Recommended PLL Settings > 480i 480p 720p 1080i 1080p VGA-60 VGA-72 VGA-75 VGA-85 SVGA-56 SVGA-60 SVGA-72 SVGA-75 SVGA-85 XGA-60 XGA-70 XGA-75 XGA-80 XGA-85 SXGA-60 SXGA-75 SXGA-85 UXGA-60 Hsync [kHz] 15.750 31.469 45.000 33.750 67.500 31.479 37.861 37.500 43.269 35.156 37.879 48.077 46.875 53.674 48.363 56.476 60.023 64.000 68.677 63.981 79.976 91.146 75.000 Pixel Rate 13.51 27.00 74.25 74.25 148.50 25.18 31.50 31.50 36.00 36.00 40.00 50.00 49.50 56.25 65.00 75.00 78.75 85.50 94.50 108.00 135.00 157.50 162.00 PLL Divider 858 858 1650 2200 2200 800 832 840 832 1024 1056 1040 1056 1048 1344 1328 1312 1336 1376 1688 1688 1728 2160 Sampling Clock: Internal R04[6:5] 00 01 10 10 11 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11 R04[4:2] R04[1:0] 011 00 011 00 101 00 100 00 101 00 011 00 100 00 100 00 101 00 100 00 101 00 100 00 100 00 100 00 100 00 101 00 101 00 011 00 100 00 100 00 101 00 101 00 101 00 Sampling Clock: External R04 8C AC D4 D0 F4 AC B0 B0 B4 B0 B4 D0 D0 D0 D0 D4 D4 EC F0 F0 F4 F4 F4 R04[6:5] R04[4:2] 00 000 01 000 10 000 10 000 11 000 01 000 01 000 01 000 01 000 01 000 01 000 10 000 10 000 10 000 10 000 10 000 10 000 11 000 11 000 11 000 11 000 11 000 11 000 R04[1:0] 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 R04 82 A3 C3 C3 E3 A3 A3 A3 A3 A3 A3 C3 C3 C3 C3 C3 C3 E3 E3 E3 E3 E3 E3 * Other than the settings above, please refer to the other document, "THC7984 PLL Setting Sheet". R05[5:0] Sampling Clock Phase The sampling clock phase can be shifted in 64 steps of T/64. Bigger values mean more delay. * Even the external clock is used as sampling clock(R04[1:0]=10b or 11b) , the clock phase can be shifted. R06[2:0]/R07[7:0] R-ch (Pr-ch) Gain R08[2:0]/R09[7:0] G-ch (Y-ch) Gain R0A[2:0]/R0B[7:0] B-ch (Pb-ch) Gain The gain can be adjusted from 0.5 to 1.5 in 2048 steps. Bigger value means higher gain. Gain = (Register Value + 1024) / 2048 Because the full scale of ADC input is 0.7 Vpp (Typical Value) , the gain is set to [0.7 / Video Signal Level*]. * Signal Level without Sync on Video (Vpp) Example. Video Signal Level: 0.5 Vpp Gain = 0.7/0.5 =1.4 Register value=1843 Video Signal Level: 0.7 Vpp Gain = 0.7/0.7 =1.0 Register value=1024 Video Signal Level: 1.0 Vpp Gain = 0.7/1.0 =0.7 Register value=410 * The setting method above is not always necessary for the purpose of contrast adjustment. Bigger gain means higher contrast. Copyright(c)2013 THine Electronics, Inc. 19 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R0C[0]/R0D[7:0] R-ch (Pr-ch) Clamp Level Offset R0E[0]/R0F[7:0] G-ch (Y-ch) Clamp Level Offset R10[0]/R11[7:0] B-ch (Pb-ch) Clamp Level Offset Clamping restores DC level of the video signals. Three clamp modes can be selected; Pedestal clamp, Center clamp (Midscale clamp) , and Sync tip clamp (R17[5:4]/R17[3:2]/R17[1:0]) . It's possible to give an offset to the clamp level by the 1LSB unit by a clamp level offset. The register value is configured by two's complement from -256 to +255. < Clamp Level Offset > 1023 Clamp Level Offset = 0 Clamp Level Offset > 0 Clamp Level Offset < 0 Output Code (Pedestal Clamp) 0 Clamp Level Offset 1023 Clamp Level Offset = 0 Clamp Level Offset > 0 Clamp Level Offset < 0 Output Code 512 (Center Clamp) 0 Clamp Level Offset 1023 Clamp Level Offset = 0 Clamp Level Offset > 0 Clamp Level Offset < 0 Output Code (256-level Clamp) 256 0 Clamp Level Offset R12[7:6] Reserved *Must be set to 00b (Default value: 00b) R12[5] Input Port Automatic Selection Enable 1: Selection input port (R12[3]) is done automatically. Under Automatic setting, with the judgement result of the input SYNC type by Sync Processor, An activated port is selected with the following rules. -When the selected port is activated, even if the other port becomes activated, selection of port doesn't change. -Both ports are activate and one port which is selected became inactivate, selection of port changes to the other port. Copyright(c)2013 THine Electronics, Inc. 20 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R12[4] Reserved * Must be set to 0 (Default Value: 0) R12[3] Input Port Select 0: Port-0 is selected. Port-0: HSYNC0, VSYNC0, RAIN0, GAIN0, SOGIN0, BAIN0 1: Port-1 is selected. Port-1: HSYNC1, VSYNC1, RAIN1, GAIN1, SOGIN1, BAIN1 R12[2] Input Sync Type Automatic Select Enable 1: Input Sync Type Select (R12[1:0]) is automatically set. When Automatic Select is enabled, Input Sync Type Select is determined by sync processor based on the result of Input Sync Type Detection(R2C[6:5]/R2C[4:3]/R2C[0]) . R12[1:0] Input Sync Type Select Select the input sync type. The combination of Input Port Select (R12[3]) and Input Sync Type Select (R12[1:0]) determines the input pin for HSYNC and VSYNC. < Input Port / Sync Type > HSYNC Input P in HSYNC0 HSYNC0 VSYNC In pu t P in VSYNC0 HSYNC0 S ync on V ide o (2- le ve l) S O G IN 0 S O G IN 0 1 1b S ync on V ide o (3- le ve l) S O G IN 0 * S O G IN 0* P ort-1 P ort-1 0 0b 0 1b S eparate S ync C om posite S ync HSYNC1 HSYNC1 VSYNC1 HSYNC1 1 P ort-1 1 0b S ync on V ide o (2- le ve l) S O G IN 1 S O G IN 1 1 P ort-1 1 1b S ync on V ide o (3- le ve l) S O G IN 1 * S O G IN 1* R 12 [3] Input P ort R 12 [1:0 ] S ync T ype 0 0 P ort-0 P ort-0 0 0b 0 1b S eparate S ync C om posite S ync 0 P ort-0 1 0b 0 P ort-0 1 1 *3-level sliced (pedestal slice) . R13[6] HSYNC Input, VSYNC Input Polarity Automatic Select Enable 1: HSYNC Input Polarity (R13[5]) and VSYNC Input Polarity (R13[4]) are automatically set. When Automatic Select is enabled, the sync input polarity is determined by sync processor based on the result of HSYNC Input Polarity Detection (R2C[1]) and VSYNC Input Polarity Detection (R2C[2]) . R13[5] HSYNC Input Polarity HSYNC Input Polarity must be correctly set for normal operation. Set to 0 when the input polarity is Active-Low. Set to 1 when the input polarity is Active-High. * Set to 0 when Input Sync Type Select is set to "Sync on Video (3-level) " (R12[1:0]=11b) . R13[4] VSYNC Input Polarity VSYNC Input Polarity must be correctly set for normal operation. Set to 0 when the input polarity is Active-Low. Set to 1 when the input polarity is Active-High. Copyright(c)2013 THine Electronics, Inc. 21 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R13[3] HSYNC Output, VSYNC Output Polarity Automatic Select Enable 1: HSYNC Output Polarity (R13[2]) and VSYNC Output Polarity (R13[1]) are automatically set to the same polarity as the input. When Automatic Select is enabled, the sync output polarity is determined by sync processor based on the result of HSYNC Input Polarity Detection (R2D[1]) and VSYNC Input Polarity Detection (R2D[2]) . R13[2] HSYNC Output (HSOUT) Polarity Select the HSYNC output polarity of HSOUT-pin. 0: Output polarity is Active-Low. 1: Output polarity is Active-High. * The polarity of HSYNC available from HSOUT-pin (HO, Regenerated HSYNC) is selected. R13[1] VSYNC Output (VSOUT) Polarity Select the VSYNC output polarity of VSOUT-pin. 0: Output polarity is Active-Low. 1: Output polarity is Active-High. * The polarity of VSYNC available from VSOUT-pin (VO, Regenerated VSYNC, Raw VSYNC) is selected. R13[0] VSYNC Output (VSOUT) Interlace Mode Select the output mode of VSYNC available from VSOUT-pin (VO, Regenerated VSYNC) for interlaced video input. 1: VSYNC Output (VO, Regenerated VSYNC) is produced at the center of horizontal period when video field of interlaced video changes from ODD field to EVEN field. 0: VSYNC Output is produced only at the start position of horizontal period. Consequently, the vertical total line number of interlaced video changes by 1 depending on video field. * The output mode of VSYNC available from VSOUT-pin (VO, Regenerated VSYNC) is selected. Raw VSYNC is not affected by this mode. * The edge of VSYNC Output always occurs at the start position of horizontal period for non-interlaced video (Detection result: R2E[7]=0) . Therefore, R13[0]=0 and R13[0]=1 produce the same result for non-interlaced video. < VSOUT Interlace Mode > EVEN Field -> ODD Field Horizontal Cycle Input Sync VSOUT (R13[0]=1) VSOUT (R13[0]=0) ODD Field -> EVEN Field Horizontal Cycle Input Sync VSOUT (R13[0]=1) VSOUT (R13[0]=0) Copyright(c)2013 THine Electronics, Inc. 22 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R14[7:0] HSYNC Output (HO) Start Position Set the start position of HO available from HSOUT-pin in steps of 1 pixel with reference to the leading edge of the HSYNC (It is the leading edge of the positive pulse when it is 3-level sync) . The register value is configured by two's complement from -128 to +127. * When the external clock input is used (R04[1:0]=10b or 11b) , minus number is prohibited. R15[7:0] HSYNC Output (HO) Pulse Width Set the pulse width of HO available from HSOUT-pin in steps of 1 pixel. < HO Start Position / Pulse Width > HSYNC / CSYNC / Sync on Video (2-level) Input HSYNC Start Position HO (Start Position < 0) Pulse Width HO (Start Position > 0) Start Position Sync on Video (3-level) Input HSYNC Start Position HO (Start Position < 0) Pulse Width HO (Start Position > 0) Start Position R16[4] PLL COAST Source PLL should stop synchronization with the HSYNC input during the vertical blank time including the pulses disturbing PLL lock and the sampling clock generation such as equalization pulses and copy protection signal. PLL COAST signal causes PLL to stop synchronization with the HSYNC input and free-run. 0: PLL COAST signal is internally generated in the device. 1: PLL COAST signal can be externally input from COAST-pin. * When PLL COAST signal is internally generated, automatic setting mode (R22[7]) is available. R16[3] PLL COAST Input Polarity Select the input polarity of PLL COAST signal when externally input (R16[4]=1) . Set to 0 when the input polarity is Active-Low (PLL free-runs at COAST-pin=Low) . Set to 1 when the input polarity is Active-High (PLL free-runs at COAST-pin=High) . R16[2] Clamp Pulse Source Select the generation source of clamp pulse which is a timing signal of a clamp 0: The clamp pulse is generated internally. 1: Clamp pulse must be inputted through Clamp-pin. R16[1] Clamp Pulse Input Polarity Select input polarity when the external clamp pulse is used (R16[2]=1). 0: Input polarity becomes Active-Low. 1: Input polarity becomes Active-High. Copyright(c)2013 THine Electronics, Inc. 23 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R16[0] Clamp COAST Source It's sometimes necessary to make the clamp suspend while the period which is including the signals that disturb the clamp such as a copy protection signal. The clamp COAST signal is the signal which makes the clamp stop. 0: Internal Clamp COAST 1: External Clamp COAST R17[6] Clamp Pulse Start Reference Edge The timing of Clamp pulse is set based on the edge of the HSYNC input. Selecting the edge of the HSYNC input 0: the leading edge of the HSYNC input is referred. 1: the trailing edge of the HSYNC input is referred. * In case of 3-level sync, the leading edge or trailing edge of the positive pulse is referred. R17[5:4] R-ch (Pr-ch) Clamp Mode R17[3:2] G-ch (Y-ch) Clamp Mode R17[1:0] B-ch (Pb-ch) Clamp Mode As a clamp method, pedestal clamp, midscale clamp, and 256-level clamp can be selected. 00b: Pedestal clamp for RGB and Y (luminance) clamps black level to 0 with automatic offset cancel (if clamp level offset is set to 0) . The Automatic offset cancel circuitry eliminates any offset errors. 01b: Midscale clamp for PbPr clamps to 512 with automatic offset cancel (if clamp level offset is set to 0) . The Automatic offset cancel circuitry eliminates any offset errors. 10b: Reserved 11b: 256-level clamp clamps to 256 with automatic offset cancel (if clamp level offset is set to 0). The Automatic offset cancel circuitry eliminates any offset errors. * It's possible to set a clamp pulse on sync part and realize sync tip clamp by a pedestal clamp (R17 [5:4], R17 [3:2] and R17 [1:0] =00b) . R18[7:0] Clamp Pulse Start Position Set the clamp pulse start position in steps of 1 pixel with reference to clamp pulse start reference edge (selected by R17[6]) . R19[7:0] Clamp Pulse Width Set the clamp pulse width in steps of 1 pixel. * When the register is set to 0, clamp pulse is not generated. * Set the end position of clamp pulse (R18[7:0] + R19[7:0]) more than 16 pixels front of active video period because Clamp Offset Cancel is completed after 16 pixels from the clamp pulse. Copyright(c)2013 THine Electronics, Inc. 24 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E < Clamp Pulse Start Position / Pulse Width > HSYNC / CSYNC / Sync on Video (2-level) Input HSYNC Start Position Clamp Pulse (R17[6]=0) Start Position Clamp Pulse (R17[6]=1) Pulse Width Sync on Video (3-level) Input HSYNC Start Position Clamp Pulse (R17[6]=0) Start Position Clamp Pulse (R17[6]=1) Pulse Width R1A[6] SOG Slicer Hysterisis Enable 1: SOG Slicer works with about 30mV hysteresis. R1A[5:4] SOG Input Filter SOG Input Filter (low pass filter) can reduce the noise and the ringing, etc. of SOG input. 00b: OFF (Through) 01b: ON 10b,11b: Reserved *The default value is 10b(Reserved) , so please change the setting to 00b (OFF) or 01b (ON) . R1A[3:0] SOG Slicer threshold When Input Sync Type Select is set to "Sync on Video (2-level) " (R12[1:0]=10b) , input signal from SOGIN0 or SOGIN1 is sliced at the selected level by R1A[3:0] relative to the lowest level (sync tip) to extract the sync signal. SOG slicer threshold can be adjusted from15 mV to 240 mV in steps of 15 mV. *Set the value of SOG Slicer threshold to 3 and over. < SOG Slicer > SOG Slice Level (R1A[3:0]) Sync on Video Extracted Sync Copyright(c)2013 THine Electronics, Inc. 25 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E * <2-Level Slice / 3-Level Slice> Sync on Video (2-Level) Sync on Video Sliced at SOG Slice Level (R1A[3:0]) Extracted Sync Sync on Video (3-Level) Sliced at Pedestal Level Sync on Video Extracted Sync *When setting the input sync signal as Sync on Video (2-level) at the time of 3-level sync signal input, (R12 [1:0], =10b) , it is sliced by the SOG slicer threshold. R1B[7] SOGOUT Output Polarity Select the output polarity of SOGOUT-pin. 0: Output polarity is Active-Low. 1: Output polarity is Active-High. * The polarity of signals available from SOGOUT-pin (Raw HSYNC, Regenerated HSYNC, and Filtered HSYNC) is selected. R1B[6:5] SOGOUT Output Signal Select the output signal from SOGOUT-pin. The source signal of the output is HSYNC selected by the combination of Input Port Select (R12[3]) and Input Sync Type Select (R12[1:0]) . 00b: Raw HSYNC --- Buffered signal of the HSYNC input. 01b: Regenerated HSYNC --- This HSYNC is generated by using the internal oscillator (about 40 MHz) from Raw HSYNC. It has jitter of several internal oscillator clock cycles. 10b: Filtered HSYNC --- By the HSYNC Filter, the pulses which are not related to Horizontal period is eliminated. 11b: Reserved < Output Signal from SOGOUT> Horizontal Period Input HSYNC Raw HSYNC Regenerated HSYNC Filtered HSYNC Copyright(c)2013 THine Electronics, Inc. 26 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1B[4:0] Pre-Amp Bandwidth (Low Pass Filter) The THC7984 has the internal 5th-order Low Pass Filters as anti-aliasing filter for component video input (YPbPr) , and it's possible to control cut-off frequency in 24 steps between 6 to 92MHz by setting the register. The THC7984 also has the internal 2nd-order Low Pass Filters to filter the noise and glitch of PC input (RGB) , and it's possible to control cut-off frequency in 4 steps (40 MHz/90 MHz/170 MHz/310 MHz) by setting the register. < Preamp Bandwidth> Analog Input Preamp Output (ADC Input) < Cutoff Frequency > Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R1B[4:0] Binary 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 fc Note 0 6MHz 1 7MHz 0 8MHz 1 9MHz 0 10MHz 1 11MHz 0 12MHz 1 13.5MHz 5th-order LPF 0 15MHz for Component Video 1 18MHz 0 21MHz 1 24MHz 0 27MHz 1 30MHz 0 33MHz 1 36MHz Dec 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R1B[4:0] Binary 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 fc 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 39MHz 42MHz 46MHz 52MHz 58MHz 66MHz 78MHz 92MHz 40MHz 90MHz 170MHz 310MHz Note 5th-order LPF for Component Video 2nd-order LPF for PC Reserved Reserved Reserved Reserved *Setting example Component video input: About 0.5 times of the sampling frequency is used as cut-off frequency. PC input: About 1.5 times of the sampling frequency is used as cutoff frequency. *When R54[4] is set to 1, it's possible to control the cut-off frequency of a 5th-order lowpass filter in steps of 1MHz between 25MHzto 39MHz by using register R54 [3:0]. In this case, R1B [4:0] is ignored. < Cutoff Frequency > R54[3:0] Binary Dec 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 Copyright(c)2013 THine Electronics, Inc. fc Note 25MHz 26MHz 27MHz 28MHz 29MHz 30MHz 31MHz 32MHz 33MHz 34MHz 34MHz 35MHz 36MHz 37MHz 38MHz 39MHz 5th-order LPF for Component Video 27 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1C[7:6] Output Format 4 output formats can be selected. 00b: 4:4:4 Output 01b: 4:4:4 DDR Output 10b: 4:2:2 Output 11b: 4:2:2 DDR Output * 4:4:4 DDR Output and 4:2:2 DDR Output are supported up to 85 MHz of sampling clock. <Output Format> RED Output Format Normal 4:4:4 DDR Normal 4:2:2 DDR GREEN BLUE Edge 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 R[9:0] G[9:0] B[9:0] G[4:0] B[9:0] R[9:0] G[9:5] Cb/Cr Y Cb/Cr Y * The pins not assigned to output data are disabled (Hi-Z) . < 4:4:4 Normal Output > RED[9:0] R0 R1 R2 R3 R4 R5 GREEN[9:0] G0 G1 G2 G3 G4 G5 BLUE[9:0] B0 B1 B2 B3 B4 B5 DATACK R1C[4:3]=00b R1C[2:0]=000b HO, DE HO, DE Start Position = Even HO, DE Start Position = Odd * DATACK can be shifted in 8 steps (R1C[2:0]) . < 4:4:4 DDR Output > RED[9:5] G0L RED[4:0] B0M R0L B1M R1L B2M R2L B3M GREEN[9:5] B0L G0M B1L G1M B2L G2M B3L G3M B4L G4M R0M G1L R1M G2L R2M G3L R3M G4L R4M G5L R5M R3L B4M R4L B5M R5L B5L G5M DATACK R1C[4:3]=00b R1C[2:0]=000b HO, DE HO, DE Start Position = Even HO, DE Start Position = Odd * "M" indicates upper 5 bits in MSB side. "L" indicates lower 5 bits in LSB side. * DATACK can be shifted in 8 steps (R1C[2:0]) . Copyright(c)2013 THine Electronics, Inc. 28 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E < 4:2:2 Normal Output > RED[9:0] GREEN[9:0] Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Y0 Y1 Y2 Y3 Y4 Y5 DATACK R1C[4:3]=00b R1C[2:0]=000b HO, DE HO, DE Start Position = Even HO, DE Start Position = Odd * DATACK can be shifted in 8 steps (R1C[2:0]) . < 4:2:2 DDR Output > BLUE[9:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 DATACK R1C[4:3]=00b R1C[2:0]=000b HO, DE HO, DE Start Position = Even HO, DE Start Position = Odd * DATACK can be shifted in 8 steps (R1C[2:0]) . R1C[5] 4:2:2 Decimation Filter Enable Set the way of downsampling (process of changing from 4:4:4 to 4:2:2) of CbCr in 4:2:2 output and 4:2:2 DDR output 0: CbCr is sampled every two pixel by pixel skipping. 1: CbCr is decimated by digital filter. Copyright(c)2013 THine Electronics, Inc. 29 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1C[4:3] Output Clock Select Select a output signal from DATACK-pin. 00b: Pixel Clock: the same frequency as the sampling clock 01b: 1/2 x Pixel Clock: half the frequency of the sampling clock 10b: Internal Oscillator (approximately 40 MHz) 11b: Reserved R1C[2:0] Output Clock Phase Since the output clock phase can be shifted in 8 steps, the setup and hold time of output data can be adjusted. * If DATACLK is Pixel Clock(R1C[4:3]=00b) , Phase setteing 0-2 is not recommended to use (except for DDR output) because rising edge of output clock will be around the transition period of output data. * The phase of internal oscillator clock (R1C[4:3]=10b) can not be controlled. * When oversampling setting is 8 times, the output clock pahse is possible to set in only 4 steps. (the value of 0 and 1 , 2 and 3, 4 and 5, 6 and 7 will be the same phase setting.) < DATACK Phase Shift> Output Data (Normal Output) Output Data (DDR Output) HO, DE Start Position =Even HO, DE HO, DE Start Position =Odd DATACK: Pixel Clock R1C[2:0]=0 R1C[2:0]=1 R1C[2:0]=2 R1C[2:0]=3 R1C[2:0]=4 R1C[2:0]=5 R1C[2:0]=6 R1C[2:0]=7 DATACK: 1/2 x Pixel Clock R1C[2:0]=0 R1C[2:0]=1 R1C[2:0]=2 R1C[2:0]=3 R1C[2:0]=4 R1C[2:0]=5 R1C[2:0]=6 R1C[2:0]=7 Copyright(c)2013 THine Electronics, Inc. 30 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1D[7:6] Reserved *Must be set to 01b for proper operation (Default value: 10b) R1D[5:4] RGB DATA Output Drive Strength Output pins: RED<9:0>, GREEN<9:0>, BLUE<9:0> R1D[3:2] Sync Output Drive Strength Output pins: SOGOUT, HSOUT, VSOUT, O/E FIELD R1D[1:0] Clock Output Drive Strength Output pins: DATACK Bigger values mean stronger output drive strength. * Output drive strength should be adjusted according to the load capacitance, the trance length on PCB, and the power supply voltage of output buffer (VDD) . * Clock output drive strength is stronger than others. R1E[7:6] HSOUT Output Signal Select Select a output signal from HSOUT-pin. 00: HO --- HSYNC generated from the HSYNC input, and synchronous with the PLL clock. Output polarity (R13[2]) , Start Position (R14[7:0]) , and Pulse Width (R15[7:0]) can be selected by the register setting. PLL parameter settings (R02 to R04) are necessary for normal output. HO can be used as a reference of the image (RGB data) alignment. 01: Regenerated HSYNC --- HSYNC generated from the HSYNC input, and synchronous with the internal oscillator clock (approximately 40 MHz) . The start position is delayed some internal oscillator clock cycles after the leading edge of the HSYNC input, and the pulse width is approximately 1/16 of horizontal period. The polarity is selected by register (R13[2]) . PLL parameter settings (R02 to R04) are unnecessary for normal output. It has jitter of several internal oscillator clock cycles. 10b: Raw HSYNC --- Buffered signal of the HSYNC input. 11b: Filtered HSYNC --- The Raw Hsync's pulse which is not relate to horizontal period is removed by the HSYNC Filter (R1F[3:0]. < Output Signal from HSOUT> Horizontal Period Input VSYNC HO Regenerated HSYNC Raw HSYNC Filtered HSYNC Copyright(c)2013 THine Electronics, Inc. 31 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1E[5:4] VSOUT Output Signal Select Select a output signal from VSOUT-pin. 00b: VO --- VSYNC generated from the HSYNC and VSYNC input, and synchronous with the PLL clock. Output polarity (R13[1]) , Start Position (R20[6:0]) , and Pulse Width (R21[5:0]) can be select by the register setting (auto setting modes are available) . PLL parameter settings (R02 to R04) are necessary for normal output. It is synchronous with HO. 01b: Regenerated VSYNC --- VSYNC generated from the HSYNC and VSYNC input, and synchronous with the internal oscillator clock (approximately 40 MHz) . Output polarity (R13[1]) , Start Position (R20[6:0]) , and Pulse Width (R21[5:0]) can be selected by the register setting (auto setting modes are available) . PLL parameter settings (R02 to R04) are unnecessary for normal output. It has jitter of several internal oscillator clock cycles. It is synchronous with Regenerated HSYNC. 10b: Raw VSYNC --- Buffered signal of the VSYNC input 11b: Filtered VSYNC --- VSYNC generated from the HSYNC and VSYNC input, and digitally filtered with the internal oscillator clock (approximately 40 MHz). It's possible to set polarity (R13 [1]) by register. (An automatic setting mode is available.) It's generated regardless of PLL setting (R02-R04). It has jitter of several internal oscillator clock cycles. The output phase is delayed about 3/4 H to input VSYNC. < Output Signal from VSOUT> Horizontal Period Input VSYNC VO Regenerated VSYNC Raw VSYNC Filtered VSYNC Copyright(c)2013 THine Electronics, Inc. 32 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1E[3:1] O/E FIELD Output Signal Select Select a output signal from O/E FIELD-pin. 000b: FO --- Odd / Even FIELD generated from the HSYNC and VSYNC input, and synchronous with the PLL clock. Output polarity (R1E[0]) can be select by the register setting. PLL parameter settings (R02 to R04) are necessary for normal output. It is synchronous with VO. 001b: Regenerated FIELD --- Odd / Even FIELD generated from the HSYNC and VSYNC input, and synchronous with the internal oscillator clock (approximately 40 MHz) . Output polarity (R1E[0]) can be selected by the register setting. PLL parameter settings (R02 to R04) are unnecessary for normal output. It has jitter of several internal oscillator clock cycles. It is synchronous with Regenerated VSYNC. 010b: DE --- Data Enable signal generated from the HSYNC and VSYNC input, and synchronous with the PLL clock. The polarity is Active-High. Start Position (R26[3:0]/R27[7:0]) , Pulse Width(R28[3:0]/R29[7:0]) , Vertical Blank Front Porch (R2A[6:0]) and Back Porch (R2B[6:0]) are programmable by registers (auto setting modes are not available) . 011b: IRQ --- Interrupt Request Signal from Sync Processor. 100b - 111b: Reserved < FO / Regenerated FIELD> Horizontal Period VSYNC Input FO Regenerated FIELD R1E[0] O/E FIELD Output Polarity Select the polarity of FO and Regenerated FIELD available from O/E FIELD-pin 0: O/E FIELD=Low in Odd FIELD, O/E FIELD=High in Even FIELD. 1: O/E FIELD=High in Odd FIELD, O/E FIELD=Low in Even FIELD. < FO / Regenerated FIELD> EVEN Field -> ODD Field Horizontal Period Sync Input FIELD (R1E[0]=0) FIELD (R1E[0]=1) ODD Field -> EVEN Field Horizontal Period Input Sync FIELD (R1E[0]=0) FIELD (R1E[0]=1) Copyright(c)2013 THine Electronics, Inc. 33 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R1F[6:5] Reserved *Must be set to 00b for proper operation (Default value: 00b) R1F[4] PLL HSYNC Filter Enable By using Filtered HSYNC generated by HSYNC Filter that eliminates the extraneous pulses such as equalization pulses and copy protection signal from the HSYNC input (Raw HSYNC) , the PLL COAST period (PLL free-run period) can be set shorter. However, the HSYNC input with high jitter makes HSYNC Filter Window unstable and possibly causes PLL unlock. 0: Raw HSYNC is used as the reference signal of PLL. 1: Filtered HSYNC is used as the reference signal of PLL. R1F[3:0] HSYNC Filter Window Width Set HSYNC Filter Window Width of HSYNC Filter. The setting range is from about +/-100ns (internal oscillator clock +/-4 cycles) to about +/-1600ns (internal oscillator clock +/-64 cycles) around the leading edge of the HSYNC input (the leading edge of the positive pulse for 3-level sync) . The setting step is +/-100ns (internal oscillator clock +/-4 cycles) and bigger value results in wider width. < HSYNC Filter > Input HSYNC Leading Edge Input HSYNC with extraneous pulses Excessive Edge Filter Window Width Filter Window Filtered HSYNC Suppressed Filter Window = High: Not suppressed Filter Window = Low: Falling Edges are suppressed *Input HSYNC into HSYNC Filter is always Active-Low Copyright(c)2013 THine Electronics, Inc. 34 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E *About timing of input VSYNC Input VSYNC Forbidden Region 15% 0% 35% 85% 65% 100% Input HSYNC Input VSYNC Input VSYNC Forbidden Region When the transition of VSYNC is in "Input VSYNC Forbidden Region", it is possible that following vertical timing fluctuates about one line. VSYNC output (VO, Regenerated VSYNC) ---Setting Register: R20[6:0]/R21[5:0] PLL COAST Timing ---Setting Register: R22[6:0]/R23[6:0] Clamp COAST Timing ---Setting Register: R24[6:0]/R25[6:0] DE Restraint period ---Setting Register: R2A[6:0]/R2B[6:0] The edge of Input VSYNC must be outside "Input VSYNC Forbidden Region" to prevent fluctuation of these vertical timing. R20[7] VSYNC Output (VO, Regenerated VSYNC) Timing Automatic Setting Enable When set to 1, VSYNC Output Start Position (R20[6:0]) and VSYNC Output Pulse Width (R21[5:0]) are automatically set to match the VSYNC input timing. The VSYNC Output Start Position is set to 0 and the VSYNC Output Pulse Width is determined by sync processor based on the result of VSYNC Input Pulse Width Measurement (R2F[7:0]). R20[6:0] VSYNC Output (VO, Regenerated VSYNC) Start Position The starting position of VO and Regenerated VSYNC, which are the possible output from VSOUT-pin, is set in steps of 1 line based on leading edge of Input VSYNC. The set value is expressed by complement of 2 and the set range is from 64 to +63. R21[5:0] VSYNC Output (VO, Regenerated VSYNC) Pulse Width The pulse width of VO and Regenerated VSYNC, which are the possible output from VSOUT-pin, is set in steps of 1 line. < Output VSYNC Start Position / Pulse Width > Horizontal Period Input VSYNC Output VSYNC (R20[6:0]= -1) Output VSYNC (R20[6:0]= 0) Output VSYNC (R20[6:0]= +1) Output VSYNC Pulse Width Copyright(c)2013 THine Electronics, Inc. 35 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R22[7] PLL COAST Timing Automatic Setting Enable PLL should stop synchronization with the HSYNC input during the vertical blank time including the pulses disturbing PLL lock and the sampling clock generation such as equalization pulses and copy protection signal. PLL COAST signal causes PLL to stop synchronization with the HSYNC input and free-run. 1: PLL Pre-COAST (R22[6:0]) and PLL Post-COAST (R23[6:0]) are automatically set PLL COAST Period generated by automatic setting is depend on the setting of PLL HSYNC Filter Enable (R1F[4]) . * When HSYNC Filter is disabled (R1F[4]=0) , the PLL COAST period covers the period including extraneous and missing pulses in vertical blank time. * Even in the case Input Sync Type is set to "Separate Sync" (R12[1:0]=00b) , the PLL COAST signal covers the VSYNC pulse period. * When HSYNC Filter is enabled (R1F[4]=1) , the PLL COAST period covers the VSYNC pulse period because extraneous pulses are eliminated by HSYNC Filter. < PLL COAST Auto Mode> Horizontal Period Input HSYNC HSYNC Filter Disable (R1F[4]=0) Raw HSYNC PLL COAST HSYNC Filter Enable (R1F[4]=1) Filtered HSYNC PLL COAST R22[6:0] PLL Pre-COAST Set the start position of PLL COAST in steps of 1 line with reference to the leading edge of the VSYNC input. R23[6:0] PLL Post-COAST Set the end position of PLL COAST in steps of 1 line with reference to the leading edge of the VSYNC input. < PLL COAST Timing> Horizontal Period Input VSYNC PLL COAST PLL Post-COAST PLL Pre-COAST Copyright(c)2013 THine Electronics, Inc. 36 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R24[6:0] Clamp Pre-COAST Clamp should be suspended during the vertical blank time including the pulses disturbing clamp such as copy protection signal. Clamp COAST signal causes clamp to be suspend. Set the start position of Clamp COAST in steps of 1 line with reference to the leading edge of the VSYNC input. R25[6:0] Clamp Post-COAST Set the end position of Clamp COAST in steps of 1 line with reference to the leading edge of the VSYNC input. < Clamp COAST Timing> Horizontal Period Analog Input Clamp COAST Clamp Pre-COAST Clamp Post-COAST * Clamp COAST timing is related to a 3-level slicer. In case that Sync type select is "Sync on Video (3-level) " (R12[1:0]=11b) , Clamp COAST timing should cover VSYNC pulse (and the period which includes equalization pulses in interlace signal) , and end at least 12 lines prior to the active line start. (Setting example: Clamp Pre-COAST=2 / Clamp Post-COAST=8). R26[3:0] / R27[7:0] DE Start Position set the start position of DE (Data Enable) available from O/E FIELD-pin in steps of 1 pixel with reference to the leading edge of the HSYNC input (the leading edge of the positive pulse for 3-level sync) . R28[3:0] / R29[7:0] DE Pulse Width set the pulse width of DE (Data Enable) available from O/E FIELD-pin in steps of 1 pixel. The output polarity of DE is Active-High. < DE Horizontal Timing> Input HSYNC DE Start Position DE DE Pulse Width R2A[6:0] V-Blank Front Porch (DE End Line Position) Set the end line of DE (Data Enable) available from O/E FIELD-pin in steps of 1 line with reference to the VSYNC Output Start Position (R20[6:0]) . R2B[6:0] V-Blank Back Porch (DE Start Line Position) Set the start line of DE (Data Enable) available from O/E FIELD-pin in steps of 1 line with reference to the VSYNC Output End Position (R20[6:0]+R21[5:0]) . < V-Blank Front Porch / V-Blank Back Porch > Horizontal Period Input VSYNC Output VSYNC Pulse Width Output VSYNC DE Copyright(c)2013 THine Electronics, Inc. V-Blank Front Porch 37 / 45 V-Blank Back Porch THine Electronics, Inc. THC7984_Rev.2.0_E R2C[3:2] Port-1 Input Sync Type Detection R2C[1:0] Port-0 Input Sync Type Detection The result of Input Sync Type Detection can be read. < Input Sync Type Detection > HSYNC VSYNC SOGIN Input Sync Type Not Active Not Active Not Active Not Active Active Active Active Active Not Active Not Active Active Active Not Active Not Active Active Active Not Active Active Not Active Active Not Active Active Not Active Active No Signal Sync on Video No Signal Sync on Video Composite Sync Composite Sync Separate Sync Separate Sync R2C[3:2] R2C[1:0] 11b 10b 11b 10b 01b 01b 00b 00b R2D[2] VSYNC Input Polarity Detection The result of VSYNC Input Polarity Detection can be read. 0: Input polarity is Active-Low. 1: Input polarity is Active-High. R2D[1] HSYNC Input Polarity Detection The result of HSYNC Input Polarity Detection can be read. 0: Input polarity is Active-Low. 1: Input polarity is Active-High. R2D[0] Sync on Video 2-level / 3-level Detection When the result of Input Sync Type Detection of the selected input port (R12[3]) is Sync on Video (R2C[6:5], R2C[4:3]=10b) , the result of Sync on Video 2-level / 3-level Detection can be read. 0: Sync on Video is 2-level. 1: Sync on Video is 3-level. * When Input Sync Type is not Sync on Video, 0 can be read. R2E[7] Interlace Detection The result of Interlace Detection detected by the HSYNC and VSYNC input can be read. 0: Input signal is non-interlace (progressive) . 1: Input signal is interlace. R2E[6:0] / R2F[7:0] Vertical Total Line Measurement The result of Vertical Total Line Measurement measured by the HSYNC and VSYNC input can be read in 1/4 line unit. R30[7:0] VSYNC Input Pulse Width Measurement The result of VSYNC Input Pulse Width Measurement measured by the HSYNC and VSYNC input can be read in 1/4 line unit. R31[2] Reserved * Must be set to 0 (Default Value: 0) R31[1] External REFCLK Input Enable 1: It is possible to measure the horizontal period (R32[3:0] / R33[7:0] / R34[7:0]) by inputting clock which is 7 - 40 MHz to CLAMP-pin. The frequency precision of the input clock influences a result of measurement directly, so please input the clock with the high frequency precision. * If the external REFCLK input is enable (R31[1]=1) , the function of external clamp pulse (R16[2]) can not be used. Copyright(c)2013 THine Electronics, Inc. 38 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R31[0] HSYNC Period Measurement Run 0: Stop the Measurement of HSYNC Period. 1: Start Measurement of HSYNC Period. (A result of measurement is renewed every 100 lines.) . *When reading the result of measurement (R32[3:0] / R33[7:0] / R34[7:0]) , please suspend measurement. R32[3:0]/R33[7:0]/R34[7:0] HSYNC Period Measurement Result The period of 100 lines of horizontal period is counted by External REFCLK and the result can be read. The horizontal period and frequency are calculated by the following formula. Horizontal period [us] = Measurement result / (100 * fREFCLK) Horizontal Frequency [kHz] = fREFCLK * 105 / Measurement result * fREFCLK is REFCLK frequency (unit :MHz) *Input a reference clock (7-40MHz) to CLAMP-pin to measure period of Horizontal, and the setting of External REFCLK input should be enabled(R31[1]=1) . *Stop the measurement after more than 20ms(or more than 300 lines) from the start of measurement of horizontal period (R31[0]=1), and read the result(R32[3:0] / R33[7:0] / R34[7:0]) . R35[7] Sync Signal Valid Flag (Event Recorder) 1 is set when HSYNC and VSYNC are detected in input sync. At this point, all the measurement and detection are completed. R35[4] Port-1 Input Sync Type Change Detection (Event Recorder) R35[3] Port-0 Input Sync Type Change Detection (Event Recorder) 1 is set when Port-1 Input Sync Type Detection (R2C[6:5]) , Port-0 Input Sync Type Detection (R2C[4:3]) changes. R35[2] Input Signal Format Change Detection When following even one detection and result of measurement changed, 1 is set HSYNC Input polarity Detection VSYNC Input polarity Detection Vertical Total Line Measurement (Change detection threshod(R37[7:5]) default setting is +/-1 line) VSYNC Input Pulse Width Measurement (Change detection threshold (R37 [4:3]) default setting:+/- 1 line.) HSYNC Period Measurement (Change detection threshold (R37 [2:0]) default setting:+/- 64) *It's possible to detect the switching of seamless input format change of which the input SYNC type doesn't change. R35[1] Input HSYNC Missing Edge Detection (Event Recorder) 1 is set when HSYNC edges are not detected inside the prospective period. The PLL COAST period (R22[6:0]/R23[6:0]) is not the subject of detection. * In case input sync signal includes no pulses during the vertical sync time such as OR-type CSYNC, these missing pulses should be covered by PLL COAST signal. R35[0] Input HSYNC Extraneous Edge Detection (Event Recorder) `1' is read when HSYNC edges are detected outside the prospective period. The PLL COAST period (R22[6:0]/ R23[6:0]) is not the subject of detection. * In case input sync signal includes extraneous pulses such as equalization pulses and copy protection signal during the vertical blank time, these pulses should be covered by PLL COAST signal or eliminated by HSYNC Filter (R1F[4]) . * Event recorders must be cleared by writing 1 to them to start the measurement and detection by them. Copyright(c)2013 THine Electronics, Inc. 39 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E R36[7]/R36[4:0] Sync Processor IRQ Output Enable by Event Recorder 1: When corresponding bit of event recorders R34[5:0] is set to 1, interrupt request is triggered. Interrupt request signal is available from O/E FIELD-pin (R1E[3:1]=011b) . < Sync Processor IRQ Enable > Event Recorder R35[7] R35[6] R35[5] R35[4] R35[3] R35[2] R35[1] R35[0] Event Sync Signal Valid Flag Reserved Reserved Port-1 Input Sync Type Change Detection Port-0 Input Sync Type Change Detection Input Signal Format Change Input HSYNC Missing Edge Detection Input HSYNC Extraneous Edge Detection IRQ Enable R36[7] R36[6] R36[5] R36[4] R36[3] R36[2] R36[1] R36[0] R37[7:5] Input Signal Format Change Detection---Threshold of Vertical Total Line Change Set the change detection threshold of vertical total line for Input Signal Format Change Detection (R35[2]). When the result of vertical total line measurement (R2E[6:0] / R2F[7:0]) change more than this value, R35[2] will be 1. 000b: 0.5 lines 001b: 1 line 010b: 2 lines 011b: 4 lines 100b: 8 lines 101b: 16 lines 110b: 32 lines 111b: Do not observe the change R37[4:3] Input Signal Format Change Detection---Threshold of VSYNC Input Pulse Width Set the change detection threshold of VSYNC Input Pulse Width for Input Signal Format Change Detection (R35[2]). When the result of VSYNC Input Pulse Width measurement (R30[7:0]) change more than this value, R35[2] will be 1. 00b: 0.5 lines 01b: 1 line 10b: 4 lines 11b: Do not observe the change R37[2:0] Input Signal Format Change Detection---Threshold of HSYNC Period Set the change detection threshold of VSYNC Input Pulse Width for Input Signal Format Change Detection (R35[2]). When the result of VSYNC Input Pulse Width measurement (R32[3:0]/R33[7:0]/R34[7:0]) change more than this value, R35[2] will be 1. 000b: 8 001b: 16 010b: 32 011b: 64 100b: 128 101b: 256 110b: 512 111b: Do not observe the change R39[7:2] Reserved *Must be set to 111111b for proper operation (Default value: 111111b) R39[1] SOG Slicer Port 1 (SOGIN1) Power-on R39[0] SOG Slicer Port 0 (SOGIN0) Power-on When the SOG slicer is not used, it's possible to be powered down. When making only SOG slicer Port 1 to be powered down, set R39=FDh When making only SOG slicer Port 0 to be powered down, set R39=FEh When making both of SOG Slicer Port to be powered down, set R39=FCh. *R38 and the registers after R39 are for test purpose. Don't write values to these registers. Copyright(c)2013 THine Electronics, Inc. 40 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Application Example GND VD GND SOGIN0 GND SOGIN1 VD GND 75 10F 10F 10F RAIN1 RST BLUE<2> 61 BLUE<1> 62 VDD BLUE<0> 63 65 64 SDA SCL GND 66 68 67 HSYNC1 VSYNC1 69 VSYNC0 HSYNC0 70 71 72 73 CLAMP PVD 74 PVD GND GND 75 76 77 78 PVD 52 10 THC7984 51 11 Top View 50 BLUE<6> BLUE<7> BLUE<8> BLUE<9> GND VDD GREEN<0> GREEN<1> 13 49 GREEN<2> 48 GREEN<3> 14 47 12 15 16 46 Note1 REFLO 18 REFCM 19 REFHI 20 VDD 10k GREEN<4> GREEN<5> 45 GREEN<6> GREEN<7> 44 GREEN<8> 43 GREEN<9> 42 DAVDD 41 17 Note2 alternative FILT 53 9 BLUE<4> BLUE<5> 32 RED<4> 33 RED<3> 34 RED<2> 35 RED<1> 36 RED<0> 37 VDD 38 GND 39 GND 40 100nF 8 31 75 RAIN0 54 BLUE<3> RED<5> 100nF 55 7 30 1nF 6 RED<6> 75 GAIN1 56 RED<7> 100nF VD 5 29 1nF 57 28 75 GAIN0 58 4 RED<8> 100nF 59 3 27 75 BAIN1 60 2 GND 100nF 1 RED<9> 75 VD BAIN0 O/E FIELD 21 VSOUT/A0 22 HSOUT 23 SOGOUT 24 DATACK 25 VDD 26 100nF 79 80 GND 5.6nF EXTCLK/COAST Note3 PVD 56nF 2.2k 10k Note1. Power-down / Reset - When it is not used, set this pin to low. (e.g., pull-down to GND by a resistor (10kohm) ) . - RST-pin is not made pull-up or pull-down inside of device. Note2. Device address setting Pull-down VSOUT/A0-pin to GND by a resistor (10kohm) : Device address will be 1001100. Pull-up VSOUT/A0-pin to VDD by a resistor (10kohm) : Device address will be 1001101. - In case of pull-up, connect a resistor to VDD. - Don't connect VSOUT/A0-pin to the input pin with bus hold circuit of the subsequent device (Device address can't be acquired properly). - VSOUT-pin is not made pull-up or pull-down inside the device, so please be sure to connect the resistor to this pin. Note3. SYNC Signal Input - The outside circuit should be designed not to apply higher voltage above absolute maximum rating (PVD+3.6v) to the digital input pins when power is not supplied, - Fix the input level when there is no sync signal on the sync input pins (e.g., pull-down to GND by resistor (10kohm) ) . Copyright(c)2013 THine Electronics, Inc. 41 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E Notice about the crosstalk when using 2 ports (Port 0/ Port 1) . Crosstalk of video signal Although the input signal to the non-selected port will give weak noise to the signal on the selected port by crosstalk, it has little influence as long as the signal level is normal. If the input signal to non-selected port is abnormally higher amplitude than normal signals (nominally 1.15V peak to peak from the bottom of the sync to the peak level of copy protection signal) and supply voltage VD is lower (1.7V) than the typical value, the crosstalk may increase and has influence to the selected port. The component video signal on the non-selected port should be muted (output disable) by the video switch or video buffer prior to the device to prevent the crosstalk. * The amplitude of component video signal (YPbPr) with sync and copy protection signal is relatively high. Mute of non-selected port (e.g.) THC7984 port selection selected port RGB (PC input) video switch YPbPr (Component input) non-selected port mute Crosstalk of SOG slicer The SOG slicer extracts a sync signal from Sync-On-Video signal (SOG, SOY). In case that the Input Sync Type of the selected port is Sync-On-Video(2-level) (R12[1:0]=10b) and a signal is inputted to the non-selected port, there is a possibility to have an influence on the clock Jitter by crosstalk. * When the SOG slicer is not used (including YPbPr with separated sync input) , SOG crosstalk doesn't influence on the clock jitter. To prevent crosstalk of the SOG slicer, take one of following countermeasures. 1. SOG slicer of non-selected port should be Power-down When Port 0 is selected (R12[3]=0) : SOG slicer of port 1 should be powered down (R39=FDh) When Port 1 is selected (R12[3]=1) : SOG slicer of port 0 should be powered down (R39=FEh) * The SOG slicer of the port which doesn't support SOG (e.g., PC input) can be powered down and the capacitor (1nF) of the SOG input can be eliminated. 2. The video signal on the non-selected port should be muted (output disable) by the video switch or video buffer prior to the device to prevent the crosstalk. By above countermeasures, the SOG activity detection of the non-selected port can't work and the following function can not be used. SYNC Type Detection of non-selected port (R2C[3:2]/R2C[1:0]) Input port Automatic Selection (R12[5]) Copyright(c)2013 THine Electronics, Inc. 42 / 45 THine Electronics, Inc. THC7984_Rev.2.0_E 2-wire Serial Interface < 2-wire Serial Interface Protocol > Start condition 9 cycle 9 cycle SCL SDA I6 I5 I0 DEVICE ID R/W A R/W ACK D7 D6 D6 D0 REGISTER ADDRESS WRITE DATA READ DATA 9 cycle D7 D1 D0 A D7 D6 D7 ACK Stop condition 9 cycle D1 A D1 D0 ACK A/A ACK -WRITE CYCYLES 0 W A REGISTER ADDRESS A DEVICE ID WRITE DATA A A P -READ CYCYLES DEVICE ID 0 W A REGISTER ADDRESS A S DEVICE ID 1 R A READ DATA A S: Start condition P: Stop condition W: Write (Low) R: Read (High) A: Acknowledge (Low) From Master to THC7984 A P A: Not acknowledge (High) From THC7984 to Master * The THC7984 operates as a slave device. * While SCL is High, SDA must be stable. SDA can change when SCL is Low. (except for start/end conditions) * A SDA High to Low transition when SCL is High defines "Start condition". A SDA Low to High transition when SCL is High defines "Stop condition". * In write or read cycle, whenever data is written or read, the register address (address pointer) is incremented. The address pointer is hold when the write cycle ends. However, The address pointer is undefined when the read cycle ends. * To read the register data, specify a register address by the write cycle, and read the data by read cycle. * Embedded watch dog timer monitors SCL transitions. When SCL stays High more than 39ms (min.) or stays Low more than 19ms (min.) , 2-wire serial interface is reset to initial state (this is different from chip reset) . < 2-wire Serial Interface Timing > VIHmin=1.4V SDA tBUFF tDHO tDSU tSTASU tSTOSU VILmax=0.8V tDAH tSTAH VIHmin=1.4V SCL VILmax=0.8V STOP START Copyright(c)2013 THine Electronics, Inc. tDAL Tf 43 / 45 START STOP THine Electronics, Inc. THC7984_Rev.2.0_E Package Dimension (Unit: mm) 16.00 BSC. 14.00 BSC. 80 61 1 60 14.00 BSC. THC7984 Top View 20 41 21 1.60 Max 16.00 BSC. Mirror Finish 40 0.65 BSC 0.38 0.30 0.22 0 - 7 deg. 1.45 1.40 1.35 Gauge Plane 0.15 0.05 Copyright(c)2013 THine Electronics, Inc. 44 / 45 0.75 0.60 0.45 0.25 THine Electronics, Inc. THC7984_Rev.2.0_E Other Precautions and Requirements 1. The specification in this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay more particular attention to circuit designing. Even if there are improper expressions in the documents, we are not responsible for any problem due to them. Please note that improper expressions may not be corrected immediately even if found. 3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to the third party are strictly prohibited without our permission. 4. We are not responsible for any problem on industrial proprietorship occurring due to the use of the THC7984, except for those directly related to the product structure, manufacturing methods and functions. 5.The THC7984 is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects the human life, etc.) . In addition, when the THC7984 is used for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 6. We are making every effort to improve the quality and reliability of our products. However, a very low probability of failure will occur in semiconductor devices. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 7. Radiation-resistant design is not incorporated in the THC7984. 8. It is due to user's judgement whether or not the THC7984 pertains to one of the strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. sales@thine.co.jp Copyright(c)2013 THine Electronics, Inc. 45 / 45 THine Electronics, Inc.