DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 1 -
1Mx32 DRAM SIMM
Revision 0.0
November 1997
(1MX16 Base)
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 2 -
Revision History
Version 0.0 (November 1997)
• Changed module PCB from 6-Layer to 4-Layer.
• Changed Module Part No. from KMM5321200CW/CWG to KMM5321200C2W/C2WG caused by PCB revision .
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 3 -
KMM5321200C2W/C2WG with Fast Page Mode
1M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V
The Samsung KMM5321200C2W is a 1Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5321200C2W consists of two CMOS 1Mx16bits DRAMs
in 42-pin SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
KMM5321200C2W is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
• Part Identification
- KMM5321200C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5321200C2WG(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(750mil), single sided component
GENERAL DESCRIPTION FEATURES
PERFORMANCE RANGE
Speed tRAC tCAC tRC
-5 50ns 15ns 90ns
-6 60ns 15ns 110ns
PIN NAMES
Pin Name Function
A0 - A9 Address Inputs
DQ0 - DQ31 Data In/Out
WRead/Write Enable
RAS0 Row Address Strobe
CAS0 - CAS3 Column Address Strobe
PD1 -PD4 Presence Detect
Vcc Power(+5V)
Vss Ground
NC No Connection
Res Reserved Pin
PRESENCE DETECT PINS (Optional)
* Pin connection changing available
Pin 50NS 60NS
PD1
PD2
PD3
PD4
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 4 -
FUNCTIONAL BLOCK DIAGRAM
RAS0
W
A0-A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RAS
LCAS
UCAS
OE
WA0-A9
CAS0
CAS1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RAS
LCAS
UCAS
OE
CAS2
CAS3
Vcc
Vss
.1 or .22uF Capacitor
for each DRAM To all DRAMs
U0
U1
WA0-A9
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 5 -
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In I CC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one page mode cycle, tPC.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
Item Symbol Rating Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
Pd
IOS
-1 to +7.0
-1 to +7.0
-55 to +150
2
50
V
V
°C
W
mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC.
*2 : -2.0V/20ns, Pulse width is measured at VSS.
Item Symbol Min Typ Max Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
4.5
0
2.4
-1.0*2
5.0
0
-
-
5.5
0
VCC+1*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
II(L)
IO(L)
VOH
VOL
Symbol Speed KMM5321200C2W/C2WG Unit
Min Max
ICC1 -5
-6 -
-300
280 mA
mA
ICC2 Don′t care -4mA
ICC3 -5
-6 -
-300
280 mA
mA
ICC4 -5
-6 -
-180
160 mA
mA
ICC5 Don′t care -2mA
ICC6 -5
-6 -
-300
280 mA
mA
II(L)
IO(L) Don′t care -10
-5 10
5uA
uA
VOH
VOL Don′t care 2.4
--
0.4 V
V
: Operating Current * (RAS, LCAS or UCAS, Address cycling @tRC=min)
: Standby Current (RAS=LCAS=UCAS=W=VIH)
: RAS Only Refresh Current * (LCAS=UCAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * (RAS=VIL, LCAS or UCAS cycling : tPC=min)
: Standby Current (RAS=LCAS=UCAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0 ≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V ≤VOUT≤Vcc)
: Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (IOL = 4.2mA)
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 6 -
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item Symbol Min Max Unit
Input capacitance[A0-A9]
Input capacitance[W]
Input capacitance[RAS0]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
CIN1
CIN2
CIN3
CIN4
CDQ
-
-
-
-
-
30
30
25
20
20
pF
pF
pF
pF
pF
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter Symbol -5 -6 Unit Note
Min Max Min Max
Random read or write cycle time tRC 90 110 ns
Access time from RAS tRAC 50 60 ns 3,4
Access time from CAS tCAC 15 15 ns 3,4,5
Access time from column address tAA 25 30 ns 3,10
CAS to output in Low-Z tCLZ 0 0 ns 3
Output buffer turn-off delay tOFF 013 015 ns 6
Transition time(rise and fall) tT350 350 ns 2
RAS precharge time tRP 30 40 ns
RAS pulse width tRAS 50 10K 60 10K ns
RAS hold time tRSH 13 15 ns
CAS hold time tCSH 50 60 ns
CAS pulse width tCAS 13 10K 15 10K ns
RAS to CAS delay time tRCD 20 37 20 45 ns 4
RAS to column address delay time tRAD 15 25 15 30 ns 10
CAS to RAS precharge time tCRP 5 5 ns
Row address set-up time tASR 0 0 ns
Row address hold time tRAH 10 10 ns
Column address set-up time tASC 0 0 ns
Column address hold time tCAH 10 10 ns
Column address to RAS lead time tRAL 25 30 ns
Read command set-up time tRCS 0 0 ns
Read command hold referenced to CAS tRCH 0 0 ns 8
Read command hold referenced to RAS tRRH 0 0 ns 8
Write command hold time tWCH 10 10 ns
Write command pulse width tWP 10 10 ns
Write command to RAS lead time tRWL 13 15 ns
Write command to CAS lead time tCWL 13 15 ns
Data-in set-up time tDS 0 0 ns 9
Data-in hold time tDH 10 10 ns 9
Refresh period tREF 16 16 ms
Write command set-up time tWCS 0 0 ns 7
CAS setup time(CAS-before-RAS refresh) tCSR 5 5 ns
CAS hold time(CAS-before-RAS refresh) tCHR 10 10 ns
RAS precharge to CAS hold time tRPC 5 5 ns
Access time from CAS precharge tCPA 30 35 ns 3
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 7 -
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V IH(min) and V IL(max) and are assumed to be 5ns
for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V OH or
VOL.
tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristic s only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameter are referenced to the CAS leading edge in
early write cycles.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
Parameter Symbol -5 -6 Unit Note
Min Max Min Max
Fast page mode cycle time tPC 35 40 ns
CAS precharge time(Fast page cycle) tCP 10 10 ns
RAS pulse width(Fast page cycle) tRASP 50 200K 60 200K ns
W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns
W to RAS hold time(C-B-R refresh) tWRH 10 10 ns
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 8 -
tCRP
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VOH -
VOL -
DQ
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tAA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tRRH tRCH
Don′t care
Undefined
tRCS
tOFF
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 9 -
tWCS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
tWP
tDS tDH
tWCH
tCWL
tRWL
Don′t care
DATA-IN
Undefined
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 10 -
tRCH
tCLZ
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VOH -
VOL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tASC
tRAD
tASR tRAH
tASC
tCAH
tCRP
VALID
Don′t care
FAST PAGE READ CYCLE
tRRH
DATA-OUT
Undefined
VALID
DATA-OUT
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tRCH
¡ó
tRCS tRCStRCS
tCAC tCAC tCAC
VALID
DATA-OUT
tCLZ
tOFF
tAA tOFF
tAA
tCLZ tOFF
tRAC
tAA
tCP
tCAS
tRP
tCP
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 11 -
tASC
tCAH
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VIH -
VIL -
DQ
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tRAD
tASR tRAH
tASC
tCRP
VALID
Don′t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
tDS
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tWCS tWCH
tWCS
VALID
DATA-IN
tWP
tCWL
tWP
tWCH
tWP
tWCS tWCH
tCWL
tRWL
tCWL
tDH tDS tDH tDS tDH
¡ó
¡ó
¡ó
tRP
tCP
tCP
tCAS
tPC
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 12 -
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - ROW
ADDR
tRAS tRC tRP
tASR tRAH
tCRP
Don′t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, OE, DIN = Don't care
DOUT = OPEN
tRPC tCRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don't care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tWRP
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
VOH -
VOL -
DQ OPEN
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 13 -
tWRH
tOFF
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VOH -
VOL -
DQ
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHRtRCD
tRAD
tASR tRAH tASC tCAH
tCRP
tRCS
tAA
tCAC
tCLZ
tRAC
OPEN
tRRH
Don′t care
tRSH
tWRP
Undefined
tRC
DATA-OUT
tRP tRP
tRAS
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 14 -
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
VIH -
VIL -
DQ
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHR
tRCD
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
tRSH
DATA-IN
tWRP
tWRH
Undefined
tRC
NOTE : DOUT = OPEN
tWCH
tWP
tDH
tRPtRP tRAS
tDS
tWCS
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 15 -
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - COLUMN
ADDRESS
tRAS
tRSH
tCHR
tRAL
tCSR tCPT
tRP
tCAS
tASC tCAH
READ CYCLE
VOH -
VOL - DATA-OUT
DQ
tOFF
tCLZ
WRITE CYCLE
VIH -
VIL - DATA-IN
DQ
tDH
tDS
Don′t care
Undefined
tWRP tWRH tRRH
tRCH
tRCS tCAC
tAA
VIH -
VIL -
W
tWRP tWRH
tWCS tWCH
tCWL
VIH -
VIL -
W
tWP
tRWL
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
OPEN
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 16 -
Don′t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRASS tRPS
tRPC
tWRP
tCHS
tRP
tCP
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
OPEN
VOH -
VOL -
DQ
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tRPC
tWTS
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWTH
tOFF
OPEN
VOH -
VOL -
DQ
DRAM MODULE KMM5321200C2W/C2WG
Rev. 0.0 (Nov. 1997)
- 17 -
PACKAGE DIMENSIONS
.133(3.38)
4.250(107.95)
3.984(101.19)
.125(3.17)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
.250(6.35)
Units : Inches (millimeters)
Gold & Solder Plating Lead
.010(.25)MAX
.050(1.27) .041±.004(1.04±.10)
.100(2.54)
MIN
.200(5.08)
MAX
.054(1.37)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 1Mx16 DRAM
DRAM Part No. : KMM5321200C2W/C2WG -- KM416C1200CJ (400 mil)
.750(19.05)
MIN
.400(10.16)
.125 DIA±.002(3.18±.051)
R.062(1.57)
.250(6.35)
.080(2.03)
.047(1.19)
( Back view )
( Front view )
Revision History
Rev 0.0 : Nov. 1997
