PIC16F1934-I/PT - Microchip Technology

PIC16F193X/LF193X

This document includes the

programming specifications for the

following devi ces:

1.0 OVERVIEW

The PIC16F193X and PIC16LF193X devices can be

programmed using either the high-voltage In-Circuit

Serial Programming™ (ICSP™) method or the

low-voltage ICSP™ method.

1.1 Hardware Requir ements

1.1.1 HIGH-VOLTAGE ICSP

PROGRAMMING

In High-Voltage ICSP™ mode, the PIC16F193X and

PIC16LF193X devices require two programmable

power supplies: one for VDD and one for the

MCLR/VPP/RE3 pin.

1.1.2 LOW-VOLTAGE ICSP

PROGRAMMING

In Low-Voltage ICSP™ mode, the PIC16F193X and

PIC16LF193X devices can be programmed using a

single VDD source in the operating range. The

MCLR/VPP/RE3 pin does not have to be brought to a

different voltage, but can instead be left at the normal

operating voltage.

1.1.2.1 Single-Supply ICSP Programming

The LVP bit in Configuration Word 2 enables

single-supply (low-voltage) ICSP programming. The

LVP bit def aul ts to a ‘1’ (enabled) from the f act ory. The

LVP bit may only be progra mm ed to ‘0’ by entering the

High-V o ltage ICS P mode, where M CLR/VPP/RE3 pin is

raised to VIHH. Once the LVP bit is programmed to a ‘0’,

only th e H i gh- Voltage ICSP mode is availab le an d o nl y

the High-Voltage ICSP mode can be used to program

the device.

1.2 Pin Utilization

Five pins are needed for ICSP™ programming. The

pins are listed in Table 1-1.

TABLE 1-1: PIN DE SCR IPTI ONS DU RING PROGR AMMIN G

• PIC16F1933 • PIC16F1934 • PIC16F1936

• PIC16F1937 • PIC16F1938 • PIC16F1939

• PIC16LF1933 • PIC16LF1934 • PIC16LF1936

• PIC16LF1937 • PIC16LF1938 • PIC16LF1939

Note 1: The High-Voltage ICSP mode is always

available, regardless of the state of the

LVP bit, by applying VIHH to the

MCLR/VPP/RE3 pin.

2: While in Low-Voltage ICSP mode, MCLR

is always enabled, regardless of the

MCLRE b it, and RE 3 pin can no longer b e

used as a general purpose input.

Pin Name During Programming

Function Pin Ty pe Pin Description

RB6 ICSPCLK I Clock Input – Schmitt Trigger Input

RB7 ICSPDAT I/O Data Input/Output – Schmitt Trigger Input

RE3/MCLR/VPP Program/V erify mode P(1) Program Mode Select/Programming Power Supply

VDD VDD P Power Supply

VSS VSS P Ground

Legend: I = Input, O = Output, P = Power

Note 1: In the PIC16F193X/LF193X, the programming high voltage is internally generated. To activate the Program/Verify

mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not

draw any significant current.

PIC16F193X/LF193X Memory Pr ogramming Specification

PIC16F193X/LF193X

Table of Contents

1.0 Overview ..................................................................................................................................................................................... 1

1.1 Hardware Requirements ................................................................. ...... ............... ...... .......... ................................................... 1

1.1.1 High-Voltage ICSP Programm ing ................................................................................................................................ 1

1.1.2 Low-Voltage ICSP Programming ........................ ........... ..................... .......... ....... .......... .......... .................................... 1

1.2 Pin Utilization .......................................................................................................................................................................... 1

2.0 Device Pinouts ............................................................................................................................................................................ 3

3.0 Memory Map ............................................................................................................................................................................... 8

3.1 User ID Loc a tion ............................................................ ....... ..................... ...... ....................................................................... 9

3.2 Device ID ............ .......................................... ....... .......... ....... ..................... ...... ....................................................................... 9

3.3 Configuration Words ............................................................................................................................................................. 10

3.4 Calib ration Words .......................................................................................................... ....................................................... 10

4.0 Prog ram/Verify Mode ................................................................................................................................................................ 13

4.1 High Voltage Program/Verify Mode Entry and Exit ..................... .... ...... ........... ...... .... ............. .... ...... . ................................... 13

4.1.1 VPP – First Entry Mode .... ........................................................................................................................................... 13

4.1.2 VDD – First Entry Mode .............................................................................................................................................. 13

4.1.3 Program/Verify Mode Exit .............. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .......................................... 13

4.2 Low-Voltage Programming (LVP) Mode ...................................................................... ............. ............................................ 13

4.3 Program/Verify Commands . .................................................................................................................................................. 14

4.3.1 Load Configuration . .................................................................................................................................................... 15

4.3.2 Load Data For Program Memory ............................................................................................................................... 15

4.3.3 Load Data For Data Memory . ..................................................................................................................................... 16

4.3.4 Read Data From Pro g ram Memory .............................................. ....... ..................... ...... ............................................ 16

4.3.5 Read Data From Data Memor y .......... ...................................................................... .................................................. 17

4.3.6 Increment Ad d ress .. ..................... ........... ...... .......... ........... ...... ........... .......... ....... ......... ............................................. 17

4.3.7 Reset Address ............................................................................................................................................................ 18

4.3.8 Begin Interna lly Timed Programmin g ........ ............................................................................... .................................. 18

4.3.9 Begin Ext ern a l ly Timed Programming ........................ ...... ..................... ...... ..................... ...... .................................... 19

4.3.1 0 End Exter n ally Timed Prog ramming .............................. ...... ........... ...... ..................... ...... .......................................... 19

4.3.11 Bulk Erase Program Memory ..................................................................................................................................... 20

4.3.1 2 Bulk Erase Data Memory ......... ......................................................................... ....... .................................................. 20

4.3.13 Row Erase Program Memory ..................................................................................................................................... 21

5.0 Progra mming Al g o rithms .......... ..................... ....... .......... ........... ...... .......... ....... .......... ............................................................... 22

6.0 Code Protect ion ......................................................................................................................................................................... 30

6.1 Prog ram Memory .................................................................................. ....... .................... ..................................................... 30

6.2 Data Memory ...... ........... ...... ........... ...... ..................... ...... ..................... ....... ......................................................................... 30

7.0 Hex File Usage .......................................................................................................................................................................... 30

7.1 Configuration Word ............................................................................................................................................................... 30

7.2 Device ID and Revision ...... ........... ...... .................................................................................................................................. 30

7.3 Data EEPROM ......... .......... ........... ...... .......... ....... .......... ........... ...... ........... ...... .......... ........................................................... 30

7.4 Che ck sum Computat io n ......... ............................................................................................................................................... 31

7.4.1 Code Prote ction Disabl e d ...... .......... ..................... ....... ..................... ...... ..................... ..... ......................................... 31

7.4.2 Code Protection Enabled .............................. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .... .. .. ....... .... .. ............................................ 32

8.0 Electrical Specifications ...................................................................................................... . ...... .. ...... ...... ..... .. ...... ...... .. ..... ...... .. 33

8.1 AC Timin g Diagr a ms .... ..................... ...... .......................................... ...... .............................................................................. 34

PIC16F193X/LF193X

2.0 DEVICE PINOUTS

The pin diagrams for the PIC16F193X/PIC16LF193X

family are show n in Figu re 2-1 thr ough Fig ure 2-5. The

pins that are required for programming are listed in

Table 1-1 and shown in bold lettering in the pin

diagrams.

FIGURE 2-1: 28-PIN PDIP/SOIC/SSOP DIAGRAM FOR PIC16F1933/1936/1938 AND

PIC16LF1933/1936/1938

FIGURE 2-2: 28-PIN QFN PACKAGE DIAGRAM FOR PIC16F1933/1936/1938 AND

PIC16LF1933/1936/1938

28-pin SPDIP, SOIC, SSOP

PIC16F1933/1936/1938

PIC16LF1933/1936/1938

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6/ICSPCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

14 15

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7/ICSPDAT

716

RC0

RB7/ICSPDAT

RB6/ICSPCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC7

RC6

RC5

RC4

RE3/MCLR/VPP

RA0

RA1

RA2

RA3

RA4

RA5

VSS

RA7

RA6

RC1

RC2

RC3

PIC16F1933/1936/1938

PIC16LF1933/1936/1938

28-pin QF N

PIC16F193X/LF193X

FIGURE 2-3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND

PIC16LF1934/1937/1939

FIGURE 2-4: 44-PIN QFN PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND

PIC16LF1934/1937/1939

PIC16F1934/1937/1939

PIC16LF1934/1937/1939

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

RB6/ICSPCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RD2

VDD

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD0

RD1

RC5

RC4

RD3

RD4

RC7

RC6

RD7

RD6

RD5

RB7/ICSPDAT

40-pin PDIP

RA1

RA0

VPP/MCLR/RE3

RB3

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4

NC RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

RC0

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

44-pin QFN

PIC16F1934/1937/1939

PIC16LF1934/1937/1939

RA3

RA2

PIC16F193X/LF193X

FIGURE 2-5: 44-PIN TQFP PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND

PIC16LF1934/1937/1939

44-pin TQFP

RA3

RA2

RA1

RA0

VPP/MCLR/RE3

ICSPDAT/RB7

ICSPCLK/RB6

RB5

RB4

RC0

VSS

VDD

RB0

RB1

RB2

RB3

4PIC16F1934/1937/1939

PIC16LF1934/1937/1939

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

RC6

RC5

RC4

RD3

RD2

RD1

RD0

RC3

RC2

RC1

PIC16F193X/LF193X

3.0 MEMORY MAP

The memory for the PIC16F193X/LF193X devices is

broken into two sections: program memory and

configuration memory. Only the size of the program

memory changes between devices, the configuration

memor y remains the same.

FIGURE 3-1: PIC16F1933/PIC16LF1933, PIC16F1934/PIC16LF1934 PROGRAM MEMORY

MAPPING

7FFF

8000

8200

FFFF

Implemented

4 KW

Implemented

0FFF

Maps to

0-0FFF

Maps to

Program Memory

Configuration Memory

8000-81FF

User ID Location

Reserved

Device ID

Configuration Word 1

Configuration Word 2

Calibration Word 1

Calibration Word 2

Reserved

8000h

8001h

8002h

8003h

8004h

8005h

8006h

8007h

8009h

8008h

800Ah

800Bh-81FFh

0000h

PIC16F193X/LF193X

FIGURE 3-2: PIC16F1936/PIC16LF1936, PIC16F1937/PIC16LF1937 PROGRAM MEMORY

MAPPING

7FFF

8000

8200

FFFF

Implemented

8 KW

Implemented

1FFF

Maps to

0-1FFF

Maps to

Program Memory

Configuration Memory

8000-81FF

User ID Location

Reserved

Device ID

Configuration Word 1

Configuration Word 2

Calibration Word 1

Calibration Word 2

Reserved

8000h

8001h

8002h

8003h

8004h

8005h

8006h

8007h

800Ah

8008h

800Bh-81FFh

8009h

0000

PIC16F193X/LF193X

FIGURE 3- 3 : PIC16F 19 38/PIC1 6LF 1938, PIC16F1939/PIC16LF1939 PR OGRAM ME MORY

MAPPING

7FFF

8000

8200

FFFF

16 KW

Implemented

Maps to

Program Memory

Configuration Memory

8000-81FF

User ID Location

Reserved

Device ID

Configuration Word 1

Configuration Word 2

Calibration Word 1

Calibration Word 2

Reserved

8000h

8001h

8002h

8003h

8004h

8005h

8006h

8007h

8009h

8008h

800Ah

Implemented

800Bh-81FFh

0000

3FFF

Maps to

0-3FFF

PIC16F193X/LF193X

3.1 User ID Location

A user may store identification information (user ID) in

four designated locations. The user ID locations are

mapped to 8000h-8003h. Each location is 14 bits in

length. Code protection has no effect on these memory

locations. Each location may be read with code

protection enabled or disabled.

3.2 Device ID

The device ID word for the PIC16F193X/LF193X is

located at 8006h. This location i s read-only and can not

be erased or modified.

TABLE 3-1: DEVICE ID VALUES

Note: MPLAB® IDE only displays the 7 Least

Significant bits (LSb) of each user ID

location, the upper bits are not read. It is

recommended that only the 7 LSb’s be

used if MPLAB IDE is the primary tool

used to read these addresses.

R-q R-q R-q R-q R-q R-q R-q

DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 DEV2

bit 13 bit 7

R-q R-q R-q R-q R-q R-q R-q

DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 6 bit 0

Legend: P = Programmable bit U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit ‘0’ = Bit is cleared

-n = Va lue at POR ‘1’ = Bit is set x = Bit is unknown

bit 13-5 DEV<8:0>: Device ID bits

These bits are used to identify the part number.

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision.

Note 1: This location cannot be written.

DEVICE DEVICE ID VALUES

DEV REV

PIC16F1933 10 0011 001 x xxxx

PIC16F1934 10 0011 010 x xxxx

PIC16F1936 10 0011 011 x xxxx

PIC16F1937 10 0011 100 x xxxx

PIC16F1938 10 0011 101 x xxxx

PIC16F1939 10 0011 110 x xxxx

PIC16LF1933 10 0100 001 x xxxx

PIC16LF1934 10 0100 010 x xxxx

PIC16LF1936 10 0100 011 x xxxx

PIC16LF1937 10 0100 100 x xxxx

PIC16LF1938 10 0100 101 x xxxx

PIC16LF1939 10 0100 110 x xxxx

PIC16F193X/LF193X

3.3 Configuration Words

The PIC16F193X/PIC 16LF193X has two Configurat ion

Words, Configuration Word 1 (8007h) and Configuration

Word 2 (8008h). The individual bits within these

Configuration Words are used to enable or disable

device functions such as the Brown-out Reset, code

protection and Power-up Timer.

3.4 Calibration Words

For the PIC16F193X/PIC16LF193X devices, the

internal calibration values are factory calibrated and

stored in Calibration Words 1 and 2 (8009h and

800Ah).

The Calibration Words do not participate in erase

operat ions. The de vice can be erase d wit hout af fec ting

the Calibration Words.

PIC16F193X/LF193X

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CP

bit 13 bit 7

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0

bit 6 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bi t W = Writable bit ‘0’ = Bit i s cl eared

-n = Value at POR ‘1’ = Bit is set x = Bit is unk nown

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabl ed

0 = Fail-Safe Clock Monitor is disabled

bit 12 IESO: Inte r n al Extern a l Switc h over bit

1 = Internal/External Switchover mode is enabled

0 = Internal/External Switchov er mode is disabled

bit 11 CLKOUTEN: Clock Out Enable bit

1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT

0 = CLKOUT f unction is enabled on RA6/CLKOUT

bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)

11 = BOR enabled

10 = BOR enabled during operation and disabled in Sleep

01 = BOR controlled by SBOREN bit of the PCON register

00 = BOR disabled

bit 8 CPD: Data C od e Pr otec tion bit(2)

1 = Data memory code protect i on is disabled

0 = Data memory code prote ct i on is enable d

bit 7 CP: Code Protectio n bit(3)

1 = Program memory code protection is disabled

0 = Program memory code protection is enabled

bit 6 MCLRE: RE3/MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1 =RE3/MCLR

/VPP pin function is MCLR; Weak pull-up enabled.

0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit.

bit 5 PWRTE: Power-up Timer Enable bit (1)

1 = PWRT disabled

0 = PWR T enabled

bit 4-3 WDTE<1:0>: W atchdog Timer Enable bit

11 = WDT enabled

10 = WDT enabled while running and disabled in Sleep.

01 = WDT controlled by the SWDTEN bit in the WDTCON regist er

00 = W D T di sa bled

bit 2-0 FOSC<2:0>: O scillator Selection bits

111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN

110 = ECM: External Clock, Medium-Power mode: CLKI N on RA7/OSC1/C LKIN

101 = ECL: External Clock , Low-Power mode: CLKIN on RA7/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN

011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN

010 = HS oscillat or: High-speed c rystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/C LKIN

001 = XT oscillator: Cryst al/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN

000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1 /CLKIN

Note 1: Enabling Brown-out Reset does not automatically en able Power-up Timer.

2: The entire data EEPROM will be erased when the code protecti on is turned off during an erase.

3: The entire pro gram memory will be erased when the code protection is turned off.

PIC16F193X/LF193X

R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1

LVP DEBUG — BORV STVREN PLLEN —

bit 13 bit 7

U-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1

— VCAPEN1 VCAPEN0 ——WRT1WRT0

bit 6 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit ‘0’ = Bit is cleared

-n = Va lue at POR ‘1’ = Bit is set x = Bit is unknown

bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled

0 = HV on MCLR/VPP must be used for programming.

bit 12 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins

0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger

bit 11 Unimplemented: Read as ‘1’

bit 10 BORV: Brown-out Reset Voltage Selection bit

1 = Brown-out Reset voltage set to 1.9V

0 = Brown-out Reset voltage set to 2.7V

bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack overflow or underflow will cause a Reset

0 = Stack overflow or underflow will not cause a Reset

bit 8 PLLEN: PLL Enable bit

1 = 4xPLL enabled

0 = 4xPLL disabled

bit 7-6 Unimplemented: Read as ‘1’

bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits(2)

00 =VCAP functionality is enabled on RA0.

01 =V

CAP functionality is enabled on RA5.

10 =V

CAP functionality is enabled on RA6.

11 = No capacitor on VCAP pin.

bit 3-2 Unimplemented: Read as ‘1’

bit 1-0 WRT<1:0>: Flash memory self-write protection bits

4 kW FLASH memory (PIC16F1933/PIC16LF1933 and PIC16F1934/PIC16LF1934 only):

11 = Write protection off

10 = 000h to 1FFh write protected, 200h to FFFh may be modified by EECON control

01 = 000h to 7FFh write protected, 800h to FFFh may be modified by EECON control

00 = 000h to FFFh write protected, no addresses may be modified by EECON control

8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only):

11 = Write protection off

10 = 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control

01 = 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control

00 = 000h to 1FFFh write protected, no addresses may be modified by EECON control

16 kW FLASH memory (PIC16F1938/PIC16LF1938 and PIC16F1939/PIC16LF1939 only):

11 = Write protection off

10 = 000h to 1FFh write protected, 200h to 3FFFh may be modified by EECON control

01 = 000h to 1FFFh write protected, 2000h to 3FFFh may be modified by EECON control

00 = 000h to 3FFFh write protected, no addresses may be modified by EECON control

Note 1: The LV P bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: Reads as ‘11’ on PIC16LF193X only.

PIC16F193X/LF193X

4.0 PROGRAM/VERIFY MODE

In Program/V erify mode, the program memory and the

configuration memory can be accessed and pro-

grammed in serial fashion. ICSPDAT and ICSPCLK

are used for the data and the clock, respectively. All

commands and data words are transmitted LSb first.

Data changes on the rising edge of the ICSPCLK and

latched on the falling edge. In Program/Verify mode

both the IC SPDAT and I CSPC LK are Schmi tt Trigger

inputs. The sequence that enters the device into

Program/Verify mode places all other logic into the

Reset state. Upon entering Program/Verify mode, all

I/O’s are automatically configured as high-impedance

inputs and the addre ss is cle ar ed.

4.1 High-V oltage Program/Verify Mode

Entry and Exit

There are two different methods of entering

Prog ram/Verify mode via high-vol tage:

•V

PP – First entry mode

•VDD – First entry mode

4.1.1 VPP – FIRST ENTRY MODE

To enter Program/Verify mode via the VPP-fi r st metho d

the following sequence must be followed:

1. Hold ICSPCLK and ICSPD AT low . All oth er pins

should be unpowered.

2. Raise the voltage on MCLR from 0V to V IHH.

3. Raise the voltage on VDD FROM 0V to the

desired operating voltage.

The VPP-first en tr y p rev en ts t he de vi ce fr om exe cu ti ng

code prior to entering Program/Verify mode. For

example, when the Configuration Word has MCLR

disabled (MCLRE = 0), the power-up time is disabled

(PWRTE =0), the internal oscillator is selected

(FOSC =100), and RB 6 and RB7 a re driven by the user

application, the device will execute code. Since this

may prevent entry, VPP-first entry mode is strongly

recommended. See the timing diagram in Figure 8-3.

4.1.2 VDD – FIRST ENTRY MODE

To enter Program/ Verify mode via the VDD-fir st method

the following sequence must be followed:

1. Hold ICSPCLK and ICSPDAT low.

2. Raise t he volta ge on VDD from 0 V to the desire d

operating voltage.

3. Raise the voltage on MCLR from VDD or below

to VIHH.

The VDD-first method is useful when programming the

devi ce when VDD is alread y a pp lied, for it is not neces-

sary to disconnect VDD to enter Program/Verify mode.

See the timing diagram in Figure 8-2.

4.1.3 PROGRAM/VERIFY MODE EXIT

To exit Program/Verify mode take MCLR to VDD or

lower (VIL). See Figures 8-4 and 8-5.

4.2 Low-Voltage Programming (LVP)

Mode

The Low-Voltage Programming mode allows the

PIC16F1 93X/LF193X devi ces to be prog rammed using

VDD only, without hi gh vol tag e. When the LVP bit of the

Configuration Word 2 register is set to '1', the

low-voltage ICSP programming entry is enabled. To

disable the Low-Voltage ICSP mode, the LVP bit must

be programmed to '0'. This can only be done while in

the High-Voltage Entry mode.

Entry into the Low-V oltage ICSP Program/V erify modes

requires the following steps:

1. MCLR is brought to VIL.

2. A 32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

The key sequence is a specific 32-bit pattern, '0100

1101 0100 0011 0100 1000 0101 0000' (more

easily remembered a s MCHP in ASCII). T he device will

enter Program/Verify mode only if the sequence is

valid. The Least Significant bit of the Least Significant

nibble must be shifted in first.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mo de is to be

maintained.

For low-voltage programming timing, see Figures 8-9

and 8-10.

Exiting Program/Verify mode is done by no longer

driving MCLR to VIL. See Figures 8-9 and 8-10.

PIC16F193X/LF193X

4.3 Program/Verify Commands

The PIC16F193X and PIC16LF193X implement 13

programming commands, each six bits in length. The

commands are summarized in Table 4-1.

Commands that have data associated with them are

specified to have a minimum delay of TDLY between the

command and the data. After this delay 16 clocks are

required to either clock in or clock out the 14-bit data

word. Th e first clock i s for the S t art bit and th e last cloc k

is for the Stop bit.

TABLE 4-1: COMMAND MAPPING FOR PIC16F193X/LF193X

Command Mapping Data/Note

Binary (MSb … LSb) Hex

Load Configuration x0000000h 0, data (14), 0

Load Data For Program Memory x0001002h 0, data (14), 0

Load Data For Data Memory x0001103h 0, data (8), zero (6), 0

Read Data From Program Memory x0010004h 0, data (14), 0

Read Data From Data Memory x0010105h 0, data (8), zero (6), 0

Inc rement Address x0011006h —

Reset Address x1011016h —

Begin Internally Timed Programming x0100008h —

Begin Extern all y Timed Programmi ng x1100018h —

End Externally Timed Programming x010100Ah —

Bulk Erase Prog ram Memory x0100109h Internally Timed

Bulk Erase Data Memory x010110Bh Internally Timed

Row Era se Prog ram Memory x1000111h Internally Timed

PIC16F193X/LF193X

4.3.1 LOAD CONFIGURATION

The Load Configuration command is used to access

the configuration memory (User ID Locations,

Configuration Words, Calibration Words). The Load

Config uration c ommand se ts the addre ss to 8000h and

loads the data latches with one word of data (see

Figure 4-1).

Aft er issuing the Load Configurat ion command , use the

Increment Address command until the proper address

to be program med is reached. The address is then pro-

grammed by issuing either the Begin Internally Timed

Programming or Begin Externally Timed Programming

command.

The only way to get back to the program memory

(address 0) is to exit Program/Verify mode or issue the

Reset Address command after the configuration memory

has been accessed by the Load Configuration command.

FIGURE 4-1: LOAD CONFIGURATION

4.3.2 LOAD DATA FOR PROGRAM

MEMORY

The Load Da ta for Progra m Memo ry comm and is use d

to load one 14-b it w ord into t he da t a la tc hes . The word

programs into program memory after the Begin

Internally Timed Programming or Begin Externally

Timed Programming command is issued (see

Figure 4-2).

FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY

00LSb MSb 0

123 4561215 16

ICSPCLK

ICSPDAT 0000

TDLY

ICSPCLK

ICSPDAT

12345612 15 16

X00

LSb MSb 0

0100

TDLY

PIC16F193X/LF193X

4.3.3 LOAD DATA FOR DATA MEMORY

The Load D ata for Data Memory command will load a

14-bit “data word” when 16 cycles are applied.

Howeve r , th e dat a memo ry is only 8 bit s wide a nd thus,

only the first 8 bits of data after the Start bit will be

prog ram me d i nt o the da ta m em ory. I t is stil l ne ce ss ary

to cycl e the clo ck the fu ll 16 cy cles in order to al low the

internal circuitry to reset properly (see Figure 4-3).

FIGURE 4-3: LOAD DATA FOR DATA MEMORY COMMAND

4.3.4 READ DATA FROM PROGRAM

MEMORY

The Read Data from Program Memory command will

transmit data bits out of the program memory map

currently accessed, starting with the second rising edge

of the clock input. The ICSPDAT pin will go into Output

mode on th e f ir st fa llin g cl ock edg e, and it w ill re ve rt to

Input mode (high-impedance) after the 16th falling edge

of the clock. If the progr am memory is code-pro tected

(CP), the data will be read as zeros (see Fig ure 4-4).

FIGURE 4-4: READ DATA FROM PROGRAM MEMORY

ICSPCLK

ICSPDAT

123 4561215 16

00LSb MSb 0

1100

TDLY

1 2 3 4 5 6 1 2 15 16

LSb MSb

TDLY

ICSPCLK

ICSPDAT

Input Input

Output

(from Programmer)

0010

ICSPDAT

(from device)

PIC16F193X/LF193X

4.3.5 READ DATA FROM DATA MEMORY

The Read Data from Data Memory command will

transmit data bits out of the data memory starting with

the second rising edge of the clock input. The ICS PDA T

pin w ill g o into Outp ut mo de on the se con d risi ng ed ge,

and it will revert to Input mode (high-impedance) after

the 16th rising edge. The data memory is 8 bits wide,

and therefore, only the first 8 bits that are output are

actual data. If th e data memo ry is code -protecte d, the

data is read as all zeros. A timing diagram of this

command is shown in Figure 4-5.

FIGURE 4-5: READ DATA FROM DATA MEMORY COMMAND

4.3.6 INCREMENT ADDRESS

The address is incremented when this command is

received. It is not possible to decrement the address.

To reset this counter, the user must use the Reset

Address command or exit Program/Verify mode and

re-enter it.

If the address is incremented from address 7FFFh, it

will wrap around to location 0000h. If the address is

increm ented from FFFFh, it will wrap around to location

8000h.

FIGURE 4-6: INCREMENT ADDRESS

1 2 3 4 5 6 1 2 15 16

LSb MSb

TDLY

ICSPCLK

ICSPDAT

Input Input

Output

(from Programmer)

1010

ICSPDAT

(from device)

12345612

ICSPCLK

ICSPDAT 011

XXX

TDLY

Next Command

Address + 1

Address

PIC16F193X/LF193X

4.3.7 RESET ADDR ES S

The Reset Address command will reset the address to

0000h, regardless of the current value. The address is

use d in program memory or t he conf igur atio n memory.

FIGURE 4-7: RESET ADDRESS

4.3.8 BEGIN INTERNALLY TIMED

PROGRAMMING

A Load Configuration or Load Data for Program

Memory command must be given before every Begin

Programming command. Programming of the

addressed memory will begin after this command is

received. An internal timing mechanism executes the

write. The user must allow for the program cycle time,

TPINT, for the programming to complete.

The End Externally Timed Programming command is

not needed when the Begin Internally Timed

Programming is used to start the programming.

The program memory address that is being

programmed is not erased prior to bei ng pr ogrammed.

However, the EEPROM memory address that is being

programm ed is era sed pri or to be ing pro gram med w i th

internally timed programming.

FIGURE 4-8: BEGIN INTERNALLY TIMED PROGRAMMING

123 45612

ICSPCLK

ICSPDAT 011

XXX

TDLY

Next Command

0000h

Address

12345612

ICSPCLK

ICSPDAT

TPINT

000XXX

Next Command

PIC16F193X/LF193X

4.3.9 BEGIN EXTERNALLY TIMED

PROGRAMMING

A Load Configuration, Load Data for Program Memory

or Load Dat a for Data Memory command must be given

before every Begin Programming command. Program-

ming of the addressed memory will begin after this

command is received. To complete the programming

the End Externally Timed Programming command

must be sent in the specified time window defined by

TPEXT. No internal erase is performed for the data

EEPROM, therefore, the de vice sh ould be e rased prior

to executing this command.

The Begin Externally Timed Programming command

can not be used for programming the Configuration

Words (see Figure 4-9).

FIGURE 4-9: BEGIN EXTERNALLY TIMED PROGRAMMING

4.3.10 END EXTERNALLY TIMED

PROGRAMMING

This command is required after a Begin Externally

Timed Programming command is given. This com-

mand mu st be sent within the tim e window s pecified b y

TPEXT after the Begin Externally Timed Programming

comma nd is sent.

After sending the End Externally Timed Programming

comma nd, an addit ional delay (TDIS) is required before

sending the next command. This delay is longer than

the dela y ordinarily requi red between oth er c om m and s

(see Figure 4-10).

FIGURE 4-10: END EXTERNALLY TIMED PROGRAMMING

123 45612

ICSPCLK

ICSPDAT 000110

End Externally Timed Programming

Command

TPEXT 3

123 4561

ICSPCLK

ICSPDAT

TDIS

010XXX

Next Command

PIC16F193X/LF193X

4.3.11 BULK ERASE PROGRAM MEMORY

The Bulk Erase Program Memory command performs

two different functions dependent on the current state

of the address.

A Bulk Erase Program Memory command should not

be issued when the address is greater than 8008h.

After receivin g the Bulk Erase P rogram M emory com-

mand the e rase will not complete un til the ti me interva l,

TERAB, has expired.

FIGURE 4-11: BULK ERASE PROGRAM MEMORY

4.3.12 BULK ERASE DA TA MEMORY

To perform an erase of the data memory, after a Bulk

Erase Data Memory command, wait a minimum of

TERAB to complete Bulk Erase.

To erase dat a memory when d ata code-protect is active

(CPD = 0), the Bulk Erase Pro gram Mem ory comm and

should be used.

Aft er receiving the Bulk Erase Data Memory command,

the erase will not complete until the time interval,

TERAB, has expired.

FIGURE 4-12: BULK ERASE DATA MEMORY COMMAND

Address 0000h-7FFFh:

Program Memory is eras ed

Configuration words are erased

If CPD = 0, Data Memory is erased

Address 8000h-8008h:

Program Memory is eras ed

Configuration Words are erased

User ID Locations are erased

If CPD = 0, Data Memory is erased

Note: The co de protection C onfiguration bit (CP)

has no effect on the Bulk Erase Program

Memory command.

123 45612

ICSPCLK

ICSPDAT

TERAB

100XXX

Next Command

Note: Data memory will not erase if

code-protected (CPD = 0).

123456 12

XX1

TERAB

ICSPCLK

ICSPDAT 11 0

Next Command

Wait a minimum of

PIC16F193X/LF193X

4.3.13 ROW ERASE PROGRAM MEMORY

The Row Erase Program Memory command will erase

an indiv idual row . A r ow of program memory consis ts of

32 conse cutive 14-bit words. A row is addres sed by the

address PC<15:5>. If the program memory is

code-protected the Row Erase Program Memory

command will be ignored. When the address is

8000h-8008h the Row Erase Program Memory com-

mand wil l only erase the user ID loc ations regardles s of

the setting of the CP Configuration bit.

After receiving the Row Erase Program Memory

command the erase will not complete until the time

interval, TERAR, has expired.

FIGURE 4-13: ROW ERASE PROGRAM MEMORY

12345612

ICSPCLK

ICSPDAT

TERAR

100XXX

Next Command

PIC16F193X/LF193X

5.0 PROGRAMMING ALGORITHMS

The PIC16F193X/PIC16LF193X devices have the

capability of storing eight 14-bit words in its data

latches. The data latches are internal to the

PIC16F1 93X/PIC16L F193X devices and are only used

for programming. The data latches allow the user to

program u p to eigh t program words with a single Begin

Externally Timed Programming or Begin Internally

Timed Programming command. The Load Program

Data or the Load Configuration command is used to

load a single data latch. The data latch will hold the

data until the Begin Externally Timed Programming or

Begin Internally Timed Programming command is

given.

The data latches are aligned with the 3 LSb of the

address. The address at the time the Begin Externally

Timed Programming or Begin Internally Timed Pro-

gramming command is given will determine which loca-

tion(s) in memory are written. Writes can not cross a

physic al eight-word bou ndary . For exam ple, attemptin g

to write from address 0002h-0009h will result in data

being written to 0008h-000Fh.

If more than 8 data latches are written without a Begin

Externally Timed Programming or Begin Internally

Timed Programming command the data in the data

latches will be overwritten. The following figures show

the recommended flowcharts for programming.

PIC16F193X/LF193X

FIGUR E 5-1: DEVICE PROGRAM/VERIFY FLOWCHART

Done

Start

Bul k Erase

Device

Write User IDs

Enter

Programming Mode

Write Program

Memory(1)

Verify User IDs

Write Configuration

Words(2)

Verify Configuration

Words

Exit Programming

Mode

Write Data

Memory(3)

Verify D a ta

Memory

Verif y Progr a m

Memory

Note 1: See Figure 5-2.

2: See Figure 5-5.

3: See Figure 5-6.

PIC16F193X/LF193X

FIGURE 5-2: PROGRAM MEMORY FLOWCHART

Start

Read Data

Program Memory

Data Correct?

Report

Programming

Failure

All Locations

Done?

Increment

Address

Command

from

Bulk Erase

Program

Yes

Memory(1, 2)

Done

Yes

Note 1: This step is optional if device has already been eras ed or has not been previously programmed.

2: If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 5-8.

3: See Figure 5-3 or Figure 5-4.

Program Cycle

(3)

PIC16F193X/LF193X

FIGURE 5-3: ONE-WORD PROGRAM CYCLE

Begin

Programming

Wait T DIS

Load Data

for

Program Memor y

Command

(Internally timed)

Begin

Programming

Wait TPEXT

Command

(Externally timed)

End

Programming

Wait TPINT

Program Cycle

Command

PIC16F193X/LF193X

FIGURE 5-4: MULTIPLE-W ORD PR OGRAM CYCLE

Begin

Programming

Wait T PINT

Load Data

for

Program Memory

Command

(Internally timed)

Wait TPEXT

End

Programming

Wait TDIS

Load Data

for

Program Memory

Increment

Address

Command

Load Data

for

Program Memory

Begin

Programming

Command

(Externally timed)

Latch 1

Latch 2

Latch 8

Increment

Address

Command

Program Cycle

Command

PIC16F193X/LF193X

FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART

Start

Load

Configuration

Program Cycle (2)

Read Data

Memory Command

Data Correct? Report

Programming

Failure

Address =

8004h?

Data Correct? Report

Programming

Failure

Yes

Increment

Address

Command

No Increment

Address

Command

Done

One-word

Program Cycle(2)

(Config. Word 1)

Increment

Address

Command

Increment

Address

Command

(User ID)

From Program

Read Data

Memory Comm and

From Program

Program

Bulk Erase

Memory(1)

Data Correct? Report

Programming

Failure

Yes

One-word

Program Cycle(2)

(Config. Word 2)

Increment

Address

Command

Read Data

Memory Command

From Program

Note 1: This step is optional if device is erased or not previously programmed.

2: See Figure 5-3.

PIC16F193X/LF193X

FIGURE 5-6: DATA MEMORY PROGRAM FLOWCHART

Start

Data

Data Correct? Report

Programming

Failure

All Locations

Done?

Increment

Address

Command

Yes

Done

Bulk Erase

Data Memory

Read Data

Memory Command

From D a ta

Program Cycle(1)

Note 1: See Figure 5-7.

PIC16F193X/LF193X

FIGU RE 5-7: DAT A ME MORY PROGR AM CYCL E

FIGURE 5-8: ERASE FLOWCHART

Begin

Programming

Wa it TPINT

Program Cycle

Load Data

for

Data Memory

Command

(Internally timed)

Begin

Programming

Wait T PEXT

Command

(Externally timed)

End

Programming

Wait TDIS

Command

Start

Load Configuration

Done

Bulk Erase

Program Memory

Bul k Erase

Data Memory

Note: This sequenc e does not erase the Calibration Words.

PIC16F193X/LF193X

6.0 CODE PROTECTION

Code protection is controlled using the CP bit in

Configuration Word 1. When code protection is

enabled , all p rogram me mory loca tions (00 00h-7FFFh)

read as all ‘0’. Further programming is disabled for the

program me mory (0000h-7FFFh).

Data memory is protected with its own Code-Protect bit

(CPD). When data code-protection is enabled (CPD =0),

all data memory locations read as ‘0’. Further

programming is disabled for the data memory. Data

memory can still be programmed and read during

prog ram ex ecut ion.

The user ID locations and Configuration Words can be

programmed and read out regardless of the code

prote cti on set tin gs.

6.1 Program Memory

Code prot ec tion is ena bl ed by progra mm in g the CP bit

in Configuration Word 1 re gister to ‘0’.

The only way to disable code protection is to use the

Bulk Erase Program Memory command.

6.2 Data Memory

Data memory protection is enabled by programming

the CPD bit in Configuration Word 1 register to ‘0’.

The only way to disable code protection is to use the

Bulk Erase Program Memory command.

7.0 HEX FILE USAGE

In the hex file there are two bytes per program word

stored in the Intel® INHX32 hex format. Data is stored

LSB first, MSB second. Because there are two bytes

per word, the addresses in the hex file are 2x the

address in program memory. (Example: The

Configuration Word 1 is stored at 8007h on the

PIC16F193X/PIC16LF193X. In the hex file this will be

referenced as 1000Eh-1000Fh).

7.1 Configuration Word

To allow port abil ity of c ode, it i s strongly recom mended

that the programmer is able to read the Configuration

Words and user ID locations from the hex file. If the

Config uration Wo rds informatio n was not present in the

hex file, a simple warning message may be issued.

Similarly, while saving a hex file, Configuration Words

and user ID information should be included.

7.2 Device ID and Revision

If a device ID is present in the hex file at

1000Ch-1000Dh (8006h on the part), the programmer

should verify the device ID (excluding the revision)

against the value read from the part. On a mismatch

condition the programmer should generate a warning

message.

7.3 Data EEPROM

The programmer should be able to read data memory

information from a hex file and write data memory

contents to a hex file.

The phys ic al address range of the 25 6 data memory is

0000h-00FFh. However, these addresses are logically

mapped to address 1E000h-1E1FFh in the hex file.

This provi des a way of dif ferenti ating betwe en the data

and program memory locations in this range. The

format for data memory storage is one data byte per

address location, LSb aligned.

Note: To ensure system security, if CPD bit = 0,

the Bulk Erase Program Memory command

will also erase dat a m emory.

PIC16F193X/LF193X

7.4 Checksum Computation

The checksum is calculated by two different methods

dependent on the setting of the CP Configuration bit.

7.4.1 PROGRAM CODE PROTECTION

DISABLED

With the program code protection disabled, the

checksum is computed by reading the contents of the

PIC16F193X/PIC16LF193X program memory locations

and adding up the program memory data starting at

address 0000h, up to the maximum user addressable

location (e.g., 1FFFH for the PIC16F1936). Any Carry

bit exceeding 16 bits are ignored. Additionally, the

relevant bits of the Configuration Words are added to

the checksum. All unimplemented Configuration bits

are masked to ‘0’.

EXAMPLE 7-1: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED

(PIC16F1936)

EXAMPLE 7-2: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED

(PIC16LF1936)

TABLE 7-1: CONFIGURATION WORD

MASK VALUES

Device Config. Wo rd 1

Mask Config. W ord 2

Mask

PIC16F1933 3FFFh 3733h

PIC16LF1933 3FFFh 3703h

PIC16F1934 3FFFh 3733h

PIC16LF1934 3FFFh 3703h

PIC16F1936 3FFFh 3733h

PIC16LF1936 3FFFh 3703h

PIC16F1937 3FFFh 3733h

PIC16LF1937 3FFFh 3703h

PIC16F1938 3FFFh 3733h

PIC16LF1938 3FFFh 3703h

PIC16F1939 3FFFh 3733h

PIC16LF1939 3FFFh 3703h

Note: Data memory does not effect the

checksum.

PIC16F1936 Sum of Memory addresses 0000h-1FFFh 2534h

Configuration Word 1 2D83h

Configurat ion Word 1 mask 3FFFh

Configuration Word 2 3AEFh

Configuration Word 2 mask 3733h

Checksum = 2534h + (2D83h and 3FFFh) + (3AEFh and 3733h)

= 2534h + 2D83h + 3223h

= 84DAh

PIC16LF1936 Sum of Memory addresses 0000h-1FFFh 2534h

Configuration Word 1 2D83h

Configurat ion Word 1 mask 3FFFh

Configuratio n Word 2 3AFFh

Configuration Word 2 mask(1) 3703h

Checksum = 2534h + (2 D83h and 3FFFh) + (3AFFh and 3703h)

= 2534h + 2D83h + 3203h

= 84BAh

Note 1: In PIC16LF193X de vices, the VCAPEN<1:0 > bits are not im plemented in Con figuration W ord 2 and the

Configuration Word 2 mask is 3703h.

PIC16F193X/LF193X

7.4.2 PROGRAM CODE PROTECTI ON

ENABLED

With the program code protection enabled the

checksum is computed in the following manner. The

Configuration Words are summed (all unimplemented

Configuration bits are masked to ‘0’) with the Least

Significant nibble of the user ID’s.

EXAMPLE 7-3: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED

(PIC16F1936)

EXAMPLE 7-4: CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED

(PIC16LF1936)

Note: Data memory does not effect the

checksum.

PIC16F1936 Configuration Word 1 2C03h

Configuration Word 1 mask 3FFFh

Configuration Word 2 3AECh

Configuration Word 2 mask 3733h

User ID (8000h ) 0123h

User ID (8001h ) 4567h

User ID (8002h) 89ABh

User ID (8003h ) CDEFh

Checksum = (2C03h and 3FFFh) + (3AECh and 3733h) + (0123h and 000Fh) +

(4567h and 000Fh) + (89ABh and 000Fh) +(CDEFh and 000Fh)

= 2C03h +3220h + 0003h + 0007h + 000Bh + 000Fh

= 5E47h

PIC16LF1936 Configuration Word 1 2C03h

Configuration Word 1 mask 3FFFh

Configuration Word 2 3AFCh

Configuration Word 2 mask(1) 3703h

User ID (8000h ) 0123h

User ID (8001h ) 4567h

User ID (8002h) 89ABh

User ID (8003h ) CDEFh

Checksum = (2C03h and 3FFFh) + (3AFCh an d 3703h) + (0123h and 000Fh) +

(4567h and 000Fh) + (89ABh and 000Fh) +(CDEFh and 000Fh)

= 2C03h +3200h + 0003h + 0007h + 000Bh + 000Fh

= 5E27h

Note 1: In PIC16LF19 3X devices, the VCAPEN<1 :0> bits are not implem ented in Confi guration W ord 2 and the

Configuration Word 2 mask is 3703h.

PIC16F193X/LF193X

8.0 ELECTRICAL SPECIFICATIONS

Refer to device specific data sheet for absolute

maximum ratings.

TABLE 8-1: AC/DC CHARACTERISTICS T IMING REQUIREMENT S FOR PROGRAM/VERIFY MODE

AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating Tem perat ure -40°C ≤ TA ≤ +85°C

Sym. Characteristics Min. Typ. Max. Units Conditions/Comments

Supply Voltages and currents

VDD

VDD Read/Write and Row Erase

operations PIC16F193X 2.1 — 5.5 V

PIC16LF193X 2.1 — 3.6 V

Bulk Erase operations PIC16F193X 2.7 — 5.5 V

PIC16LF193X 2.7 — 3.6 V

IDDI Current on VDD, Id l e — — 1.0 mA

IDDP Current on VDD, Programming — — 3.0 mA

IPP

VPP

Current on MCLR/VPP — — 600 μA

VIHH High voltage on MCLR/VPP for

Program/Verify mode entry 8.0 — 9.0 V

TVHHR MCLR rise time (VIL to VIHH) for

Program/Verify mode entry ——1.0μs

I/O pins

VIH (ICSPCL K , ICSPDAT, MCLR/VPP) input high

level 0.8 VDD ——V

VIL (ICSPCL K , ICSPDAT, MCLR/VPP) input low level — — 0.2 VDD V

VOH ICSPDAT output high level VDD-0.7

VDD-0.7

VDD-0.7 ——V

IOH = 3.5 mA, VDD = 5V

IOH = 3 mA, VDD = 3.3V

IOH = 2 mA, VDD = 1.8V

VOL ICSPDAT output low level ——

VSS+0.6

VSS+0.6 VIOH = 8 mA, VDD = 5V

IOH = 6 mA, VDD = 3.3V

IOH = 3 mA, VDD = 1.8V

Programming mode entry and exit

TENTS Programing mode entry setup time: ICSPC LK,

ICSPDAT setup time before VDD or MCLR↑ 100 — — ns

TENTH Programing mode entry hold time: ICSPCLK,

ICSP D AT hold time a fte r VDD or MCLR↑ 250 — — μs

Serial Program/Veri fy

TCKL Clock Low Pulse Width 100 — — ns

TCKH Clock High Pulse Width 100 — — ns

TDS Data in setup time before clock↓100 — — ns

TDH Data in hold time after clock↓100 — — ns

TCO Clock↑ to data out valid (during a

Read Data command) 0 — 80 ns

TLZD Clock↓ to data low-impedance (during a

Read Data command) 0 — 80 ns

THZD Clock↓ to data high-impedance (during a

Read Data command) 0 — 80 ns

TDLY Data input not driven to next clock input (delay

required between command/data or

command/command) 1.0 — — μs

TERAB Bulk Erase cycle time — — 5 ms

TERAR Row Erase cycle time — — 2.5 ms

TPINT Internally timed programming operation time —

——

—2.5

5ms

ms Program memory

Configuration words

TPEXT Externally timed programming pulse 1.0 — 2.1 m s

TDIS Time delay from program to compare

(HV discharge time) 100 — — μs

TEXIT Time delay when exiting Program/Verify mode 1 — — μs

PIC16F193X/LF193X

8.1 AC Timing Diagr ams

FIGURE 8-2: PROGRAMMING MODE

ENTRY – VDD FIRST

FIGURE 8-3: PROGRAMMING MODE

ENTRY – VPP FIRST

FIGURE 8-4: PROGRAMMING MODE

EXIT – VPP LAST

FIGURE 8-5: PROGRAMMING MODE

EXIT – VDD LAST

FIGURE 8-6: CLOCK AND DATA

TIMING

VPP

TENTH

VDD

TENTS

ICSPDAT

ICSPCLK

VIHH

VIL

TENTH

ICSPDAT

ICSPCLK

VDD

TENTS

VPP

VIHH

VIL

TEXIT

VPP

VDD

ICSPDAT

ICSPCLK

VIHH

VIL

TEXIT

VPP

VDD

ICSPDAT

ICSPCLK

VIHH

VIL

ICSPCLK

TCKH TCKL

TDH

TDS

ICSPDAT

output

TCO

ICSPDAT

TLZD

THZD

input

from input

from output

to input

to output

PIC16F193X/LF193X

FIGURE 8-7: WRITE COMMAND-PAYLOAD TIMING

FIGURE 8-8: READ COMMAND-PAYLOAD TIMING

123 4561215 16

X0LSb MSb 0

TDLY

Command Next

Command

Payload

ICSPCLK

ICSPDAT XXXXX

123 4561215 16

TDLY

Command Next

Command

Payload

ICSPCLK

ICSPDAT XXXXX

(from Programmer)

LSb MSb 0

ICSPDAT

(from Device)

PIC16F193X/LF193X

FIGURE 8-9: LVP ENTRY (POWERING UP)

FIGURE 8-10: LVP ENTRY (POWERED)

TCKLTCKH

33 clocks

012... 31

TDH

TDS

TENTH

LSb of Pattern MSb of Pattern

VDD

MCLR

ICSPCLK

ICSPDAT

TENTS

TCKH TCKL

33 Clocks

Note 1: Sequence matching can start with no edge on MCLR first.

0 1 2 ... 31

TDH

TDS

TENTH

LSb of Pattern MSb of Pattern

VDD

MCLR

ICSPCLK

ICSPDAT

PIC16F193X/LF193X

APPENDIX A: REVISION HISTORY

Revision A (11/2008)

Original release of this document.

PIC16F193X/LF193X

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . It is y our responsibil i ty to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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OTHERWISE, RELATED TO THE INFORMATION,

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FITNESS FOR PURPOSE. Microchip disclaims all liability

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intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MX LAB ,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , ICSP, ICEP I C , M in d i , MiWi, M PASM , MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

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Endurance, WiperLock and ZENA are trademarks of

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SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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