7544 Group (QzROM version) - Renesas Technology / Hitachi Semiconductor

DESCRIPTION

The 7544 Group is the 8-bit microcomputer based on the 740 fam-

ily core technology.

The 7544 Group has a serial interface, 8-bit timers, a 16-bit timer,

and an A/D converter, and is useful for control of home electric ap-

pliances and office automation equipment.

FEATURES

•Basic machine-language instructions ...................................... 71

•The minimum instruction execution time ......................... 0.25 µs

(at 8 MHz oscillation frequency, double-speed mode for the

shortest instruction)

•Memory size ROM.........................................................8 K bytes

RAM ........................................................ 256 bytes

•Programmable I/O ports........................................................... 25

•Interrupts ................................................. 12 sources, 12 vectors

•Timers............................................................................. 8-bit ✕ 2

...................................................................................... 16-bit ✕ 1

•Serial interface ............ 8-bit ✕ 1 (UART or Clock-synchronized)

•A/D converter ................................................. 8-bit ✕ 6 channels

•Clock generating circuit............................................. Built-in type

(low-power dissipation by an on-chip oscillator enabled)

(connect to external ceramic resonator or quartz-crystal oscilla-

tor permitting RC oscillation)

•Watchdog timer ............................................................16-bit ✕ 1

•Power source voltage

oscillation frequency at ceramic/quartz-crystal oscillation, in

double-speed mode

At 8 MHz .............................................. 4.5 to 5.5 V

At 4 MHz .............................................. 4.0 to 5.5 V

At 2 MHz .............................................. 2.4 to 5.5 V

At 1 MHz .............................................. 2.2 to 5.5 V

XIN oscillation frequency at ceramic/quartz-crystal oscillation, in

high-speed mode

At 8 MHz .............................................. 4.0 to 5.5 V

At 4 MHz .............................................. 2.4 to 5.5 V

At 2 MHz .............................................. 2.2 to 5.5 V

XIN oscillation frequency at RC oscillation

At 4 MHz .............................................. 4.0 to 5.5 V

At 2 MHz .............................................. 2.4 to 5.5 V

At 1 MHz .............................................. 2.2 to 5.5 V

XIN oscillation frequency at on-chip oscillator .......... 1.8 to 5.5 V

•Power dissipation ...........................................22.5mW(standard)

•Operating temperature range...................................–20 to 85 °C

APPLICATION

Office automation equipment, factory automation equipment,

home electric appliances, consumer electronics, etc.

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7544 Group (QzROM version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0108-0102

Rev.1.02

2005.07.20

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 2 of 61

REJ03B0108-0102

Fig. 2 Pin configuration (PLQP0032GB-A type)

Package type : PLQP0032GB-A (32P6U-A)

CNV

/AN

(LED

)

(LED

)

(LED

)

(LE

)/TX

OUT

(LED

)

(LED

)

(LED

)/CNTR

(LED

)/INT

M37544G2A-XXXGP

M37544G2AGP

/AN

REF

RESET

P20/

P21/

P14/CNTR0

P13/SRDY

P12/SCLK

P11/TXD

P10/RXD

P07(LED7)

XOUT

XIN

VSS

P30(LED8)

P31(LED9)

P32(LED10)

P33(LED11)

P34(LED12)/INT1

PIN CONFIGURATION (TOP VIEW)

Fig. 1 Pin configuration (PRDP0032BA-A type)

Package type : PRDP0032BA-A (32P4B)

P12/SCLK

M37544G2A-XXXSP

M37544G2ASP

P13/SRDY

P14/CNTR0

P20/AN0

P21/AN1

P22/AN2

P23/AN3

P24/AN4

P25/AN5

VREF

CNVSS

VCC

XIN

XOUT

VSS

RESET

P11/TXD

P10/RXD

P07(LED7)

P06(LED6)

P05(LED5)

P04(LED4)

P03(LED3)/TXOUT

P02(LED2)

P01(LED1)

P00(LED0)/CNTR1

P34(LED12)/INT1

P33(LED11)

P32(LED10)

P31(LED9)

P30(LED8)

P37(LED13)/INT0

7544 Group (QzROM version)

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Table 1 Performance overview

Parameter

0.25 µs (Minimum instruction, oscillation frequency = 8MHz,

double-speed mode)

8 MHz (Maximum)

8 K bytes

256 bytes

8-bit ✕ 1, 6-bit ✕ 2, 5-bit ✕ 1

12 sources, 12 vectors

8-bit ✕ 2, 16-bit ✕ 1

8-bit ✕ 1 (UART or Clock-synchronized)

8-bit resolution ✕ 6 channels

16-bit ✕ 1

Low-power dissipation by an on-chip oscillator enabled (connect

to external ceramic resonator or quartz-crystal oscillator permit-

ting RC oscillation)

4.0 to 5.5 V

2.4 to 5.5 V

2.2 to 5.5 V

4.5 to 5.5 V

4.0 to 5.5 V

2.4 to 5.5 V

2.2 to 5.5 V

4.5 to 5.5 V

2.4 to 5.5 V

2.2 to 5.5 V

1.8 to 5.5V

Std. 22.5 mW

-20 to 85 °C

CMOS sillicon gate

32-pin plastic molded SDIP/LQFP

Number of basic instructions

Instruction execution time

Oscillation frequency

Memory sizes

Input output port

Interrupt

Timer

Serial interface

A/D converter

Watchdog timer

Clock generating circuits

Power source

voltage

(ceramic oscillation

frequency)

Power source

voltage

(RC oscillation frequency)

Power source voltage (In on-chip oscillator frequency)

Power dissipation

Operating temperature range

Device structure

Package

Function

ROM

RAM

P0, P1, P2, P3

In high-,middle-speed mode

In double-speed mode

In high-,middle-speed mode

8MHz

4MHz

2MHz

8MHz

4MHz

2MHz

1MHz

4MHz

2MHz

1MHz

7544 Group (QzROM version)

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FUNCTIONAL BLOCK

Fig. 3 Functional block diagram (PRDP0032BA-A package)

FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0032BA-A)

16 11

13 12

P1(5)

232

P2(6)

P3(6)

1720 18

14 15

2122

P0(8)

30 28 26 24

29 27 25 23

A/D

converter

(8)

IN OUT

CPU

RESET

CNV

I/O port P2 I/O port P0I/O port

I/O port P3

SI/O(8)

RAM ROM A

Reset input

Clock generating circuit

Clock input Clock output

REF

Watchdog timer

Reset

INT

CNTR

Timer X (8)

Key-on wakeup

Prescaler X (8)

CNTR

Timer A (16)

Timer 1 (8)

Prescaler 1 (8)

OUT

INT

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Fig. 4 Functional block diagram (PLQP0032GB-A package)

FUNCTIONAL BLOCK DIAGRAM (Package: PLQP0032GB-A)

IN OU

SI/O(8)

RAM ROM

CPU

RESET

CNV

P1(5)

30 28 26

29 27

32 31

P2(6)

P3(6)

1215 13

Reset input

I/O port P2 I/O port P1I/O port P3

Clock generating circuit

Clock input Clock output

910

A/D

converter

(8)

REF

Watchdog timer

Reset

INT

1617

CNTR

I/O port P0

Timer X (8)

Key-on wakeup

Prescaler X (8)

CNTR

Timer A (16)

P0(8)

25 23 21 19

24 22 20 18

Timer 1 (8)

Prescaler 1 (8)

OUT

INT

7544 Group (QzROM version)

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PIN DESCRIPTION

Table 1 Pin description Function

•Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss.

•Reference voltage input pin for A/D converter

•Chip operating mode control pin, which is always connected to Vss.

•Reset input pin for active “L”

•Input and output pins for main clock generating circuit

•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins.

•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.

•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• When the on-chip oscillator is selected as the main clock, connect X

pin to V

and leave X

OUT

open.

Function expect a port function

Name

Power source

Analog reference

voltage

CNVss

Reset input

Clock input

I/O port P0

I/O port P1

Vcc, Vss

VREF

CNVss

______

RESET

XIN

P00/CNTR1

P01

P02

P03/TXOUT

P04–P07

• Key-input (key-on wake up

interrupt input) pins

• Timer X and timer A function

•8-bit I/O port.

•I/O direction register allows each pin to be individually pro-

grammed as either input or output.

•CMOS compatible input level

•CMOS 3-state output structure

•P0 can output a large current for driving LED.

•Whether a built-in pull-up resistor is to be used or not can be de-

termined by program.

•5-bit I/O port

•I/O direction register allows each pin to be individually pro-

grammed as either input or output.

•CMOS compatible input level

•CMOS 3-state output structure

•CMOS/TTL level can be switched for P10 and P12

•6-bit I/O port having almost the same function as P0

•CMOS compatible input level

•CMOS 3-state output structure

P10/RxD

P11/TxD

P12/SCLK

____

RDY

P14/CNTR0

/AN

–P2

/AN

P30–P33

P34/INT1

P37/INT0

I/O port P2

I/O port P3

• Serial I/O function pin

• Timer X function pin

• Input pins for A/D converter

• Interrupt input pins

•6-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level (CMOS/TTL level can be switched for P34 and P37).

•CMOS 3-state output structure

•P3 can output a large current for driving LED.

XOUT Clock output

•Whether a built-in pull-up resistor is to be used or not can be de-

termined by program.

7544 Group (QzROM version)

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GROUP EXPANSION

We are planning to expand the 7544 group (QzROM version) as

follow:

Memory type

Support for QzPROM version.

Memory size

ROM size ..........................................................................8 K bytes

RAM size ......................................................................... 256 bytes

Package

PRDP0032BA-A ..................................32-pin plastic molded SDIP

PLQP0032GB-A .......... 0.8 mm-pitch 32-pin plastic molded LQFP

Fig. 5 Memory expansion plan

Currently supported products are listed below.

Table 2 List of supported products

ROM size

(bytes)

RAM size

(bytes)

256

M37544G2A

Part number ROM size (bytes)

ROM size for User ()

8192

(8062)

RAM size

(bytes)

256

Package

PRDP0032BA-A

PLQP0032GB-A

PRDP0032BA-A

PLQP0032GB-A

Remarks

M37544G2A-XXXSP

M37544G2A-XXXGP

M37544G2ASP

M37544G2AGP

QzROM version

QzROM version (blank)

7544 Group (QzROM version)

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FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The MCU uses the standard 740 family instruction set. Refer to

the table of 740 family addressing modes and machine-language

instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL

for details on each instruction set.

Machine-resident 740 family instructions are as follows:

1. The FST and SLW instructions cannot be used.

2. The MUL and DIV instructions can be used.

3. The WIT instruction can be used.

4. The STP instruction can be used.

This instruction cannot be used while CPU operates by an on-chip

oscillator.

Accumulator (A)

The accumulator is an 8-bit register. Data operations such as data

transfer, etc., are executed mainly through the accumulator.

Index register X (X), Index register Y (Y)

Both index register X and index register Y are 8-bit registers. In

the index addressing modes, the value of the OPERAND is added

to the contents of register X or register Y and specifies the real

address.

When the T flag in the processor status register is set to “1”, the

value contained in index register X becomes the address for the

second OPERAND.

Stack pointer (S)

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. The stack is used to store the current address data

and processor status when branching to subroutines or interrupt

routines.

The lower eight bits of the stack address are determined by the

contents of the stack pointer. The upper eight bits of the stack ad-

dress are determined by the Stack Page Selection Bit. If the Stack

Page Selection Bit is “0”, then the RAM in the zero page is used

as the stack area. If the Stack Page Selection Bit is “1”, then RAM

in page 1 is used as the stack area.

The Stack Page Selection Bit is located in the SFR area in the

zero page. Note that the initial value of the Stack Page Selection

Bit varies with each microcomputer type. Also some microcom-

puter types have no Stack Page Selection Bit and the upper eight

bits of the stack address are fixed. The operations of pushing reg-

ister contents onto the stack and popping them from the stack are

shown in Fig. 7.

Program counter (PC)

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

Fig. 6 740 Family CPU register structure

b7 b0

PCL

Processor Status Register (PS)

Carry Flag

b7 b0

b15

PCH

Zero Flag

Interrupt Disable Flag

Decimal Mode Flag

Break Flag

Index X Mode Flag

Overflow Flag

Negative Flag

Program Counter

Stack Pointer

Index Register Y

Index Register X

Accumulator

CZIDBTVN

7544 Group (QzROM version)

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Table 3 Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

Fig. 7 Register push and pop at interrupt generation and subroutine call

Execute JSR

On-going Routine

M (S) (PC

)

(S) (S – 1)

M (S) (PC

)

Execute RTS

(PC

) M (S)

(S) (S – 1)

(S) (S + 1)

(PC

) M (S)

Subroutine

Restore Return

Address

Store Return Address

on Stack M (S) (PS)

Execute RTI

(PS) M (S)

(S) (S – 1)

(S) (S + 1)

Interrupt

Service Routine

Restore Contents of

Processor Status Register

M (S) (PC

)

(S) (S – 1)

M (S) (PC

)

(S) (S – 1)

(PC

) M (S)

(S) (S + 1)

(PC

) M (S)

Restore Return

Address

I Flag “0” to “1”

Fetch the Jump Vector

Store Return Address

on Stack

Store Contents of Processor

Status Register on Stack

Interrupt request

(Note)

Note : The condition to enable the interrupt Interrupt enable bit is “1”

Interrupt disable flag is “0”

7544 Group (QzROM version)

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Processor status register (PS)

The processor status register is an 8-bit register consisting of

flags which indicate the status of the processor after an arithmetic

operation. Branch operations can be performed by testing the

Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)

flag. In decimal mode, the Z, V, N flags are not valid.

After reset, the Interrupt disable (I) flag is set to “1”, but all other

flags are undefined. Since the Index X mode (T) and Decimal

mode (D) flags directly affect arithmetic operations, they should

be initialized in the beginning of a program.

(1) Carry flag (C)

The C flag contains a carry or borrow generated by the arithmetic

logic unit (ALU) immediately after an arithmetic operation. It can

also be changed by a shift or rotate instruction.

(2) Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic operation

or a data transfer is “0”, and cleared if the result is anything other

than “0”.

(3) Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt generated

by the BRK instruction. Interrupts are disabled when the I flag is

“1”.

When an interrupt occurs, this flag is automatically set to “1” to

prevent other interrupts from interfering until the current interrupt

is serviced.

(4) Decimal mode flag (D)

The D flag determines whether additions and subtractions are ex-

ecuted in binary or decimal. Binary arithmetic is executed when

this flag is “0”; decimal arithmetic is executed when it is “1”.

Decimal correction is automatic in decimal mode. Only the ADC

and SBC instructions can be used for decimal arithmetic.

(5) Break flag (B)

The B flag is used to indicate that the current interrupt was gener-

ated by the BRK instruction. The BRK flag in the processor status

ate an interrupt, the processor status register is pushed onto the

stack with the break flag set to “1”. The saved processor status is

the only place where the break flag is ever set.

(6) Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed be-

tween accumulator and memory, e.g. the results of an operation

between two memory locations is stored in the accumulator. When

the T flag is “1”, direct arithmetic operations and direct data trans-

fers are enabled between memory locations, i.e. between memory

and memory, memory and I/O, and I/O and I/O. In this case, the

result of an arithmetic operation performed on data in memory lo-

cation 1 and memory location 2 is stored in memory location 1.

The address of memory location 1 is specified by index register X,

and the address of memory location 2 is specified by normal ad-

dressing modes.

(7) Overflow flag (V)

The V flag is used during the addition or subtraction of one byte of

signed data. It is set if the result exceeds +127 to -128. When the

BIT instruction is executed, bit 6 of the memory location operated

on by the BIT instruction is stored in the overflow flag.

(8) Negative flag (N)

The N flag is set if the result of an arithmetic operation or data

transfer is negative. When the BIT instruction is executed, bit 7 of

the memory location operated on by the BIT instruction is stored in

the negative flag.

Table 4 Set and clear instructions of each bit of processor status register

Set instruction

Clear instruction

C flag

SEC

CLC

Z flag

–

I flag

SEI

CLI

D flag

SED

CLD

B flag

–

T flag

SET

CLT

V flag

–

CLV

N flag

–

7544 Group (QzROM version)

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[CPU mode register] CPUM

The CPU mode register contains the stack page selection bit.

This register is allocated at address 003B16.

Switching method of CPU mode register

Switch the CPU mode register (CPUM) at the head of program af-

ter releasing Reset in the following method.

Fig. 9 Switching method of CPU mode register

Fig. 8 Structure of CPU mode register

Processor mode bits (Note 1)

b1 b0

0 0 Single-chip mode

0 1

1 0

1 1

Not available

b7 b0

2: These bits are used only when a ceramic

/quartz-crystal

oscillation is selected.

Note 1: The bit can be rewritten only once after releasing reset. After rewriting

it is disable to write any data to the bit. However, by reset the bit is

initialized and can be rewritten, again.

Do not use these when an RC oscillation is selected.

Oscillation mode selection bit (Note 1)

0 : Ceramic/quartz-crystal oscillation

1 : RC oscillation

CPU mode register

(CPUM: address 003B

, initial value: 80

)

Stack page selection bit

0 : 0 page

1 : 1 page

Clock division ratio selection bits

b7 b6

0 0 : f(φ) = f(X

)/2 (High-speed mode)

0 1 : f(φ) = f(X

)/8 (Middle-speed mode)

1 0 : applied from on-chip oscillator

1 1 : f(φ) = f(X

) (Double-speed mode)(Note 2)

On-chip oscillator oscillation control bit

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

oscillation control bit

0 : Ceramic/quartz-crystal or RC oscillation enabled

1 : Ceramic/quartz-crystal or RC oscillation stop

After releasing reset

Switch the oscillation mode

selection bit (bit 5 of CPUM)

Switch the clock division ratio

selection bits (bits 6 and 7 of CPUM)

Main routine

Start with an on-chip oscillator

An initial value is set as a ceramic/quartz-crystal

oscillation mode. When it is switched to an RC

oscillation, its oscillation starts.

Select 1/1, 1/2, 1/8 or on-chip oscillator.

Wait by on-chip oscillator operation

until establishment of oscillator clock

When using a ceramic/quartz-crystal oscillation, wait

until establlishment of oscillation from oscillation starts.

When using an RC oscillation, wait time is not required

basically (time to execute the instruction to switch from

an on-chip oscillator meets the requirement).

7544 Group (QzROM version)

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Memory

Special function register (SFR) area

The SFR area in the zero page contains control registers such as

I/O ports and timers.

RAM

RAM is used for data storage and for a stack area of subroutine

calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is a user area for storing programs.

ROM Code Protect Address (address FFD416)

Address FFD416, which is the reserved ROM area of QzROM, is

the ROM code protect address. “0016” is written into this address

when selecting the protect bit write by using a serial programmer

or selecting protect enabled for writing shipment by Renesas

Technology corp.. When “0016” is set to the ROM code protect ad-

dress, the protect function is enabled, so that reading or writing

from/to QzROM is disabled by a serial programmer.

As for the QzROM product in blank, the ROM code is protected by se-

lecting the protect bit write at ROM writing with a serial programmer.

As for the QzROM product shipped after writing, “0016” (protect

enabled) or “FF16” (protect disabled) is written into the ROM code

protect address when Renesas Technology corp. performs writing.

The writing of “0016” or “FF16” can be selected as the ROM (re-

ferred to as “Mask option setup” in MM) when ordering.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

Zero page

The 256 bytes from addresses 000016 to 00FF16 are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF0016 to FFFF16 are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

■ Note on use

The content of RAM is undefined when the microcomputer is re-

set. The initial values must be surely set before you use it.

Fig. 10 Memory map diagram

010016

000016

004016

044016

FF0016

FFD516

FFFE16

FFFF16

256

XXXX16

013F16

8192 E00016 E08016

YYYY16

ZZZZ16

RAM

ROM

Reserved area

SFR area

Disable

Interrupt vector area

ROM area

Reserved ROM area

(128 bytes)

Zero page

Special pag

RAM area

RAM capacity

(bytes) address

XXXX

ROM capacity

(bytes) address

YYYY

Reserved ROM area

address

ZZZZ

16 FFD416 Function set ROM area

Function set ROM area

Address

FFD4

ROM code protect

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Fig. 11 Memory map of special function register (SFR)

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Pull-up control register (PULL)

Transmit/Receive buffer register (TB/RB)

Serial I/O status register (SIOSTS)

Serial I/O control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

Port P1P3 control register (P1P3C)

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

Timer count source set register1 (TCSS1)

A/D register (AD)

Prescaler 1 (PRE1)

Timer 1 (T1)

Reserved

Timer X mode register (TXM)

Prescaler X (PREX)

Timer X (TX)

Reserved

A/D control register (ADCON)

Reserved

MISRG

Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt control register 1 (ICON1)

Timer A mode register (TAM)

Timer A (low-order) (TAL)

Timer A (high-order) (TAH)

Reserved

Interrupt request register 2 (IREQ2)

Interrupt control register 2 (ICON2)

Reserved

Timer count source set register2 (TCSS2)

Reserved

Note : Do not access to the SFR area includin

nothin

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I/O Ports

[Direction registers] PiD

The I/O ports have direction registers which determine the input/

output direction of each pin. Each bit in a direction register corre-

sponds to one pin, and each pin can be set to be input or output.

When “1” is set to the bit corresponding to a pin, this pin becomes

an output port. When “0” is set to the bit, the pin becomes an in-

put port.

When data is read from a pin set to output, not the value of the pin

itself but the value of port latch is read. Pins set to input are float-

ing, and permit reading pin values.

If a pin set to input is written to, only the port latch is written to and

the pin remains floating.

[Pull-up control register] PULL

By setting the pull-up control register (address 001616), ports P0

and P3 can exert pull-up control by program. However, pins set to

output are disconnected from this control and cannot exert pull-up

control.

[Port P1P3 control register] P1P3C

By setting the port P1P3 control register (address 001716), a

CMOS input level or a TTL input level can be selected for ports

P10, P12, P34, and P37 by program.

Fig. 13 Structure of port P1P3 control register

Fig. 12 Structure of pull-up control register

Pull-up control register

(PULL: address 0016

, initial value: 00

)

pull-up control bit

, P0

pull-up control bit

– P0

pull-up control bit

– P3

pull-up control bit

Disable

pull-up control bit

b7 b0

0 : Pull-up Off

1 : Pull-up On

Note : Pins set to output ports are disconnected from pull-up control.

Port P1P3 control register

(P1P3C: address 001716, initial value: 0016)

b7 b0

P37/INT0 input level selection bit

0 : CMOS level

1 : TTL level

P34/INT1 input level selection bit

0 : CMOS level

1 : TTL level

P10,P12 input level selection bit

0 : CMOS level

1 : TTL level

Disable

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REJ03B0108-0102

Table 5 I/O port function table

P00/CNTR1

P01

P02

P03/TXOUT

P04–P07

P10/RxD

P11/TxD

P12/SCLK

____

P13/SRDY

P14/CNTR0

P20/AN0–

P25/AN5

P30–P33

P34/INT1

P37/INT0

Input/output

I/O individual

bits

I/O format

•CMOS compatible

input level

•CMOS 3-state output

(Note)

Non-port function

Key input interrupt

Timer X function output

Timer A function input

Serial I/O function

input/output

Timer X function input/output

A/D conversion input

External interrupt input

Related SFRs

Pull-up control register

Timer X mode register

Timer A mode register

Interrupt edge selection

Serial I/O control register

Port P1,P3 control register

Timer X mode register

A/D control register

Pull-up control register

Interrupt edge selection

Pull-up control register

Port P1,P3 control register

Diagram No.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

Note : Ports P10, P12, P34, and P37 are CMOS/TTL level.

Name

I/O port P0

I/O port P1

I/O port P2

I/O port P3

(8)

(9)

(10)

(11)

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REJ03B0108-0102

Fig. 14 Block diagram of ports (1)

(6)Port P1

Serial I/O clock output

Serial I/O mode selection bit

Serial I/O enable bit

Serial I/O synchronous

clock selection bit

Direction

Data bus Port latch

Serial I/O clock input

P10, P12

input level

selection bit

(2)Ports P0

,P0

4–

Direction

Data bus Port latch

Pull-up control

To key input interrupt

generating circuit

(1)Port P0

Direction

Data bus Port latch

Pull-up control

To key input interrupt

generating circuit

CNTR1 interrupt input

(3)Port P0

Direction

Data bus Port latch

Pull-up control

To key input interrupt

generating circuit

Timer output

P03/TXOUT

output valid

(5)Port P1

Data bus Port latch

Serial I/O output

P11/TxD P-channel output disable bit

Direction

Serial I/O enable bit

Transmit enable bit

(4)Port P1

Direction

Data bus Port latch

Serial I/O enable bit

Receive enable bit

Serial I/O input

P10, P12

input level

selection bit

*P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.

When the TTL level is selected, there is no hysteresis characteristics.

P00 key-on wakeup

selection bit

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REJ03B0108-0102

Fig. 15 Block diagram of ports (2)

Pull-up control

INT interrupt input

P3 input level

selection bit

(10) Ports P3

–P3

Pull-up control

(8) Port P1

Data bus

Serial I/O ready output

Port latch

Direction

CNTR

interrupt input

Pulse output mode

Timer output

Serial I/O mode selection bit

Serial I/O enable bit

RDY

output enable bit

, P1

, P3

, and P3

input level are switched to the CMOS/TTL level by the port P1P3 control register.

When the TTL level is selected, there is no hysteresis characteristics.

Data bus Port latch

Direction

Data bus Port latch

Direction

Data bus Port latch

Direction

A/D converter input Analog input pin

selection bit

(11) Ports P3

, P3

Data bus Port latch

Direction

(9) Ports P2

–P2

(7) Port P1

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REJ03B0108-0102

Termination of unused pins

• Termination of common pins

I/O ports: Select an input port or an output port and follow

each processing method.

Output ports: Open.

P00/CNTR1

P01, P02

P03/TXOUT

P04 to P07

P10/RxD

P11/TxD

P12/SCLK

P13/SRDY

P14/CNTR0

P20/AN0 to

P25/AN5

P30 to P33

P34/INT1

P37/INT0

VREF

Termination 1

(recommend)

I/O port

Vss.

Termination 2

When selecting CNTR1 input function,

perform termination of input port.

When selecting TXOUT function, perform

termination of output port.

When selecting RXD function, perform

termination of input port.

When selecting TXD function, perform

termination of output port.

When selecting external clock input, perform

termination of input port.

When selecting SRDY function, perform

termination of output port.

When selecting CNTR0 input function,

perform termination of input port.

When selecting AN function, perform

termination of input port.

When selecting INT1 function, perform

termination of input port.

When selecting INT0 function, perform

termination of input port.

Termination 3

When selecting CNTR1 output function,

perform termination of output port.

When selecting internal clock output,

perform termination of output port.

When selecting CNTR0 output function,

perform termination of output port.

Termination 4

When selecting key-on

wakeup function, per-

form termination of input

port.

Table 7 Termination of unused pins

Input ports: If the input level become unstable, through current

flow to an input circuit, and the power supply current

may increase.

Especially, when expecting low consumption current

(at STP or WIT instruction execution etc.), pull-up or

pull-down input ports to prevent through current

(built-in resistor can be used).

We recommend processing unused pins through a

resistor which can secure IOH(avg) or IOL(avg).

Because, when an I/O port or a pin which have an

output function is selected as an input port, it may

operate as an output port by incorrect operation etc.

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REJ03B0108-0102

Interrupts

Interrupts occur by 12 different sources : 5 external sources, 6 in-

ternal sources and 1 software source.

Interrupt control

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit, and they are controlled by

the interrupt disable flag. When the interrupt enable bit and the in-

terrupt request bit are set to “1” and the interrupt disable flag is set

to “0”, an interrupt is accepted.

The interrupt request bit can be cleared by program but not be set.

The interrupt enable bit can be set and cleared by program.

The reset and BRK instruction interrupt can never be disabled with

any flag or bit. All interrupts except these are disabled when the

interrupt disable flag is set.

When several interrupts occur at the same time, the interrupts are

received according to priority.

Interrupt operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status reg-

ister are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

4. Concurrently with the push operation, the interrupt destination

address is read from the vector table into the program counter.

[Interrupt edge selection register] INTEDGE

The valid edge of external interrupt INT0 and INT1 can be selected

by the interrupt edge selection bit, respectively.

By the key-on wakeup selection bit, enable/disable of a key-on

wakeup of P00 pin can be selected.

■ Notes on use

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address

003A16)

Timer X mode register (address 2B 16)

Timer A mode register (address 1D16)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

➀ Set the corresponding interrupt enable bit to “0” (disabled).

➁ Set the interrupt edge select bit (active edge switch bit) to “1”.

➂ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃ Set the corresponding interrupt enable bit to “1” (enabled).

Table 6 Interrupt vector address and priority

Vector addresses (Note 1)

High-order

Priority Low-order Interrupt request generating conditions RemarksInterrupt source

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

Note 1: Vector addressed contain internal jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt (valid at falling)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

STP release timer underflow

Non-maskable software interrupt

At reset input

At completion of serial I/O data receive

At completion of serial I/O transmit shift or

when transmit buffer is empty

At detection of either rising or falling edge of

INT0 input

At detection of either rising or falling edge of

INT1 input

At falling of conjunction of input logical level

for port P0 (at input)

At detection of either rising or falling edge of

CNTR0 input

At detection of either rising or falling edge of

CNTR1 input

At timer X underflow

Not available

At timer A underflow

Not available

At completion of A/D conversion

At timer 1 underflow

Not available

At BRK instruction execution

—

Reset (Note 2)

Serial I/O receive

Serial I/O transmit

INT0

INT1

Key-on wake-up

CNTR0

CNTR1

Timer X

Reserved area

T imer A

Reserved area

A/D conversion

Timer 1

Reserved area

BRK instruction

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REJ03B0108-0102

Fig. 16 Interrupt control

Fig. 17 Structure of Interrupt-related registers

Interrupt disable flag I

Interrupt request

Interrupt request bit

Interrupt enable bit

BRK instruction

Reset

b7 b0

Interrupt edge selection register

INT

interrupt edge selection bit

(INTEDGE : address 003A

, initial value : 00

)

Interrupt request register 1

Serial I/O receive interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ1 : address 003C

, initial value : 00

)

b7 b0 Interrupt control register 1

Serial I/O receive interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

(ICON1 : address 003E

, initial value : 00

)

Interrupt request register 2

Disable (returns “0” when read)

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ2 : address 003D

, initial value : 00

)

b7 b0 Interrupt control register 2

Disable (returns “0” when read)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F

, initial value : 00

)

(Do not write “1” to this bit)

Disable (returns “0” when read)

Timer 1 interrupt enable bit

A/D conversion interrupt enable bit

Disable (returns “0” when read)

Timer A interrupt enable bit

Disable (returns “0” when read)

Timer X interrupt enable bit

CNTR

interrupt enable bit

CNTR

interrupt enable bit

Key-on wake up interrupt enable bit

INT

interrupt enable bit

INT

interrupt enable bit

Serial I/O transmit interrupt enable bit

Disable (returns “0” when read)

Timer 1 interrupt request bit

A/D conversion interrupt request bit

Disable (returns “0” when read)

Timer A interrupt request bit

Disable (returns “0” when read)

Timer X interrupt request bit

CNTR

interrupt request bit

CNTR

interrupt request bit

Key-on wake up interrupt request bit

INT

interrupt request bit

INT

interrupt request bit

Serial I/O transmit interrupt request bit

1 : Key-on wakeup disabled

0 : Key-on wakeup enabled

key-on wakeup enable bit

Disable (returns “0” when read)

1 : Rising edge active

0 : Falling edge active

INT

interrupt edge selection bit

1 : Rising edge active

0 : Falling edge active

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Key Input Interrupt (Key-On Wake-Up)

A key-on wake-up interrupt request is generated by applying “L”

level to any pin of port P0 that has been set to input mode.

In other words, it is generated when the AND of input level goes

from “1” to “0”. An example of using a key input interrupt is shown

in Figure 18, where an interrupt request is generated by pressing

one of the keys provided as an active-low key matrix which uses

ports P00 to P03 as input ports.

Fig. 18 Connection example when using key input interrupt and port P0 block diagram

Port PXx

“L” level output

PULL register

bit 3 = “0”

Port P0

latch

Port P0

Direction register = “1”

***

output

Key input interrupt request

Port P0

Input read circuit

* P-channel transistor for pull-up

** CMOS out

ut buffer

PULL register

bit 3 = “0”

Port P0

latch

Port P0

Direction register = “1”

***

output

PULL register

bit 3 = “0”

Port P0

latch

Port P0

Direction register = “1”

***

output

PULL register

bit 3 = “0”

Port P0

latch

Port P0

Direction register = “1”

***

output

PULL register

bit 2 = “1”

Port P0

latch

Port P0

Direction register = “0”

***

input

PULL register

bit 2 = “1”

Port P0

latch

Port P0

Direction register = “0”

***

input

PULL register

bit 1 = “1”

Port P0

latch

Port P0

Direction register = “0”

***

input

PULL register

bit 0 = “1”

Port P0

latch

Port P0

Direction register = “0”

***

input

Falling edge

detection

Falling edge

detection

Falling edge

detection

Falling edge

detection

Falling edge

detection

Falling edge

detection

Falling edge

detection

Falling edge

detection

Port P0

key-on wakeup

selection bit

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REJ03B0108-0102

Timers

The 7544 Group has 3 timers: timer 1, timer A and timer X.

The division ratio of every timer and prescaler is 1/(n+1) provided

that the value of the timer latch or prescaler is n.

All the timers are down count timers. When a timer reaches “0”, an

underflow occurs at the next count pulse, and the corresponding

timer latch is reloaded into the timer. When a timer underflows, the

interrupt request bit corresponding to each timer is set to “1”.

●Timer 1

Timer 1 is an 8-bit timer and counts the prescaler output.

When Timer 1 underflows, the timer 1 interrupt request bit is set to

“1”.

Prescaler 1 is an 8-bit prescaler and counts the signal selected by

the timer 1 count source selection bit.

Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1

latch to retain the reload value, respectively. The value of

prescaler 1 latch is set to Prescaler 1 when Prescaler 1

underflows. The value of timer 1 latch is set to Timer 1 when Timer

1 underflows.

When writing to Prescaler 1 (PRE1) is executed, the value is writ-

ten to both the prescaler 1 latch and Prescaler 1.

When writing to Timer 1 (T1) is executed, the value is written to

both the timer 1 latch and Timer 1.

When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-

ecuted, each count value is read out.

Timer 1 always operates in the timer mode.

Prescaler 1 counts the signal selected by the timer 1 count source

selection bit. Each time the count clock is input, the contents of

Prescaler 1 is decremented by 1. When the contents of Prescaler

1 reach “0016”, an underflow occurs at the next count clock, and

the prescaler 1 latch is reloaded into Prescaler 1 and count contin-

ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the

value of Prescaler 1 is n.

The contents of Timer 1 is decremented by 1 each time the under-

flow signal of Prescaler 1 is input. When the contents of Timer 1

reach “0016”, an underflow occurs at the next count clock, and the

timer 1 latch is reloaded into Timer 1 and count continues. The di-

vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer

1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is

1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and

the value of Timer 1 is m.

Timer 1 cannot stop counting by software.

●Timer A

Timer A is a 16-bit timer and counts the signal selected by the

timer A count source selection bit. When Timer A underflows, the

timer A interrupt request bit is set to “1”.

Timer A consists of the low-order of Timer A (TAL) and the high-or-

der of Timer A (TAH).

Timer A has the timer A latch to retain the reload value. The value

of timer A latch is set to Timer A at the timing shown below.

• When Timer A undeflows.

• When an active edge is input from CNTR1 pin (valid only when

period measurement mode and pulse width HL continuously mea-

surement mode).

When writing to both the low-order of Timer A (TAL) and the high-

order of Timer A (TAH) is executed, the value is written to both the

timer A latch and Timer A.

When reading from the low-order of Timer A (TAL) and the high-or-

der of Timer A (TAH) is executed, the following values are read out

according to the operating mode.

• In timer mode, event counter mode:

The count value of Timer A is read out.

• In period measurement mode, pulse width HL continuously mea-

surement mode:

The measured value is read out.

Be sure to write to/read out the low-order of Timer A (TAL) and the

high-order of Timer A (TAH) in the following order;

Read

Read the high-order of Timer A (TAH) first, and the low-order of

Timer A (TAL) next and be sure to read out both TAH and TAL.

Write

Write to the low-order of Timer A (TAL) first, and the high-order of

Timer A (TAH) next and be sure to write to both TAL and TAH.

Timer A can be selected in one of 4 operating modes by setting

the timer A mode register.

(1) Timer mode

Timer A counts the selected by the timer A count source selection

bit. Each time the count clock is input, the contents of Timer A is

decremented by 1. When the contents of Timer A reach “000016”,

an underflow occurs at the next count clock, and the timer A latch

is reloaded into Timer A. The division ratio of Timer A is 1/(n+1)

provided that the value of Timer A is n.

(2) Period measurement mode

In the period measurement mode, the pulse period input from the

P00/CNTR1 pin is measured.

CNTR1 interrupt request is generated at rising/falling edge of

CNTR1 pin input signal. Simultaneously, the value in the timer A

latch is reloaded in Timer A and count continues. The active edge

of CNTR1 pin input signal can be selected from rising or falling by

the CNTR1 active edge switch bit .The count value when trigger

input from CNTR1 pin is accepted is retained until Timer A is read

once.

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REJ03B0108-0102

(3) Event counter mode

Timer A counts signals input from the P00/CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode.

The active edge of CNTR1 pin input signal can be selected from

rising or falling by the CNTR1 active edge switch bit .

(4) Pulse width HL continuously measurement mode

In the pulse width HL continuously measurement mode, the pulse

width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode.

The count value when trigger input from the CNTR1 pin is ac-

cepted is retained until Timer A is read once.

Timer A can stop counting by setting “1” to the timer A count stop

bit in any mode.

Also, when Timer A underflows, the timer A interrupt request bit is

set to “1”.

Note on Timer A is described below;

■ Note on Timer A

CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit.

When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at

the falling edge of the CNTR1 pin input signal. When this bit is “1”,

the CNTR1 interrupt request bit is set to “1” at the rising edge of

the CNTR1 pin input signal.

However, in the pulse width HL continuously measurement mode,

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

Fig. 19 Structure of timer A mode register

Fig. 20 Timer count source set register 2

Timer A mode register

(TAM : address 001D

, initial value: 00

)

b7 b0

Disable (return “0” when read)

Timer A operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuously

measurement mode

CNTR

active edge switch bit

0 : Count at rising edge in event counter mode

Measure the falling edge period in period

measurement mode

Falling edge active for CNTR

interrupt

1 : Count at falling edge in event counter mode

Measure the rising edge period in period

measurement mode

Rising edge active for CNTR

interrupt

Timer A count stop bit

0 : Count start

1 : Count stop

Timer count source set register 2

(TCSS2 : address 002F

, initial value: 00

)

b7 b0

Timer 1 count source selection bits

b1 b0

0 0 : f(X

)/16

0 1 : f(X

)/2

1 0 : On-chip oscillator output

1 1 : Disable

Note : System operates using an on-chip oscillator as a count source

by setting the on-chip oscillator to oscillation enabled by bit 3

of CPUM.

Disable (return “0” when read)

Timer A count source selection bits

b3 b2

0 0 : f(X

)/16

0 1 : f(X

)/2

1 0 : On-chip oscillator output

1 1 : Disable

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REJ03B0108-0102

(4) Pulse width measurement mode

In the pulse width measurement mode, the pulse width of the sig-

nal input to P14/CNTR0 pin is measured.

The operation of Timer X can be controlled by the level of the sig-

nal input from the CNTR0 pin.

When the CNTR0 active edge switch bit is “0”, the signal selected

by the timer X count source selection bit is counted while the input

signal level of CNTR0 pin is “H”. The count is stopped while the

pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the

signal selected by the timer X count source selection bit is

counted while the input signal level of CNTR0 pin is “L”. The count

is stopped while the pin is “H”.

Timer X can stop counting by setting “1” to the timer X count stop

bit in any mode.

Also, when Timer X underflows, the timer X interrupt request bit is

set to “1”.

Note on Timer X is described below;

■ Note on Timer X

CNTR0 interrupt active edge selection

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at

the falling edge of CNTR0 pin input signal. When this bit is “1”, the

CNTR0 interrupt request bit is set to “1” at the rising edge of

CNTR0 pin input signal.

●Timer X

Timer X is an 8-bit timer and counts the prescaler X output.

When Timer X underflows, the timer X interrupt request bit is set

to “1”.

Prescaler X is an 8-bit prescaler and counts the signal selected by

the timer X count source selection bit.

Prescaler X and Timer X have the prescaler X latch and the timer

X latch to retain the reload value, respectively. The value of

prescaler X latch is set to Prescaler X when Prescaler X

underflows. The value of timer X latch is set to Timer X when

Timer X underflows.

When writing to Prescaler X (PREX) and Timer X (TX) is ex-

ecuted, writing to “latch only” or “latch and prescaler (timer)” can

be selected by the setting value of the timer X write control bit.

When reading from Prescaler X (PREX) and Timer X (TX) is ex-

ecuted, each count value is read out.

Timer X can be selected in one of 4 operating modes by setting

the timer X operating mode bits of the timer X mode register.

(1) Timer mode

Prescaler X counts the count source selected by the timer X count

source selection bits. Each time the count clock is input, the con-

tents of Prescaler X is decremented by 1. When the contents of

Prescaler X reach “0016”, an underflow occurs at the next count

clock, and the prescaler X latch is reloaded into Prescaler X and

count continues. The division ratio of Prescaler X is 1/(n+1) pro-

vided that the value of Prescaler X is n.

The contents of Timer X is decremented by 1 each time the under-

flow signal of Prescaler X is input. When the contents of Timer X

reach “0016”, an underflow occurs at the next count clock, and the

timer X latch is reloaded into Timer X and count continues. The di-

vision ratio of Timer X is 1/(m+1) provided that the value of Timer

X is m. Accordingly, the division ratio of Prescaler X and Timer X is

1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and

the value of Timer X is m.

(2) Pulse output mode

In the pulse output mode, the waveform whose polarity is inverted

each time timer X underflows is output from the CNTR0 pin.

The output level of CNTR0 pin can be selected by the CNTR0 ac-

tive edge switch bit. When the CNTR0 active edge switch bit is “0”,

the output of CNTR0 pin is started at “H” level. When this bit is “1”,

the output is started at “L” level.

Also, the inverted waveform of pulse output from CNTR0 pin can

be output from TXOUT pin by setting “1” to the P03/TXOUT output

valid bit.

When using a timer in this mode, set the port P14 and P03 direc-

tion registers to output mode.

(3) Event counter mode

The timer A counts signals input from the P14/CNTR0 pin.

Except for this, the operation in event counter mode is the same

as in timer mode.

The active edge of CNTR0 pin input signal can be selected from

rising or falling by the CNTR0 active edge switch bit .

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 25 of 61

REJ03B0108-0102

Fig. 21 Structure of timer X mode register

Fig. 22 Timer count source set register 1

Timer X mode register

(TXM : address 002B16, initial value: 0016)

Timer X operating mode bits

b1 b0

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

CNTR0 active edge switch bit

0 : Interrupt at falling edge

Count at rising edge

(in event counter mode)

1 : Interrupt at rising edge

Count at falling edge

(in event counter mode)

Timer X count stop bit

0 : Count start

1 : Count stop

P03/TXOUT output valid bit

0 : Output invalid (I/O port)

1 : Output valid (Inverted CNTR0 output)

Disable (return “0” when read)

b7 b0

Timer count source set register 1

(TCSS1 : address 002E

, initial value: 00

)

b7 b0

Timer X count source selection bits

b1 b0

0 0 : f(X

)/16

0 1 : f(X

)/2

1 0 : f(X

) (Note)

1 1 : Not available

Note : f(X

) can be used as timer X count source when using

a ceramic resonator or on-chip oscillator.

use

osc

ill

Disable (return “0” when read)

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 26 of 61

REJ03B0108-0102

Fig. 23 Block diagram of timer 1 and timer A

Timer A (low-order) latch (8)

Timer A (low-order) (8)

Timer A (high-order) latch (8)

Timer A (high-order) (8)

Data bus

/CNTR

CNTR

active

edge switch bit

Rising edge detected

Falling edge detected

Timer A operation mode bit

Timer A count

stop bit

Prescaler 1 latch (8)

Prescaler 1 (8)

Timer 1 latch (8)

Timer 1 (8)

Data bus

Timer A interrupt

request bit

Timer 1 interrupt

request bit

Pulse width HL

continuously

measurement mode

Period measurement mode

f(X

)/16

f(X

)/2

On-chip oscillator clock RING

f(X

)/16

f(X

)/2

On-chip oscillator clock RING

Fig. 24 Block diagram of timer X

P14/CNTR0

f(XIN)/16

f(XIN)/2

Timer X

interrupt

request bit

Toggle flip-flop

Timer X count stop bit

Pulse width

measurement

mode

Event

counter

mode CNTR0

interrupt

request bit

Pulse output mode

Port P14

latch

Port P14 direction

CNTR0 active

edge switch bit

Timer mode

Pulse output

mode

CNTR0 active

edge switch bit

Timer X count

source selection bits

f(XIN)

P03/TXOUT

Prescaler X latch (8)

Prescaler X (8)

Timer X latch (8)

Timer X (8)

Data bus

“0”

“1”

“0”

“1”

Writing to timer X latch

/TX

OUT

output valid

Port P03 latch

Port P03

direction

Pulse output mode

Timer X write control bit

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 27 of 61

REJ03B0108-0102

Fig. 25 Block diagram of clock synchronous serial I/O

Fig. 26 Operation of clock synchronous serial I/O function

Serial Interface

●Serial I/O

Serial I/O can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer is also provided for

baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the

serial I/O mode selection bit of the serial I/O control register (bit 6)

to “1”.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

1/4

F/F

CLK

Serial I/O status register

Serial I/O control register

RDY

Receive buffer register

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O synchronous

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C

BRG count source selection bit

Clock control circuit

Falling-edge detector

Transmit buffer register

Data bus Address 0018

Shift clock Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 0019

Data bus

Address 001A

Transmit shift register

RBF = 1

TSC = 1

TBE = 0 TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

Write pulse to receive/transmit

buffer register (address 0018

)

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after

the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial

data is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal

RDY

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 28 of 61

REJ03B0108-0102

Fig. 27 Block diagram of UART serial I/O

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O mode selection bit of the serial I/O control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 28 Operation of UART serial I/O function

1/4

PE FE

1/16

Data bus

Receive buffer register

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C

ST/SP/PA generator

Transmit buffer register

Data bus

Transmit shift register

Address

001816

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address

001916

ST detector

SP detector UART control register

Address 001B

Character length selection bit

Address 001A

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O control register

CLK

Serial I/O status register

TSC=0

TBE=1

RBF=0

TBE=0 TBE=0

RBF=1 RBF=1

STD0D1SP D0D1

ST SP

TBE=1 TSC=1

STD0D1SP D0D1

ST SP

Transmit or receive clock

Transmit buffer write

signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1.”

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

✽

Serial output TXD

Serial input RXD

Receive buffer read

signal

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 29 of 61

REJ03B0108-0102

[Transmit buffer register/receive buffer register (TB/RB)]

001816

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer is write-only and

the receive buffer is read-only. If a character bit length is 7 bits, the

MSB of data stored in the receive buffer is “0”.

[Serial I/O status register (SIOSTS)] 001916

The read-only serial I/O status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer register is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE

(bit 7 of the serial I/O control register) also clears all the status

flags, including the error flags.

Bits 0 to 6 of the serial I/O status register are initialized to “0” at re-

set, but if the transmit enable bit of the serial I/O control register

has been set to “1”, the transmit shift completion flag (bit 2) and

the transmit buffer empty flag (bit 0) become “1”.

[Serial I/O control register (SIOCON)] 001A16

The serial I/O control register consists of eight control bits for the

serial I/O function.

[UART control register (UARTCON)] 001B16

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer and one bit (bit 4) which is al-

ways valid and sets the output structure of the P11/TXD pin.

[Baud rate generator (BRG)] 001C16

The baud rate generator determines the baud rate for serial transfer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate generator.

■ Notes on serial I/O

• Serial I/O interrupt

When setting the transmit enable bit to “1”, the serial I/O transmit

interrupt request bit is automatically set to “1”. When not requiring

the interrupt occurrence synchronized with the transmission en-

abled, take the following sequence.

➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).

➁ Set the transmit enable bit to “1”.

➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or

more instructions have been executed.

➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).

• I/O pin function when serial I/O is enabled.

The functions of P12 and P13 are switched with the setting values

of a serial I/O mode selection bit and a serial I/O synchronous

clock selection bit as follows.

(1) Serial I/O mode selection bit → “1” :

Clock synchronous type serial I/O is selected.

Setup of a serial I/O synchronous clock selection bit

“0” : P12 pin turns into an output pin of a synchronous clock.

“1” : P12 pin turns into an input pin of a synchronous clock.

Setup of a SRDY output enable bit (SRDY)

“0” : P13 pin can be used as a normal I/O pin.

“1” : P13 pin turns into a SRDY output pin.

(2) Serial I/O mode selection bit → “0” :

Clock asynchronous (UART) type serial I/O is selected.

Setup of a serial I/O synchronous clock selection bit

“0”: P12 pin can be used as a normal I/O pin.

“1”: P12 pin turns into an input pin of an external clock.

When clock asynchronous (UART) type serial I/O is selected, it is

P13 pin. It can be used as a normal I/O pin.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 30 of 61

REJ03B0108-0102

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

“

”

)

b0 b

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

b7 UART control register

(

)

(

)

(

)

(

)

11/

TXD1

(

)

(

)

(

)

(

“

”

)

(

(UARTCON : address 001B16, initial value: E016)

Fig. 29 Structure of serial I/O-related registers

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 31 of 61

REJ03B0108-0102

A/D Converter

The functional blocks of the A/D converter are described below.

[A/D conversion register] AD

The A/D conversion register is a read-only register that stores the

result of A/D conversion. Do not read out this register during an A/

D conversion.

[A/D control register] ADCON

The A/D control register controls the A/D converter. Bit 2 to 0 are

analog input pin selection bits. Bit 4 is the AD conversion comple-

tion bit. The value of this bit remains at “0” during A/D conversion,

and changes to “1” at completion of A/D conversion.

A/D conversion is started by setting this bit to “0”.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between

AVSS and VREF by 256, and outputs the divided voltages.

[Channel selector]

The channel selector selects one of ports P25/AN5 to P20/AN0,

and inputs the voltage to the comparator.

[Comparator and control circuit]

The comparator and control circuit compares an analog input volt-

age with the comparison voltage and stores its result into the A/D

conversion register. When A/D conversion is completed, the con-

trol circuit sets the AD conversion completion bit and the AD

interrupt request bit to “1”. Because the comparator is constructed

linked to a capacitor, set f(XIN) to 500 kHz or more during A/D con-

version.

Fig. 30 Structure of A/D control register

Fig. 31 Block diagram of A/D converter

b7 b0

Analog input pin selection bits

A/D control register

(ADCON : address 0034

, initial value: 10

)

Disable (returns “0” when read)

1 : Conversion completed

0 : Conversion in progress

AD conversion completion bit

Disable (returns “0” when read)

111 : Disable

110 : Disable

101 : P2

/AN

100 : P2

/AN

011 : P2

/AN

010 : P2

/AN

001 : P2

/AN

000 : P2

/AN

A/D control register

(Address 003416)

Channel selector

A/D control circuit

Resistor ladder

VREF

Comparator

A/D interrupt request

b7 b0

Data bus

P20/AN0

P21/AN1

P22/AN2

P23/AN3

P24/AN4

P25/AN5

(Address 003516)

VSS

A/D conversion register (low-order)

■ Notes on A/D converter

The comparator uses internal capacitors whose charge will be lost

if the clock frequency is too low.

Make sure that f(XIN) is 500 kHz or more during A/D conversion.

As for AD translation accuracy, on the following operating condi-

tions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sen-

sitive to noise when VREF voltage is set up lower than Vcc

voltage, accuracy may become low rather than the case

where VREF voltage and Vcc voltage are set up to the same

value..

(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the

low temperature may become extremely low compared with

that at room temperature. When the system would be used at

low temperature, the use at VREF=3.0 V or more is recom-

mended.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 32 of 61

REJ03B0108-0102

Watchdog Timer

The watchdog timer gives a means for returning to a reset status

when the program fails to run on its normal loop due to a runaway.

The watchdog timer consists of an 8-bit watchdog timer H and an

8-bit watchdog timer L, being a 16-bit counter.

Standard operation of watchdog timer

The watchdog timer stops when the watchdog timer control regis-

ter (address 003916) is not set after reset. Writing an optional

value to the watchdog timer control register (address 003916)

causes the watchdog timer to start to count down. When the

watchdog timer H underflows, an internal reset occurs. Accord-

ingly, it is programmed that the watchdog timer control register

(address 003916) can be set before an underflow occurs.

When the watchdog timer control register (address 003916) is

read, the values of the high-order 6-bit of the watchdog timer H,

STP instruction disable bit and watchdog timer H count source se-

lection bit are read.

Initial value of watchdog timer

By a reset or writing to the watchdog timer control register (ad-

dress 003916), the watchdog timer H is set to “FF16” and the

watchdog timer L is set to “FF16”.

Operation of watchdog timer H count source selection bit

A watchdog timer H count source can be selected by bit 7 of the

watchdog timer control register (address 003916). When this bit is

“0”, the count source becomes a watchdog timer L underflow sig-

nal. The detection time is 131.072 ms at f(XIN)=8 MHz.

When this bit is “1”, the count source becomes f(XIN)/16. In this

case, the detection time is 512 µs at f(XIN)=8 MHz.

This bit is cleared to “0” after reset.

Operation of STP instruction disable bit

When the watchdog timer is in operation, the STP instruction can

be disabled by bit 6 of the watchdog timer control register (ad-

dress 003916).

When this bit is “0”, the STP instruction is enabled.

When this bit is “1”, the STP instruction is disabled, and an inter-

nal reset occurs if the STP instruction is executed.

Once this bit is set to “1”, it cannot be changed to “0” by program.

This bit is cleared to “0” after reset.

Fig. 32 Block diagram of watchdog timer

Fig. 33 Structure of watchdog timer control register

XIN

Data bus

“0”

“1”

1/16

Watchdog timer H count

source selection bit

Reset

circuit

STP Instruction disable bit

Watchdog timer H (8)

Write "FF16" to the

watchdog timer

control register

Internal

reset

RESET

Watchdog timer L (8)

STP Instruction

Write “FF16” to the

watchdog timer

control register

Watchdog timer control register

(WDTCON: address 003916, initial value: 3F16)

Watchdog timer H (read only for high-order 6-bit)

STP instruction disable bit

0 : STP instruction enabled

1 : STP instruction disabled

Watchdog timer H count source selection bit

0 : Watchdog timer L underflow

(XIN)/16

b7 b0

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 33 of 61

REJ03B0108-0102

Fig. 34 Example of reset circuit

Fig. 35 Timing diagram at reset

(Note)

0.2 VCC

0 V

Poweron

VCCRESET

VCC

RESET

Power source

voltage

detection circuit

Power source

voltage

Reset input

voltage

Note : Reset release voltage Vcc 2.2V

Data

Address

8-13 clock cycles

Reset address from the

vector table

1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock

at average of Vcc = 5 V.

2 : The mark “?” means that the address is changeable depending on the previous state.

3 : These are all internal signals except RESET.

Notes

?? FFFC FFFD

ADH,ADL

???

?? AD

???

Clock from

on-chip oscillator

RING φ

RESET

OUT

SYNC

Reset Circuit

The 7544 group starts operation by the on-chip oscillator after sys-

tem is released from reset.

Accordingly, when the rising of power supply voltage passes 2.2V,

set the reset input voltage to become below 0.2Vcc (0.44V).

Moreover, switch CPU clock to the external oscillator after the ris-

ing of power supply voltage passes the minimum operation

voltage and after an oscillation is stabilized.

Note: The minimum operation voltage is decided by the division

ratio of an external oscillator's frequency and a CPU clock.

Decide on an external oscillator's oscillation stabilizing time

after fully evaluating an oscillator's stabilizing time used.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 34 of 61

REJ03B0108-0102

Fig. 36 Internal status of microcomputer at reset

X : Undefined

The content of other registers is undefined when the microcomputer is reset.

The initial values must be surely set bifore you use it.

Address

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

Port P0 direction register

Port P1 direction register

Port P2 direction register

Port P3 direction register

Pull-up control register

Port P1P3 control register

Serial I/O status register

Serial I/O control register

UART control registe

Timer A mode register

Timer A (low-order)

Timer A (high-order)

Prescaler 1

Timer 1

Timer X mode register

Prescaler X

Timer X

Timer count source set register 1

Timer count source set register 2

A/D control register

MISRG

Watchdog timer control register

Interrupt edge selection register

CPU mode register

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

Processor status register

Program counter

000116

000316

000516

000716

001616

001716

001916

001A16

001B16

001D16

001E16

001F16

002816

002916

002B16

002C16

002D16

002E16

002F16

003416

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

(PS)

(PCH)

(PCL)

0016

XX 0000X0

XX 000000

0X 0000X0

0016

10 000000

11 000010

0016

FF16

00 000100

0016

FF16

0016

00 000001

0016

00 111111

0016

10 000000

0016

XX X1XXXX

Contents of address FFFD16

Contents of address FFFC16

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 35 of 61

REJ03B0108-0102

Fig. 38 External circuit of ceramic resonator and quartz-crystal

oscillator

Fig. 40 External clock input circuit

Fig. 37 Processing of X

and X

OUT

pins at on-chip oscillator operation

Clock Generating Circuit

An oscillation circuit can be formed by connecting a resonator be-

tween XIN and XOUT, and an RC oscillation circuit can be formed

by connecting a resistor and a capacitor.

Use the circuit constants in accordance with the resonator

manufacturer's recommended values.

No external resistor is needed between XIN and XOUT since a

feed-back resistor exists on-chip. (An external feed-back resistor

may be needed depending on conditions.)

(1) On-chip oscillator operation

When the MCU operates by the on-chip oscillator for the main

clock, connect XIN pin to VCC and leave XOUT pin open.

The clock frequency of the on-chip oscillator depends on the sup-

ply voltage and the operation temperature range.

Be careful that variable frequencies when designing application

products.

(2) Ceramic resonator and quartz-crystal oscillator

When the ceramic resonator and quartz-crystal oscillator is used

for the main clock, connect the ceramic/quartz-crystal oscillator

and the external circuit to pins XIN and XOUT at the shortest dis-

tance. A feedback resistor is built in between pins XIN and XOUT.

(3) RC oscillation

When the RC oscillation is used for the main clock, connect the

XIN pin and XOUT pin to the external circuit of resistor R and the

capacitor C at the shortest distance.

The frequency is affected by a capacitor, a resistor and a micro-

computer.

So, set the constants within the range of the frequency limits.

(4) External clock

When the external signal clock is used for the main clock, connect

the XIN pin to the clock source and leave XOUT pin open.

Insert a damping resistor if required.

The resistance will vary depending on the oscillator and

the oscillation drive capacity setting.

Use the value recommended by the maker of the oscillator.

Also, if the oscillator manufacturer ’s data sheet specifies

that a feedback resistor be added external to the chip

through a feedback resistor exists on-chip, insert a feed-

back resistor between XIN and XOUT following the

instruction.

Note:

Connect the external

circuit of resistor R

and the capacitor C at

the shortest distance.

The frequency is af-

fected by a capacitor,

a resistor and a micro-

computer.

So, set the constants

within the range of the

frequency limits.

Note:

The clock frequency of the

on-chip oscillator depends

on the supply voltage and

the operation temperature

range.

Be careful that variable fre-

quencies and obtain the

sufficient margin.

Note:

OUT

M37544

OUT

M37544

Rd (Note)

XIN XOUT

M37544

XIN XOUT

External oscillation

circuit

VCC

VSS

Open

M37544

Fig. 39 External circuit of RC oscillation

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 36 of 61

REJ03B0108-0102

Fig. 41 Structure of CPU mode register

(1) Oscillation control

• Stop mode

When the STP instruction is executed, the internal clock φ stops at

an “H” level and the XIN oscillator stops. At this time, timer 1 is set

to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-

bilization time set bit after release of the STP instruction is “0”. On

the other hand, timer 1 and prescaler 1 are not set when the

above bit is “1”. Accordingly, set the wait time fit for the oscillation

stabilization time of the oscillator to be used. Single selected by

the timer 1 count source selection bit is connected to the input of

prescaler 1. When an external interrupt is accepted, oscillation is

restarted but the internal clock φ remains at “H” until timer 1

underflows. As soon as timer 1 underflows, the internal clock φ is

supplied. This is because when a ceramic/quartz-crystal oscillator

is used, some time is required until a start of oscillation. In case

oscillation is restarted by reset, no wait time is generated. So ap-

______

ply an “L” level to the RESET pin while oscillation becomes stable.

Also, the STP instruction cannot be used while CPU is operating

by an on-chip oscillator.

• Wait mode

If the WIT instruction is executed, the internal clock φ stops at an

“H” level, but the oscillator does not stop. The internal clock re-

starts if a reset occurs or when an interrupt is received. Since the

oscillator does not stop, normal operation can be started immedi-

ately after the clock is restarted. To ensure that interrupts will be

received to release the STP or WIT state, interrupt enable bits

must be set to “1” before the STP or WIT instruction is executed.

■ Notes on clock generating circuit

For use with the oscillation stabilization set bit after release of the

STP instruction set to “1”, set values in timer 1 and prescaler 1 af-

ter fully appreciating the oscillation stabilization time of the

oscillator to be used.

• Switch of ceramic/quartz-crystal and RC oscillations

After releasing reset the operation starts by starting an on-chip os-

cillator. Then, a ceramic/quartz-crystal oscillation or an RC

oscillation is selected by setting bit 5 of the CPU mode register.

• Double-speed mode

When a ceramic/quartz-crystal oscillation is selected, a double-

speed mode can be used. Do not use it when an RC oscillation is

selected.

• CPU mode register

Bits 5, 1 and 0 of CPU mode register are used to select oscillation

mode and to control operation modes of the microcomputer. In or-

der to prevent the dead-lock by error-writing (ex. program

run-away), these bits can be rewritten only once after releasing re-

set. After rewriting it is disable to write any data to the bit. (The

emulator MCU “M37544RSS” is excluded.)

Also, when the read-modify-write instructions (SEB, CLB) are ex-

ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

• Clock division ratio, XIN oscillation control, on-chip oscillator con-

trol

The state transition shown in Fig. 45 can be performed by setting

the clock division ratio selection bits (bits 7 and 6), XIN oscillation

control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of

CPU mode register. Be careful of notes on use in Fig. 45.

Processor mode bits (Note 1)

b1 b0

0 0 Single-chip mode

0 1

1 0

1 1

Not available

b7 b0

2: These bits are used only when a ceramic

/quartz-crystal

oscillation is selected.

Note 1: The bit can be rewritten only once after releasing reset. After rewriting

it is disable to write any data to the bit. However, by reset the bit is

initialized and can be rewritten, again.

(It is not disable to write any data to the bit for emulator MCU

“M37544RSS”.)

Do not use these when an RC oscillation is selected.

Oscillation mode selection bit (Note 1)

0 : Ceramic/quartz-crystal oscillation

1 : RC oscillation

CPU mode register

(CPUM: address 003B

, initial value: 80

)

Stack page selection bit

0 : 0 page

1 : 1 page

Clock division ratio selection bits

b7 b6

0 0 : f(φ) = f(X

)/2 (High-speed mode)

0 1 : f(φ) = f(X

)/8 (Middle-speed mode)

1 0 : applied from on-chip oscillator

1 1 : f(φ) = f(X

) (Double-speed mode)(Note 2)

On-chip oscillator oscillation control bit

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

oscillation control bit

0 : Ceramic/quartz-crystal or RC oscillation enabled

1 : Ceramic/quartz-crystal or RC oscillation stop

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 37 of 61

REJ03B0108-0102

● Oscillation stop detection circuit

The oscillation stop detection circuit is used for reset occurrence

when a ceramic resonator or an oscillation circuit stops by discon-

nection. When internal reset occurs, reset because of oscillation

stop can be detected by setting “1” to the oscillation stop detection

status bit.

Also, when using the oscillation stop detection circuit, an on-chip

oscillator is required.

Figure 45 shows the state transition.

The oscillation stop detection status bit retains “1”, not initialized,

when the oscillation stop reset occurs. The oscillation stop detec-

tion status bit is initialized to “0” when the external reset occurs.

Accordingly, reset by oscillation stop can be confirmed by using

this bit.

■ Notes on Oscillation Stop Detection Circuit

• Oscillation stop detection status bit is initialized by the following

operation.

(1) External reset

(2) Write “0” data to the ceramic or RC oscillation stop detection

function active bit.

• The oscillation stop detection circuit is not included in the emu-

lator MCU “M37544RSS”.

Fig. 42 Structure of MISRG

MISRG(address 0038

, initial value: 00

)

b7 b0

Oscillation stabilization time set bit after

release of the STP instruction

0: Set “01

” in timer1, and “FF

”

in prescaler 1 automatically

1: Not set automatically

Ceramic/quartz-crystal or RC oscillation

stop detection function active bit

0: Detection function inactive

1: Detection function active

Reserved bits (return “0” when read)

(Do not write “1” to these bits)

Disable (return “0” when read)

Oscillation stop detection status bit

0: Oscillation stop not detected

1: Oscillation stop detected

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REJ03B0108-0102

Fig. 43 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator)

Fig. 44 Block diagram of internal clock generating circuit (for RC oscillation)

1/2

(Note)

1/4 1/2

WIT

instruction STP instruction

Timing φ

(Internal clock)

STP instruction

Interrupt request

Reset

Interrupt disable flag l

High-speed mode

Middle-speed mode

Clock division

ratio selection bit

Double-speed mode

On-chip oscillator mode

On-chip oscillator

RING

OUT

1/8

Clock division ratio selection bit

Middle-, high-, low-speed mode

On-chip oscillator mode

RESET

Prescaler 1 Timer 1

Note: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed

depending on conditions.

1/2

1/4 1/2

WIT

instruction STP instruction

Timing φ

(Internal clock)

STP instruction

Interru

t re

uest

Reset

Interrupt disable flag l

High-speed mode

Middle-speed mode

Clock division

ratio selection bit

Double-speed mode

On-chip oscillator mode

On-chip oscillator

RING

OUT

Delay

1/8

Clock division ratio selection bit

Middle-, high-, low-speed mode

On-chip

oscillator

mode

RESET

Prescaler 1 Timer 1

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 39 of 61

REJ03B0108-0102

Fig. 45 State transition

Stop mode Wait mode

WIT

instruction

Oscillation stop detection circuit valid

CPUM

←1

MISRG

¨1

Interrupt

STP

instruction

WIT

instruction

Interrupt

MISRG

←0

CPUM

¨1

CPUM

←0

CPUM

¨10

CPUM

¨00

(Note 2)

CPUM

¨0

MISRG

¨1

MISRG

¨0

Reset released

State 1

Operation clock source:

f(X

) (Note 1)

f(X

) oscillation enabled

On-chip oscillator stop

State 2

Operation clock source:

f(X

) (Note 1)

f(X

) oscillation enabled

On-chip oscillator enabled

State 3

Operation clock source:

On-chip oscillator (Note 3)

f(X

) oscillation enabled

On-chip oscillator enabled

State 4

Operation clock source:

On-chip oscillator (Note 3)

f(X

) oscillation stop

On-chip oscillator enabled

Notes on switch of clock

(1) In operation clock source = f(X

), the following can be

selected for the CPU clock division ratio.

● f(X

)/2 (high-speed mode)

● f(X

)/8 (middle-speed mode)

● f(X

) (double-speed mode, only at a ceramic/quartz-crystal

oscillation)

(2) Execute the state transition state 3 to state 2 or

state 3’ to state 2’ after stabilizing X

oscillation.

(3) In operation clock source = on-chip oscillator, the middle-

speed mode is selected for the CPU clock division ratio.

(4) When the state transition state 2 → state 3 → state 4

is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

• CPUM76 → 10

(State 2 → state 3)

• NOP instruction

• CPUM4 → 1

(State 3 → state 4)

Double-speed mode at on-chip oscillator: NOP ✕ 3

High-speed mode at on-chip oscillator: NOP ✕ 1

Reset state

CPUM

¨10

CPUM

←00

(Note 2)

State 2’

Operation clock source:

f(X

) (Note 1)

f(X

) oscillation enabled

On-chip oscillator enabled

State 3’

Operation clock source:

On-chip oscillator (Note 3)

f(X

) oscillation enabled

On-chip oscillator enabled

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 40 of 61

REJ03B0108-0102

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after reset are

undefined except for the interrupt disable flag I which is “1”. After

reset, initialize flags which affect program execution. In particular,

it is essential to initialize the T flag and the D flag because of their

effect on calculations.

Interrupts

The contents of the interrupt request bit do not change even if the

BBC or BBS instruction is executed immediately after they are

changed by program because this instruction is executed for the

previous contents. For executing the instruction for the changed

contents, execute one instruction before executing the BBC or

BBS instruction.

Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag

D to “1”, then execute the ADC instruction or SBC instruction. In

this case, execute SEC instruction, CLC instruction or CLD in-

struction after executing one instruction before the ADC instruction

or SBC instruction.

• In the decimal mode, the values of the N (negative), V (overflow)

and Z (zero) flags are invalid.

Ports

• The values of the port direction registers cannot be read.

That is, it is impossible to use the LDA instruction, memory opera-

tion instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions such

as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read/modify/write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

A/D Conversion

Do not execute the STP instruction during A/D conversion.

Instruction Execution Timing

The instruction execution time can be obtained by multiplying the

frequency of the internal clock φ by the number of cycles men-

tioned in the machine-language instruction table.

The frequency of the internal clock φ is the same as that of the XIN

in double-speed mode, twice the XIN cycle in high-speed mode

and 8 times the XIN cycle in middle-speed mode.

CPU Mode Register

The oscillation mode selection bit and processor mode bits can be

rewritten only once after releasing reset. However, after rewriting it

is disable to write any value to the bit. (Emulator MCU is ex-

cluded.)

When a ceramic / quartz-crystal oscillation is selected, a double-

speed mode of the clock division ratio selection bits can be used.

Do not use it when an RC oscillation is selected.

State transition

Do not stop the clock selected as the operation clock because of

setting of CM3, 4.

NOTES ON HARDWARE

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the

capacitor to as close as possible. For bypass capacitor which

should not be located too far from the pins to be connected, a ce-

ramic capacitor of 0.01 µF to 0.1 µF is recommended.

Handling of CNVss Pin

The CNVss pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVss

pin and Vss pin with 1 to 10 kΩ resistance.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 41 of 61

REJ03B0108-0102

NOTES ON USE

Countermeasures against noise

1. Shortest wiring length

(1) Package

Select the smallest possible package to make the total wiring

length short.

The wiring length depends on a microcomputer package. Use of a

small package, for example QFP and not DIP, makes the total wir-

ing length short to reduce influence of noise.

(3) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as

short as possible.

• Make the length of wiring (within 20 mm) across the grounding

lead of a capacitor which is connected to an oscillator and the

VSS pin of a microcomputer as short as possible.

• Separate the VSS pattern only for oscillation from other VSS pat-

terns.

If noise enters clock I/O pins, clock waveforms may be deformed.

This may cause a program failure or program runaway. Also, if a

potential difference is caused by the noise between the VSS level

of a microcomputer and the VSS level of an oscillator, the correct

clock will not be input in the microcomputer.

(2) Wiring for RESET pin

Make the length of wiring which is connected to the RESET pin as

short as possible. Especially, connect a capacitor across the

RESET pin and the VSS pin with the shortest possible wiring

(within 20mm).

The width of a pulse input into the RESET pin is determined by the

timing necessary conditions. If noise having a shorter pulse width

than the standard is input to the RESET pin, the reset is released

before the internal state of the microcomputer is completely initial-

ized. This may cause a program runaway.

Fig. 48 Wiring for clock I/O pins

Fig. 46 Selection of packages

Fig. 47 Wiring for the RESET pin

RESET

Reset

circuit

Noise

VSSVSS

Reset

circuit

VSS

RESET

VSS

N.G.

O.K.

Noise

XIN

XOUT

VSS

XIN

XOUT

VSS

N.G. O.K.

DIP

SDIP

SOP

QFP

(4) Wiring to VPP pin

Connect VPP pin to a GND pattern at the shortest distance.

The GND pattern is required to be as close as possible to the

GND supplied to VSS.

In order to improve the noise reduction, to connect a 1 k to 5 kΩ

resistor serially to the VPP pin - GND line may be valid.

As well as the above-mentioned, in this case, connect to a GND

pattern at the shortest distance. The GND pattern is required to be

as close as possible to the GND supplied to VSS.

The VPP pin of the QzROM is the power source input pin for the

built-in QzROM. When programming in the built-in QzROM, the

impedance of the VPP pin is low to allow the electric current for

writing flow into the QzROM. Because of this, noise can enter eas-

ily. If noise enters the VPP pin, abnormal instruction codes or data

are read from the built-in QzROM, which may cause a program

runaway.

Fig. 49 Wiring for the VPP pin of the QzPROM

CNV

shortest

distance

About 1 to 5kΩ

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 42 of 61

REJ03B0108-0102

Fig. 50 Bypass capacitor across the VSS line and the VCC line

2. Connection of bypass capacitor across VSS line and VCC line

Connect an approximately 0.1

F bypass capacitor across the VSS

line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin

at equal length.

• Connect a bypass capacitor across the VSS pin and the VCC pin

with the shortest possible wiring.

• Use lines with a larger diameter than other signal lines for VSS

line and VCC line.

• Connect the power source wiring via a bypass capacitor to the

VSS pin and the VCC pin.

3. Wiring to analog input pins

• Connect an approximately 100 Ω to 1 kΩ resistor to an analog

signal line which is connected to an analog input pin in series.

Besides, connect the resistor to the microcomputer as close as

possible.

• Connect an approximately 1000 pF capacitor across the Vss pin

and the analog input pin. Besides, connect the capacitor to the

Vss pin as close as possible. Also, connect the capacitor across

the analog input pin and the Vss pin at equal length.

Signals which is input in an analog input pin (such as an A/D con-

verter/comparator input pin) are usually output signals from

sensor. The sensor which detects a change of event is installed far

from the printed circuit board with a microcomputer, the wiring to

an analog input pin is longer necessarily. This long wiring func-

tions as an antenna which feeds noise into the microcomputer,

which causes noise to an analog input pin.

Fig. 51 Analog signal line and a resistor and a capacitor

• The analog input pin is connected to the capacitor of a voltage

comparator. Accordingly, sufficient accuracy may not be ob-

tained by the charge/discharge current at the time of A/D

conversion when the analog signal source of high-impedance is

connected to an analog input pin. In order to obtain the A/D con-

version result stabilized more, please lower the impedance of an

analog signal source, or add the smoothing capacitor to an ana-

log input pin.

N.G. O.K.

Analog

input pin

Noise

Thermistor

Microcomputer

N.G. O.K.

(Note)

Note : The resistor is used for dividing

resistance with a thermistor.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 43 of 61

REJ03B0108-0102

4. Oscillator concerns

So that the product obtains the stabilized operation clock on the

user system and its condition, contact the resonator manufacturer

and select the resonator and oscillation circuit constants.

Be careful especially when range of voltage and temperature is

wide.

Take care to prevent an oscillator that generates clocks for a mi-

crocomputer operation from being affected by other signals.

(1) Keeping oscillator away from large current signal lines

Install a microcomputer (and especially an oscillator) as far as

possible from signal lines where a current larger than the toler-

ance of current value flows.

In the system using a microcomputer, there are signal lines for

controlling motors, LEDs, and thermal heads or others. When a

large current flows through those signal lines, strong noise occurs

because of mutual inductance.

(2) Installing oscillator away from signal lines where potential lev-

els change frequently

Install an oscillator and a connecting pattern of an oscillator away

from signal lines where potential levels change frequently. Also, do

not cross such signal lines over the clock lines or the signal lines

which are sensitive to noise.

Signal lines where potential levels change frequently (such as the

CNTR pin signal line) may affect other lines at signal rising edge

or falling edge. If such lines cross over a clock line, clock wave-

forms may be deformed, which causes a microcomputer failure or

a program runaway.

➀ Keeping oscillator away from large current signal lines

➁ Installing oscillator away from signal lines where potential lev-

els change frequently

Fig. 52 Wiring for a large current signal line/Writing of signal

lines where potential levels change frequently

(3) Oscillator protection using Vss pattern

As for a two-sided printed circuit board, print a Vss pattern on the

underside (soldering side) of the position (on the component side)

where an oscillator is mounted.

Connect the Vss pattern to the microcomputer Vss pin with the

shortest possible wiring. Besides, separate this Vss pattern from

other Vss patterns.

Fig. 53 Vss pattern on the underside of an oscillator

Microcomputer

Large

current

OUT

CNTR

AAA

XIN

XOUT

VSS

An example of VSS patterns on the

underside of a printed circuit board

Oscillator wiring

pattern example

Separate the VSS line for oscillation from other VSS lines

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 44 of 61

REJ03B0108-0102

5. Setup for I/O ports

Setup I/O ports using hardware and software as follows:

• Connect a resistor of 100 Ω or more to an I/O port in series.

• As for an input port, read data several times by a program for

checking whether input levels are equal or not.

• As for an output port, since the output data may reverse because

of noise, rewrite data to its port latch at fixed periods.

• Rewrite data to direction registers and pull-up control registers at

fixed periods.

Note: When a direction register is set for input port again at fixed

periods, a several-nanosecond short pulse may be output

from this port. If this is undesirable, connect a capacitor to

this port to remove the noise pulse.

Fig. 54 Setup for I/O ports

6. Providing of watchdog timer function by software

If a microcomputer runs away because of noise or others, it can

be detected by a software watchdog timer and the microcomputer

can be reset to normal operation. This is equal to or more effective

than program runaway detection by a hardware watchdog timer.

The following shows an example of a watchdog timer provided by

software.

In the following example, to reset a microcomputer to normal op-

eration, the main routine detects errors of the interrupt processing

routine and the interrupt processing routine detects errors of the

main routine.

This example assumes that interrupt processing is repeated mul-

tiple times in a single main routine processing. Fig. 55 Watchdog timer by software

• Assigns a single byte of RAM to a software watchdog timer

(SWDT) and writes the initial value N in the SWDT once at each

execution of the main routine. The initial value N should satisfy

the following condition:

N+1 ≥ (Counts of interrupt processing executed in each main

routine)

As the main routine execution cycle may change because of an

interrupt processing or others, the initial value N should have a

margin.

• Watches the operation of the interrupt processing routine by

comparing the SWDT contents with counts of interrupt process-

ing after the initial value N has been set.

• Detects that the interrupt processing routine has failed and de-

termines to branch to the program initialization routine for

recovery processing in the following case:

If the SWDT contents do not change after interrupt processing.

• Decrements the SWDT contents by 1 at each interrupt process-

ing.

• Determines that the main routine operates normally when the

SWDT contents are reset to the initial value N at almost fixed

cycles (at the fixed interrupt processing count).

• Detects that the main routine has failed and determines to

branch to the program initialization routine for recovery process-

ing in the following case:

If the SWDT contents are not initialized to the initial value N but

continued to decrement and if they reach 0 or less.

Direction register

Port latch

Data bus

I/O port

pins

Noise

N.G.

O.K.

Main routine

(SWDT)← N

CLI

Main processing

(SWDT)

Interrupt processing

routine errors

Interrupt processing routine

(SWDT) ← (SWDT)—1

Interrupt processing

(SWDT)

Main routine

errors

≤0RTI

Return

=N?

≤0?

≠N

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 45 of 61

REJ03B0108-0102

ELECTRICAL CHARACTERISTICS (Qz ROM version)

1.7544Group (Qz ROM version)

Applied to: M37544G2A-XXXSP/GP, M37544G2ASP/GP

Absolute Maximum Ratings

Table 9 Absolute maximum ratings

–0.3 to 6.5

–0.3 to VCC + 0.3

200

–20 to 85

–40 to 125

Power source voltage

Input voltage

P00–P07, P10–P14, P20–P25, P30–P34,P37, VREF

Input voltage ______

RESET, XIN

Output voltage

P00–P07, P10–P14, P20–P25, P30–P34,P37, XOUT

Power dissipation

Operating temperature

Storage temperature

°C

VCC

Topr

Tstg

Conditions

Symbol Ratings Unit

Parameter

All voltages are

based on VSS.

When an input

voltage is measured,

output transistors

are cut off.

Ta = 25°C

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 46 of 61

REJ03B0108-0102

Power source voltage (ceramic)

Power source voltage (RC)

Power source voltage (On-chip oscillator)

Power source voltage

Analog reference voltage

“H” input voltage

P00–P07, P10–P14, P20–P25, P30–P34, P37

“H” input voltage (TTL input level selected)

P10, P12, P34, P37

“H” input voltage

______

RESET, X IN

“L” input voltage

P00–P07, P10–P14, P20–P25, P30–P34, P37

“L” input voltage (TTL input level selected)

P10, P12, P34, P37

“L” input voltage

______

RESET, CNV SS

“L” input voltage

XIN

“H” total peak output current (Note)

P00–P07, P10–P14, P20–P25, P30–P34, P37

“L” total peak output current (Note)

P10–P14, P20–P25

“L” total peak output current (Note)

P00–P07, P30–P34, P37

“H” total average output current

(Note)

–P0

, P1

–P1

, P2

–P2

, P3

–

P34, P37

“L” total average output current (Note)

P10–P14, P20–P25

“L” total average output current (Note)

P00–P07, P30–P34, P37

Recommended Operating Conditions

Table 10 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

Max.

5.5

VCC

0.3VCC

0.8

0.2VCC

0.16VCC

–80

–40

Min.

4.0

2.4

2.2

4.5

4.0

2.4

2.2

4.0

2.4

2.2

1.8

2.0

0.8VCC

2.0

0.8VCC

Symbol Parameter Unit

f(XIN) = 8 MHz (High-, Middle-speed mode)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 2 MHz (High-, Middle-speed mode)

f(XIN) = 8 MHz (Double-speed mode)

f(XIN) = 4 MHz (Double-speed mode)

f(XIN) = 2 MHz (Double-speed mode)

f(XIN) = 1 MHz (Double-speed mode)

f(XIN) = 4 MHz (High-, Middle-speed mode)

f(XIN) = 2 MHz (High-, Middle-speed mode)

f(XIN) = 1 MHz (High-, Middle-speed mode)

Typ.

5.0

Limits

VCC

VSS

VREF

VIH

VIL

∑IOH(peak)

∑IOL(peak)

∑IOH(avg)

∑IOL(avg)

Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an

average value measured over 100 ms. The total peak current is the peak value of all the currents.

“““

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Rev.1.02 2005.07.20 page 47 of 61

REJ03B0108-0102

Recommended Operating Conditions (continued)

Table 11 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

“H” peak output current (Note 1)

P00–P07, P10–P14, P20–P25, P30–P34, P37

“L” peak output current (Note 1)

P10–P14, P20–P25

“L” peak output current (Note 1)

P00–P07, P30–P34, P37

“H” average output current (Note 2)

P00–P07, P10–P14, P20–P25, P30–P34, P37

“L” average output current (Note 2)

P10–P14, P20–P25

“L” average output current (Note 2)

P00–P07, P30–P34, P37

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at RC oscillation

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at ceramic oscillation or external clock input

Internal clock oscillation frequency (Note 3)

at RC oscillation

Internal clock oscillation frequency (Note 3)

at RC oscillation

Internal clock oscillation frequency (Note 3)

at RC oscillation

Symbol Parameter Limits Max.Typ.Min. –10

–5

Notes 1: The peak output current is the peak current flowing in each port.

2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.

3: When the oscillation frequency has a duty cycle of 50 %.

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(XIN)

MHz

Unit

VCC = 4.0 to 5.5 V

High-, Middle-speed mode

VCC = 2.4 to 5.5 V

High-, Middle-speed mode

VCC = 2.2 to 5.5 V

High-, Middle-speed mode

VCC = 4.5 to 5.5 V

Double-speed mode

VCC = 4.0 to 5.5 V

Double-speed mode

VCC = 2.4 to 5.5 V

Double-speed mode

VCC = 2.2 to 5.5 V

Double-speed mode

VCC = 4.0 to 5.5 V

High-, Middle-speed mode

VCC = 2.4 to 5.5 V

High-, Middle-speed mode

VCC = 2.2 to 5.5 V

High-, Middle-speed mode

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REJ03B0108-0102

Electrical Characteristics

Table 12 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Min. Typ. Max.

Symbol Parameter Limits Unit

IOH = –5 mA

VCC = 4.0 to 5.5 V

IOH = –1.0 mA

VCC = 1.8 to 5.5 V

IOL = 5 mA

VCC = 4.0 to 5.5 V

IOL = 1.5 mA

VCC = 4.0 to 5.5 V

IOL = 1.0 mA

VCC = 1.8 to 5.5 V

IOL = 15 mA

VCC = 4.0 to 5.5 V

IOL = 1.5 mA

VCC = 4.0 to 5.5 V

IOL = 10 mA

VCC = 1.8 to 5.5 V

VI = VCC

(Pin floating. Pull up

transistors “off”)

VI = VCC

VI = VSS

(Pin floating. Pull up

transistors “off”)

VI = VSS

(Pull up transistors “on”)

When clock stopped

VCC = 5.0 V, Ta = 25 °C

Test conditions

VCC–1.5

VCC–1.0

1.6

1000

62.5

“H” output voltage

P00–P07, P10–P14, P20–P25, P30–P34, P37 (Note 1)

“L” output voltage

P10–P14, P20–P25

“L” output voltage

P00–P07, P30–P34, P37

Hysteresis

CNTR0, CNTR1, INT0, INT1 (Note 2)

P00–P07 (Note 3)

Hysteresis

RXD, SCLK (Note 2)

Hysteresis

______

RESET

“H” input current

P00–P07, P10–P14, P20–P25, P30–P34, P37

“H” input current

______

RESET

“H” input current

XIN

“L” input current

P00–P07, P10–P14, P20–P25, P30–P34, P37

“L” input current

______

RESET, CNVSS

“L” input current

XIN

“L” input current

P00–P07, P30–P34, P37

RAM hold voltage

On-chip oscillator oscillation frequency

Oscillation stop detection circuit detection frequency

1.5

0.3

1.0

2.0

0.3

1.0

5.0

–5.0

–0.5

5.5

3000

187.5

µA

kHz

VOH

VOL

VT+–VT–

IIH

IIL

VRAM

ROSC

DOSC

0.4

0.5

0.9

4.0

–4.0

–0.2

2000

125

Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: RXD, SCLK, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).

3: It is available only when operating key-on wake up.

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REJ03B0108-0102

Electrical Characteristics (continued)

Table 13 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Min. Typ. Max.

Symbol Parameter Limits UnitTest conditions

Power source

current 8.0

1.5

10.0

5.0

900

3.2

450

1.0

10.0

µA

ICC 3.3

0.3

4.8

1.8

250

1.3

0.2

120

0.45

0.1

High-speed mode, f(XIN) = 8 MHz

Output transistors “off”

High-speed mode, VCC = 2.2 V, f(XIN) = 2 MHz

Output transistors “off”

Double-speed mode, f(XIN) = 8 MHz

Output transistors “off”

Middle-speed mode, f(XIN) = 8 MHz

Output transistors “off”

On-chip oscillator operation mode, VCC = 5.0 V

Output transistors “off”

f(XIN) = 8 MHz (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),

functions except timer 1 disabled,

Output transistors “off”

On-chip oscillator operation mode (in WIT state), VCC = 5.0 V

functions except timer 1 disabled,

Output transistors “off”

Increment when A/D conversion is executed

f(XIN) = 8 MHz, VCC = 5.0 V

All oscillation stopped

(in STP state)

Output transistors “off”

Ta = 25 °C

Ta = 85 °C

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REJ03B0108-0102

A/D Converter Characteristics

Table 14 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Resolution

Absolute accuracy

(quantification error excluded)

Conversion time

Ladder resistor

Reference power source

input current

A/D port input current

Min. Typ. Max.

Symbol Parameter Limits UnitTest conditions

Ta = –20 to 85 °C, Vcc = VREF

VREF = 5.0 V

VREF = 3.0 V

Bits

LSB

tc(XIN)

kΩ

µA

±3

109

200

120

5.0

—

ABS

tCONV

RLADDER

IVREF

II(AD)

135

Timing Requirements

Table 15 Timing requirements (VCC = 1.8 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Min. Typ. Max.

Symbol Parameter Limits Unit

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0 input cycle time

CNTR0, INT0, INT1, input “H” pulse width

CNTR0, INT0, INT1, input “L” pulse width

CNTR1 input cycle time

CNTR1 input “H” pulse width

CNTR1 input “L” pulse width

Serial I/O clock input cycle time (Note)

Serial I/O clock input “H” pulse width (Note)

Serial I/O clock input “L” pulse width (Note)

Serial I/O input set up time

Serial I/O input hold time

125

200

2000

800

370

220

100

µs

Note: In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).

When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.

______

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(CNTR0)

tWH(CNTR0)

tWL(CNTR0)

tC(CNTR1)

tWH(CNTR1)

tWL(CNTR1)

tC(SCLK)

tWH(SCLK)

tWL(SCLK)

tsu(RxD–SCLK)

th(SCLK–RxD)

Note: As for AD translation accuracy, on the following operating conditions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage,

accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value..

(2) When VREF voltage is less than [ 3.0V ], the accuracy at the time of low temperature may become extremely low compared with

the time of room temperature. The use beyond VREF=3.0V is recommended in the system the use by the side of low temperature

is assumed to be.

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REJ03B0108-0102

Switching Characteristics

Table 16 Switching characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

tC(SCLK)/2–30

–30

Min. Typ. Max.

Symbol Parameter Limits Unit

tWH(SCLK)

tWL(SCLK)

td(SCLK–TxD)

tv(SCLK–TxD)

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time

Serial I/O output valid time

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note)

CMOS output falling time (Note)

Note : Pin XOUT is excluded.

140

Fig. 56 Switching characteristics measurement circuit diagram

/ / /

Measured

output pin

CMOS output

100 pF

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REJ03B0108-0102

0.2V

CLK

-TxD)

0.2V

0.8V

(RxD-S

CLK

-RxD)

CLK

-TxD)

CLK

)

CLK

) t

CLK

)

RXD (at receive)

SCLK

0.2V

)

0.8V

)

XIN

0.2V

0.8

(RESET)

RESET

0.2V

(CNTR

)

0.8V

(CNTR

)

(CNTR

)

TXD (at transmit)

CNTR

0.2V

(CNTR

)

0.8V

(CNTR

)

INT

, INT

0.2V

(CNTR

)

0.8V

(CNTR

)

(CNTR

)

CNTR

Fig. 57 Timing chart

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 53 of 61

REJ03B0108-0102

PACKAGE OUTLINE

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

24 17

Detail F

Previous CodeJEITA Package Code RENESAS Code

PLQP0032GB-A 32P6U-A

MASS[Typ.]

0.2gP-LQFP32-7x7-0.80

1.0

0.125

0.35

0.7

0.20

0.200.1450.09

0.420.370.32

MaxNomMin

Dimension in Millimeters

Symbol

Reference

7.17.06.9D

7.17.06.9E

1.4A2

9.29.08.8

1.7A

0.20.10

0.70.50.3L

0.8e

0.10y

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

SEATING PLANE

*3*3

5.08

e1.778

L3.0

0.51

0.9 1.0 1.3

E 8.75 8.9 9.05

D 27.828.028.2

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.22 0.27 0.34

P-SDIP32-8.9x28-1.78 2.2g

MASS[Typ.]

32P4BPRDP0032BA-A

RENESAS CodeJEITA Package Code Previous Code

0.35 0.45 0.55

10.169.86 10.46

0.63 0.73 1.03

3.8

1.528 2.028

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 54 of 61

REJ03B0108-0102

APPENDIX

NOTES ON PROGRAMMING

1. Processor Status Register

(1) Initializing of processor status register

Flags which affect program execution must be initialized after a re-

set.

In particular, it is essential to initialize the T and D flags because

they have an important effect on calculations.

After a reset, the contents of the processor status register (PS) are

undefined except for the I flag which is “1”.

Reset

↓

Initializing of flags

↓

Main program

Fig. 3 Stack memory contents after PHP instruction execution

PLP instruction execution

↓

NOP

Fig. 1 Initialization of processor status register

(2) How to reference the processor status register

To reference the contents of the processor status register (PS), ex-

ecute the PHP instruction once then read the contents of (S+1). If

necessary, execute the PLP instruction to return the PS to its origi-

nal status.

A NOP instruction should be executed after every PLP instruction.

Fig. 2 Sequence of PLP instruction execution

(S)

(S)+1 Stored PS

3. JMP instruction

When using the JMP instruction in indirect addressing mode, do

not specify the last address on a page as an indirect address.

4. BRK instruction

(1) Interrupt priority level

When the BRK instruction is executed with the following condi-

tions satisfied, the interrupt execution is started from the address

of interrupt vector which has the highest priority.

• Interrupt request bit and interrupt enable bit are set to “1”.

• Interrupt disable flag (I) is set to “1” to disable interrupt.

5. Multiplication and Division Instructions

(1) The index X mode (T) and the decimal mode (D) flags do not

affect the MUL and DIV instruction.

(2) The execution of these instructions does not change the con-

tents of the processor status register.

Set D flag to “1”

↓

ADC or SBC instruction

↓

NOP instruction

↓

SEC, CLC, or CLD instruction

Fig. 4 Status flag at decimal calculations

2. Decimal calculations

(1) Execution of decimal calculations

The ADC and SBC are the only instructions which will yield proper

decimal notation, set the decimal mode flag (D) to “1” with the

SED instruction. After executing the ADC or SBC instruction, ex-

ecute another instruction before executing the SEC, CLC, or CLD

instruction.

(2) Notes on status flag in decimal mode

When decimal mode is selected, the values of three of the flags in

the status register (the N, V, and Z flags) are invalid after a ADC or

SBC instruction is executed.

The carry flag (C) is set to “1” if a carry is generated as a result of

the calculation, or is cleared to “0” if a borrow is generated. To de-

termine whether a calculation has generated a carry, the C flag

must be initialized to “0” before each calculation. To check for a

borrow, the C flag must be initialized to “1” before each calcula-

tion.

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6. Read-modify-write instruction

Do not execute a read-modify-write instruction to the read invalid

address (SFR).

The read-modify-write instruction operates in the following se-

quence: read one-byte of data from memory, modify the data,

write the data back to original memory. The following instructions

are classified as the read-modify-write instructions in the 740

Family.

(1) Bit management instructions: CLB, SEB

(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF

(3) Add and subtract instructions: DEC, INC

(4) Logical operation instructions (1’s complement): COM

Add and subtract/logical operation instructions (ADC, SBC, AND,

EOR, and ORA) when T flag = “1” operate in the way as the read-

modify-write instruction. Do not execute the read invalid SFR.

When the read-modify-write instruction is executed to read invalid

SFR, the instruction may cause the following consequence: the in-

struction reads unspecified data from the area due to the read

invalid condition. Then the instruction modifies this unspecified

data and writes the data to the area. The result will be random

data written to the area or some unexpected event.

NOTES ON PERIPHERAL FUNCTIONS

Notes on I/O Ports

1. Pull-up control register

When using each port which built in pull-up resistor as an output

port, the pull-up control bit of corresponding port becomes invalid,

and pull-up resistor is not connected.

Pull-up control is effective only when each direction register is set

to the input mode.

2. Notes in stand-by state

In stand-by state*1 for low-power dissipation, do not make input

levels of an input port and an I/O port “undefined”.

Pull-up (connect the port to Vcc) or pull-down (connect the port to

Vss) these ports through a resistor.

When determining a resistance value, note the following points:

• External circuit

• Variation of output levels during the ordinary operation

When using a built-in pull-up resistor, note on varied current val-

ues:

• When setting as an input port : Fix its input level

•When setting as an output port : Prevent current from flowing out

to external.

The output transistor becomes the OFF state, which causes the

ports to be the high-impedance state. Note that the level becomes

“undefined” depending on external circuits.

Accordingly, the potential which is input to the input buffer in a mi-

crocomputer is unstable in the state that input levels of an input

port and an I/O port are “undefined”. This may cause power

source current.

*1 stand-by state : the stop mode by executing the STP instruction

3. Modifying output data with bit managing instruction

When the port latch of an I/O port is modified with the bit manag-

ing instruction*2, the value of the unspecified bit may be changed.

The bit managing instructions are read-modify-write form instruc-

tions for reading and writing data by a byte unit. Accordingly, when

these instructions are executed on a bit of the port latch of an I/O

port, the following is executed to all bits of the port latch.

• As for a bit which is set for an input port :

The pin state is read in the CPU, and is written to this bit after bit

managing.

• As for a bit which is set for an output port :

The bit value of the port latch is read in the CPU, and is written to

this bit after bit managing.

Note the following :

• Even when a port which is set as an output port is changed for

an input port, its port latch holds the output data.

• As for a bit of the port latch which is set for an input port, its

value may be changed even when not specified with a bit man-

aging instruction in case where the pin state differs from its port

latch contents.

*2 bit managing instructions : SEB, and CLB instructions

4. Direction register

The values of the port direction registers cannot be read.

That is, it is impossible to use the LDA instruction, memory opera-

tion instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions

such as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read-modify-write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

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REJ03B0108-0102

Termination of Unused Pins

1. Terminate unused pins

Perform the following wiring at the shortest possible distance (20

mm or less) from microcomputer pins.

(1) I/O ports

Set the I/O ports for the input mode and connect each pin to VCC

or VSS through each resistor of 1 kΩ to 10 kΩ. The port which can

select a built-in pull-up resistor can also use the built-in pull-up re-

sistor.

When using the I/O ports as the output mode, open them at “L” or

“H”.

• When opening them in the output mode, the input mode of the

initial status remains until the mode of the ports is switched over

to the output mode by the program after reset. Thus, the poten-

tial at these pins is undefined and the power source current may

increase in the input mode. With regard to an effects on the sys-

tem, thoroughly perform system evaluation on the user side.

• Since the direction register setup may be changed because of a

program runaway or noise, set direction registers by program

periodically to increase the reliability of program.

2. Termination remarks

(1) I/O ports setting as input mode

[1] Do not open in the input mode.

• The power source current may increase depending on the first-

stage circuit.

• An effect due to noise may be easily produced as compared with

proper termination (1) shown on the above “1. Terminate unused

pins”.

[2] Do not connect to VCC or VSS directly.

If the direction register setup changes for the output mode be-

cause of a program runaway or noise, a short circuit may occur.

[3] Do not connect multiple ports in a lump to VCC or VSS through

a resistor.

If the direction register setup changes for the output mode be-

cause of a program runaway or noise, a short circuit may occur

between ports.

Notes on Interrupts

1. Change of relevant register settings

When not requiring for the interrupt occurrence synchronous with

the following case, take the sequence shown in Figure 5.

• When switching external interrupt active edge

• When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Fig. 5 Sequence of changing relevant register

When setting the followings, the interrupt request bit of the corre-

sponding interrupt may be set to “1”.

• When switching external interrupt active edge

INT0 interrupt edge selection bit

(bit 0 of Interrupt edge selection register (address 3A16))

INT1 interrupt edge selection bit

(bit 1 of Interrupt edge selection register)

CNTR0 active edge switch bit

(bit 2 of timer X mode register (address 2B16))

CNTR1 active edge switch bit

(bit 6 of timer A mode register (address 1D16))

2. Check of interrupt request bit

When executing the BBC or BBS instruction to determine an in-

terrupt request bit immediately after this bit is set to “0”, take the

following sequence.

If the BBC or BBS instruction is executed immediately after an in-

terrupt request bit is cleared to “0”, the value of the interrupt

request bit before being cleared to “0” is read.

Set the corresponding interrupt enable bit to “0” (disabled) .

↓

Set the interrupt edge selection bit, active edge switch bit, or

the interrupt source selection bit.

↓

NOP (One or more instructions)

↓

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

↓

Set the corresponding interrupt enable bit to “1” (enabled).

Set the interrupt request bit to “0” (no interrupt issued)

↓

NOP (one or more instructions)

↓

Execute the BBC or BBS instruction

Fig. 6 Sequence of check of interrupt request bit

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REJ03B0108-0102

Notes on Timers

1. When n (0 to 255) is written to a timer latch, the frequency divi-

sion ratio is 1/(n+1).

2. When a count source of timer X is switched, stop a count of the

timer.

Notes on Timer 1

1. Timer 1 count source

The “on-chip oscillator output” of timer 1 count source selection

bits (bits 1 and 0 of timer count source set register 2 (address

2F16)) can be selected while the on-chip oscillator oscillation con-

trol bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip

oscillator oscillation enabled).

Notes on Timer A

1. CNTR1 interrupt active edge selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit (bit 6 of timer A mode register (address 1D16)).

When this bit is “0”, the CNTR1 interrupt request bit goes to “1” at

the falling edge of the CNTR1 pin input signal. When this bit is “1”,

the CNTR1 interrupt request bit goes to “1” at the rising edge of

the CNTR1 pin input signal.

However, in the pulse width HL continuously measurement mode,

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

2. Period measurement mode, event counter mode and pulse

width HL continuously measurement mode

Set the direction register of port P00, which is also used as CNTR1

pin, to input.

Set the key-on wakeup function of P00, which is also used as

CNTR1 pin, to be disabled by setting the P00 key-on wakeup se-

lection bit (bit 7 of interrupt edge selection register (address 3A16))

to “1”.

3. Timer A count source

The “on-chip oscillator output” of timer A count source selection

bits (bits 3 and 2 of timer count source set register 2 (address

2F16)) can be selected while the on-chip oscillator oscillation con-

trol bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip

oscillator oscillation enabled).

Notes on Timer X

1. CNTR0 interrupt active edge selection

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit (bit 2 of timer X mode register (address 2B16)).

When this bit is “0”, the CNTR0 interrupt request bit goes to “1” at

the falling edge of CNTR0 pin input signal. When this bit is “1”, the

CNTR0 interrupt request bit goes to “1” at the rising edge of

CNTR0 pin input signal.

2. Timer X count source selection

The f(XIN) (frequency not divided) can be selected by the timer X

count source selection bits (bits 1 and 0 of timer count source set

on-chip oscillator is selected.

Do not select it for the timer X count source at the RC oscillation.

3. Pulse output mode

Set the direction register of port P14, which is also used as CNTR0

pin, to output.

When the TXOUT pin is used, set the direction register of port P03,

which is also used as TXOUT pin, to output.

4. Pulse width measurement mode

Set the direction register of port P14, which is also used as CNTR0

pin, to input.

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3. Notes common to clock synchronous serial I/O and UART

(1) Set the serial I/O control register again after the transmission

and the reception circuits are reset by clearing both the trans-

mit enable bit and the receive enable bit to “0.”

Fig. 7 Sequence of setting serial I/O control register again

Clear both the transmit enable bit (TE)

and the receive enable bit (RE) to “0”

Set the bits 0 to 3 and bit 6 of the

serial I/O control register

Set both the transmit enable bit (TE)

and the receive enable bit (RE), or

one of them to “1”

Notes on Serial Interface

1. Clock synchronous serial I/O

(1) When the transmit operation is stopped, clear the serial I/O en-

able bit (bit 7) and the transmit enable bit (bit 4 of serial I/O

control register (address 1A16)) to “0” (serial I/O and transmit

disabled).

Since transmission is not stopped and the transmission circuit is

not initialized even if only the serial I/O enable bit is cleared to “0”

(serial I/O disabled), the internal transmission is running (in this

case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports,

the transmission data is not output). When data is written to the

transmit buffer register in this state, data starts to be shifted to the

transmit shift register. When the serial I/O enable bit is set to “1” at

this time, the data during internally shifting is output to the TxD pin

and an operation failure occurs.

(2) When the receive operation is stopped, clear the receive en-

able bit (bit 5) to “0” (receive disabled), or clear the serial I/O

enable bit (bit 7 of serial I/O control register (address 1A16)) to

“0” (serial I/O disabled).

(3) When the transmit/receive operation is stopped, clear both the

transmit enable bit and receive enable bit to “0” (transmit and

receive disabled) simultaneously. (any one of data transmis-

sion and reception cannot be stopped.)

In the clock synchronous serial I/O mode, the same clock is used

for transmission and reception.

If any one of transmission and reception is disabled, a bit error oc-

curs because transmission and reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also oper-

ates for data reception. Accordingly, the transmission circuit does

not stop by clearing only the transmit enable bit to “0” (transmit

disabled). Also, the transmission circuit cannot be initialized even

if the serial I/O enable bit is cleared to “0” (serial I/O disabled)

(same as (1)).

(4) When signals are output from the SRDY pin on the reception

side by using an external clock, set all of the receive enable bit

(bit 5), the SRDY output enable bit (bit 2 of serial I/O control

(5) When the SRDY signal input is used, set the using pin to the in-

put mode before data is written to the transmit/receive buffer

2. UART

When the transmit operation is stopped, clear the transmit enable

bit to “0” (transmit disabled).

Same as (1) shown on the above “1. Clock synchronous serial I/

O“.

When the receive operation is stopped, clear the receive enable

bit to “0” (receive disabled).

When the transmit/receive operation is stopped, clear the transmit

enable bit to “0” (transmit disabled) and receive enable bit to “0”

(receive disabled).

(2) The transmit shift completion flag (bit 2 of serial I/O status reg-

ister (address 1916)) changes from “1” to “0” with a delay of

0.5 to 1.5 shift clocks. When data transmission is controlled

with referring to the flag after writing the data to the transmit

buffer register, note the delay.

(3) When data transmission is executed at the state that an exter-

nal clock input is selected as the synchronous clock, set “1” to

the transmit enable bit while the SCLK is “H” state. Also, write

to the transmit buffer register while the SCLK is “H” state.

(4) When the transmit interrupt is used, set as the following se-

quence.

➀ Serial I/O transmit interrupt enable bit is set to “0” (disabled).

➁ Serial I/O transmit enable bit is set to “1”.

➂ Serial I/O transmit interrupt request bit (bit 1 of interrupt request

tions have been executed.

➃ Serial I/O transmit interrupt enable bit (bit 1 of interrupt control

When the transmit enable bit is set to “1”, the transmit buffer

empty flag (bit 0) and transmit shift completion flag (bit 2 of serial

I/O status register (address 1916)) are set to “1”.

Accordingly, even if the timing when any of the above flags is set

to “1” is selected for the transmit interrupt source, interrupt request

occurs and the transmit interrupt request bit is set.

(5) Write to the baud rate generator (BRG) while the transmit/re-

ceive operation is stopped.

Can be set

with the LDM

instruction at

the same time

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 59 of 61

REJ03B0108-0102

4. I/O pin function when serial I/O is enabled.

The pin functions of P12/SCLK and P13/SRDY are switched to as

follows according to the setting values of a serial I/O mode selec-

tion bit (bit 6 of serial I/O control register (address 1A16)) and a

serial I/O synchronous clock selection bit (bit 1 of serial I/O control

(1) Serial I/O mode selection bit → “1” :

Clock synchronous type serial I/O is selected.

• Setup of a serial I/O synchronous clock selection bit

“0” : P12 pin turns into an output pin of a synchronous clock.

“1” : P12 pin turns into an input pin of a synchronous clock.

• Setup of a SRDY output enable bit (SRDY)

“0” : P13 pin can be used as a normal I/O pin.

“1” : P13 pin turns into a SRDY output pin.

(2) Serial I/O mode selection bit → “0” :

Clock asynchronous (UART) type serial I/O is selected.

• Setup of a serial I/O synchronous clock selection bit

“0”: P12 pin can be used as a normal I/O pin.

“1”: P12 pin turns into an input pin of an external clock.

• When clock asynchronous (UART) type serial I/O is selected, it

functions P13 pin. It can be used as a normal I/O pin.

Notes on A/D conversion

1. Analog input pin

In order to execute the A/D conversion correctly, to complete the

charge to an internal capacitor within the specified time is re-

quired. The maximum output impedance of the analog input

source required to complete the charge to a capacitor within the

specified time is as follows;

About 35 kΩ (at f(XIN) = 8 MHz)

When the maximum output impedance exceeds the above value,

equip an analog input pin with an external capacitor of 0.01µF to

1µF between an analog input pin and VSS.

Further, be sure to verify the operation of application products on

the user side.

An analog input pin includes the capacitor for analog voltage com-

parison. Accordingly, when signals from signal source with high

impedance are input to an analog input pin, charge and discharge

noise generates. This may cause the A/D conversion/comparison

precision to be worse.

2. Clock frequency during A/D conversion

The comparator consists of a capacity coupling, and a charge of

the capacity will be lost if the clock frequency is too low. This may

cause the A/D conversion precision to be worse. Accordingly, set

f(XIN) in order that the A/D conversion clock is 500 kHz or over

during A/D conversion.

3. A/D conversion accuracy

As for AD translation accuracy, on the following operating condi-

tions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sen-

sitive to noise when VREF voltage is set up lower than Vcc

voltage, accuracy may become low rather than the case

where VREF voltage and Vcc voltage are set up to the same

value.

(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the

low temperature may become extremely low compared with

that at room temperature. When the system would be used at

low temperature, the use at VREF=3.0 V or more is recom-

mended.

Notes on Watchdog Timer

1. The watchdog timer is operating during the wait mode. Write

data to the watchdog timer control register to prevent timer un-

derflow.

2. The watchdog timer stops during the stop mode. However, the

watchdog timer is running during the oscillation stabilizing time

after the STP instruction is released. In order to avoid the un-

derflow of the watchdog timer, the watchdog timer control

tion.

3. The STP instruction disable bit (bit 6 of watchdog timer control

“0” by program.

Notes on RESET pin

1. Connecting capacitor

In case where the RESET signal rise time is long, connect a ce-

ramic capacitor or others across the RESET pin and the Vss pin.

And use a 1000 pF or more capacitor for high frequency use.

When connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor

as short as possible.

• Be sure to verify the operation of application products on the

user side.

If the several nanosecond or several ten nanosecond impulse

noise enters the RESET pin, it may cause a microcomputer fail-

ure.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 60 of 61

REJ03B0108-0102

Notes on Clock Generating Circuit

1. Switch of ceramic/quartz-crystal oscillation and RC oscillation

After releasing reset, the oscillation mode selection bit (bit 5 of

CPU mode register (address 3B16)) is “0” (ceramic/quartz-crystal

oscillation selected). When the RC oscillation is used, after releas-

ing reset, set this bit to “1”.

2. Double-speed mode

The double-speed mode can be used only when a ceramic oscilla-

tion is selected. Do not use it when an RC oscillation is selected.

3. CPU mode register

Oscillation mode selection bit (bit 5), processor mode bits (bits 1

and 0) of CPU mode register (address 3B16) are used to select os-

cillation mode and to control operation modes of the

microcomputer. In order to prevent the dead-lock by erroneously

writing (ex. program run-away), these bits can be rewritten only

once after releasing reset. After rewriting, it is disabled to write any

data to the bit. (The emulator MCU “M37542RSS” is excluded.)

Also, when the read-modify-write instructions (SEB, CLB, etc.) are

executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

4. Clock division ratio, XIN oscillation control, on-chip oscillator

control

The state transition shown in Fig. 81 can be performed by setting

the clock division ratio selection bits (bits 7 and 6), XIN oscillation

control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of

CPU mode register. Be careful of notes on use in Fig. 81.

5. On-chip oscillator operation

When the MCU operates by the on-chip oscillator for the main

clock, connect XIN pin to VCC through a 1 kΩ to 10 kΩ resistor and

leave XOUT pin open.

The clock frequency of the on-chip oscillator depends on the sup-

ply voltage and the operation temperature range.

Be careful that this margin of frequencies when designing applica-

tion products.

6. Ceramic resonator

When the ceramic resonator/quartz-crystal oscillation is used for

the main clock, connect the ceramic resonator and the external

circuit to pins XIN and XOUT at the shortest distance. A feedback

resistor is built-in.

7. RC oscillation

When the RC oscillation is used for the main clock, connect the

XIN pin and XOUT pin to the external circuit of resistor R and the

capacitor C at the shortest distance.

The frequency is affected by a capacitor, a resistor and a micro-

computer.

So, set the constants within the range of the frequency limits.

8. External clock

When the external signal clock is used for the main clock, connect

the XIN pin to the clock source and leave XOUT pin open.

Select “0” (ceramic oscillation) to oscillation mode selection bit.

Notes on Oscillation Control

1. Oscillation stop detection circuit

(1) When the stop mode is used, set the oscillation stop detection

function to “invalid”.

(2) When the ceramic or RC oscillation is stopped (bit 4 of CPU

mode register (address 3B16)), set the oscillation stop detec-

tion function to “invalid”.

(3) The oscillation stop detection circuit is not included in the emu-

lator MCU “M37542RSS”.

2. Stop mode

(1) When the stop mode is used, set the oscillation stop detection

function to “invalid”.

(2) When the stop mode is used, set “0” (STP instruction enabled)

to the STP instruction disable bit of the watchdog timer control

3916)).

(3) The oscillation stabilizing time after release of STP instruction

can be selected from “set automatically”/“not set automati-

cally” by the oscillation stabilizing time set bit after release of

the STP instruction (bit 0 of MISRG (address 3816)). When “0”

is set to this bit, “0116” is set to timer 1 and “FF16” is set to

prescaler 1 automatically at the execution of the STP instruc-

tion. When “1” is set to this bit, set the wait time to timer 1 and

prescaler 1 according to the oscillation stabilizing time of the

oscillation. Also, when timer 1 is used, set values again to

timer 1 and prescaler 1 after system is returned from the stop

mode.

(4) The STP instruction cannot be used when the on-chip oscilla-

tor is selected by the clock division ratio selection bits (bits 7

and 6 of CPU mode register (address 3B16)).

(5) When the stop mode is used, set the on-chip oscillator oscilla-

tion control bit (bit 3 of CPU mode register (address 3B16)) to

“1” (on-chip oscillator oscillation stop).

(6) Do not execute the STP instruction during the A/D conversion.

Notes on Oscillation Stop Detection Circuit

1. Oscillation stop detection status bit is initialized by the following

operation.

(1) External reset

(2) Write “0” data to the ceramic or RC oscillation stop detection

function active bit.

2. The oscillation stop detection circuit is not included in the emu-

lator MCU “M37544RSS”.

7544 Group (QzROM version)

Rev.1.02 2005.07.20 page 61 of 61

REJ03B0108-0102

Note on Power Source Voltage

When the power source voltage value of a microcomputer is less

than the value which is indicated as the recommended operating

conditions, the microcomputer does not operate normally and may

perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power supply is turned off,

reset a microcomputer when the supply voltage is less than the

recommended operating conditions and design a system not to

cause errors to the system by this unstable operation.

Product shipped in blank

As for the product shipped in blank, Renesas does not perform the

writing test to user ROM area after the assembly process though

the QzROM writing test is performed enough before the assembly

process. Therefore, a writing error of approx.0.1 % may occur.

Moreover, please note the contact of cables and foreign bodies on

a socket, etc. because a writing environment may cause some

writing errors.

NOTES ON HARDWARE

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suit-

able for high frequencies as bypass capacitor between power

source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the

capacitor to as close as possible. For bypass capacitor which

should not be located too far from the pins to be connected, a ce-

ramic capacitor of 0.01 µF to 0.1 µF is recommended.

Handling of CNVss Pin

The CNVss pin is connected to the internal memory circuit block

by a low-ohmic resistance, since it has the multiplexed function to

be a programmable power source pin (VPP pin) as well.

To improve the noise reduction, connect a track between CNVss

pin and Vss pin with 1 to 10 kΩ resistance.

NOTES ON QzROM

Notes On QzROM Writing Orders

When ordering the QzROM product shipped after writing, submit

the mask file (extension: .mask) which is made by the mask file

converter MM.

Be sure to set the ROM option ("MASK option" written in the mask

file converter) setup when making the mask file by using the mask

file converter MM.

Notes On ROM Code Protect

(QzROM product shipped after writing)

As for the QzROM product shipped after writing, the ROM code

protect is specified according to the ROM option setup data in the

mask file which is submitted at ordering.

Renesas Technology corp. write the value of the ROM option

setup data in the ROM code protect address (address FFD416)

when writing to the QzROM. As a result, in the contents of the

ROM code protect address the ordered value may differ from the

actual written value.

The ROM option setup data in the mask file is “0016” for protect

enabled or “FF16” for protect disabled. Therefore, the contents of

the ROM code protect address (other than the user ROM area) of

the QzROM product shipped after writing is “0016” or “FF16”.

Note that the mask file which has nothing at the ROM option data

or has the data other than “0016” and “FF16” can not be accepted.

DATA REQUIRED FOR QzROM WRITING

ORDERS

The following are necessary when ordering a QzROM product

shipped after writing:

1. QzROM Writing Confirmation Form*

2. Mark Specification Form*

3. ROM data...........Mask file

* For the QzROM writing confirmation form and the mark specifi-

cation form, refer to the “Renesas Technology Corp.” Homepage

(http://www.renesas.com).

Note that we cannot deal with special font marking (customer's

trademark etc.) in QzROM microcomputer.

REVISION HISTORY

Rev. Date Description

Page Summary

(1/1)

7544 Group (QzROM version) Data Sheet

1.00 Oct. 26, 2004

1.01

Nov. 24, 2004

First edition issued

Table 12 Electrical characteristics: Minimum value of VRAM revised.

The followings are added;

- A/D Converter characteristics

- T iming requirements

- Switching Characteristics

- T iming chart

–

48-50

1.02 Jul. 20, 2005 All pages Delete the following: "PRELIMINARY".

2, 4, 5, 7 Package names are revied.

3 Table 1 Performance overview is added.

7 Table 2 is deleted.

12 ROM code protect is added.

Fig.10 is partly revised.

18 Termination of unused pins is added.

41 (4)Wiring to CNVSS pin is deleted.

(4)Wiring to VPP pin is revised.

Fig.49 is partly revised.

45 Table 8 is partly revised.

53 PACKAGE OUTLINE is revised.

61 Product shipped in blank, NOTES ON QzROM, DATA REQUIRED FOR

QzROM WRITING ORDERS are added.

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of

publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is

therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product

information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor

home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to

evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes

no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life

is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a

product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater

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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and

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