CORE1553BRTEVALBOARD - Actel Corporation

March 2003 1

v2.0

MIL-STD-1553B Bus Controller

Core1553BBC

Product Summary

Intended Use

• 1553B Bus Controlle r (BC)

• DMA Backend Interf ace to Exter nal Memory

Key Features

• Suppor ts MIL-STD-1553B

• Interfaces to External RAM

– Supports up to 128kbytes of Memory

– Synchronous or Asynchronous Backend Interface

– Backend Interface Identical to Core1553BRT

• Selectable Clock Rate of 12 MHz, 16 MHz, 20, MHz or 24 MHz

• Provides Direct CPU Access to Memory

• Interfaces to Standard 1553B Transceivers

• Fully Au t om a te d Me s sa ge Sc he d ul ing

– Frame Support

– Conditional Branching and Su b-routines

– Variable Inter-message Gaps and RT Response Times

– Real Time Clock for Message Scheduling

– Asynchronous Message Support

Targeted Devices

•SX-A Family

•RTSX Family

•RT54SX-S Family

•ProASIC

PLUS Fami ly

• Axceler ator Family

Core Deliverables

• Netlist Version

– Compiled RTL Simulation Model, Compliant with

Actel’s Libero™ Integrated Design Environment (IDE)

– Compatible with Actel’s Designer Place-and-Route

Tool

• RTL Versi on

– VHDL or Verilog Core Source Code

– Synthesis Scripts

• Actel-Developed Testbenches, VHDL and Verilog

Synthesis and Simulation Support

• S ynthesis: Exemplar, Synplicity, Design Compiler, FPGA

Compiler, FPGA Expres s

• Simulat io n: Vi ta l-C om pl ia nt VHDL Si mu la to rs and

OVI-Co mpliant Verilog Simu lators

Verification and Compliance

• Actel-Developed Simulation Testbench

• Core Implemented on the 1553B BC Development System

• Third-Party 1553B Compliance Testing of the 1553B

Enco de r an d D ec o de r B lo c ks Imp lemen t e d in a

A54SXA32-STD De vice

Development System (optional)

• Complete 1553B BC Implementation in an SX-A Device

• Includes a PCI Interface for Host CPU Connection

• Include s Tr a nsc e ive r s an d Bus Te rm in ati o n Com po n en ts

General Description

The Core1553BBC provides a complete, MIL-STD-1553B Bus

Controller (BC) . A typica l system implement ation using the

Core1553BBC is shown in Figure 1 on page 2.

Core1553BBC reads message descriptor blocks from the

memory and generates messages that are transmitted on

the 1553B bus. Data words are read from the memory and

transmitted on the 1553B bus. Data received is written to

the memory. The core can be configured directly to connect

to synchronous or asynchronous memory devices.

The core consists of f ive main blocks: 1553B encoder, 1553B

decoder, a protocol controller block, CPU interface, and a

backend interface (Figure2 on page2).

A single 1553B encoder takes each word to be transmitted

and serializes it using Manchester encoding. The encoder

also includes independent logic to prevent the BC from

transmitting for greater than the allowed period and

loopback fail logic. The loopback logic monitors the

received data and verifies that the core has correctly

received every word that it transmits. The output of the

encoder is gated with the bus enable signals to select which

buses the RT should be transmitting.

MIL-STD-1553B Bus Controller Core1553BBC

2 v2.0

Since the BC knows which bus is in use at any time, only a

single decoder is required. The decoder takes the serial

Manchester received data from the bus and extracts the

received data words. The decoder requires a 12 MHz,

16 MHz, 20 MHz, or 24 MHz clock to extract the data and the

clock from the serial stream.

The decoder contains a digital phased lock loop (PLL) that

generates a recovery clock used to sample the incoming

serial data. The dat a is then dese rialized and t he 16-bit wor d

decoded. The decoder detects whether a command, status

or data word has been received and checks that no

Manchester encoding or parity errors occurred in the word.

The protocol controller block handles all the message

sequencing and error recovery. This is a complex state

machine that reads the 1553B message frames from the

memory and transmits them on the 1553B bus.

Figure 1 • Typical Core1553BBC System

Figure 2 • Core1553BBC BC Block Diagram

Actel FPGA

BUSAINEN

BUSAINP

BUSAINN

BUSAOUTINH

BUSAOUTP

BUSAOUTN

BUSBINEN

BUSBINP

BUSBIN

BUSAOUTINH

BUSBOUTP

BUSBOUTN

RCVSTBA

RXDAIN

TXINHA

TXDAIN

Transceiver

(Not Included)

RCVSTBA

RXDBIN

TXINHA

TXDBIN

Memory

CPU

Glue

Logic

Backend

Interface

Core1553BBC

CPU

Interface

Core1553BBC

Encoder

Decoder Backend

Interface

Protocol

Controller

BusA

BusB Memory

64K*16

CPU

Interface

and

Registers

v2.0 3

MIL-STD-1553B Bus Controller Core1553BBC

The CPU interface allows the system CPU to access the

control registers within the BC. It also allows the CPU to

directly access the memory connected to the backend

interface; this can simplify the system design.

The backend interface for the Core1553BBC allows a simple

connection to a memory device. The backend interface can

be configured to connect to either synchronous or

asynchronous memory devices. This allows the core to be

connected to synchronous logic or memory within the FPGA

or to external asynchronous memory blocks. The interface

supports a standard bus request and grant protocol and

provides a WAIT input allowing the core to interface to slow

memory devices. This allows the core to share system

memory rather than have its own dedicated memory block.

Core1553BBC Operation

A bus controller is responsible for sending data bus

commands, participating in data transfers, receiving status

responses, and moni toring the bus system. The system CP U

will create message lists in the BC memory, as illustrated in

Figure 3.

When started, the BC works its way through the message

lists. Core1553B transmits the specified 1553B command

and data words. It receives the 1553B status word and

associated data words and writes them to the BC memory.

During this process, the BC monitors all possible 1553B

error conditions. If an RT does not respond correctly, the

BC will retry the message on both the original bus and the

alternate bus.

Figure 3 • Message Lists

Data Words

PARAMETER

INSTRUCTION

PARAMETER

INSTRUCTION

PARAMETER

INSTRUCTION

Instruction

List

CW (RTRT RX)

MSGCMD

DATAPTR

CW (RTRT TX)

SW (RTRT RX)

SW (RTRT TX)

TSW

Message

Block

Data

Block

MIL-STD-1553B Bus Controller Core1553BBC

4 v2.0

Core1553BBC Device Requirements

Core1553BBC can be implemented in several Actel FPGA devices. Table 1 gives typical utilization figures for the core

implemented in these devices.

The Core1553BBC clock rate can be programmed to be

12 MHz, 16 MHz, 20 MHz or 24 MHz. All Actel families listed

in Table 1 easily meet the required performance.

When implemented in ProASICPLUS or Axcelerator devices,

the core can be connected directly to the internal FPGA

memory blocks, eliminating the need for external memories.

Core1553BBC Verification and

Compliance

Core1553BBC is based upon Actel’s Core1553BRT, which

has been fully verified against the RT validation Test Plan

(MIL-HDBK-1553A, Appendix A). This ensures that the

1553B encoders and decoders are fully compliant to the

1553B specification. The actual bus controller function has

been extensively verified in both simulation and hardware.

Core1553BBC has been implemented on an A54SX32A-STD

part connected to external transc eivers and memory.

MIL-STD-1553B Bus Overview

The MIL-STD-1553B bus is a differential serial bus used in

military and space equipment. It is comprised of multiple

redundant bus connections and communicates at 1MB per

second.

The bus has a single active bus controller (BC) and up to 31

remote terminals (RTs). The BC manages all data transfers

on the bus u sing the command and status protocol. The bus

controller initiates every transfer by sending a command

word and data if required. The sele cted RT will respond with

a status word and data if required.

The 1553B command word contains a five-bit RT address,

transmit or receive bit, five-bit sub-address and five-bit word

count. This allows for 32 RTs on the bus. However, only

31RTs may be connected, since the RT address (31) is used

to indicate a broadcast transfer, i.e. all RTs should accept

the following data. Each RT has 30 sub-addresses reserved

for data transfers. The other two sub-addresses (0 and 31)

are reserved for mode codes used for bus control functions.

Data transfers contain up to (32) 16-bit data words. Mode

code command words are used for bus control functions

such as synchronization.

Table 1 • Device Utilization

Family

Cells or Tiles

Device UtilizationCombinatorial Sequential

RTAX-S 1,092 546 RTAX1000S-STD 9%

RT54SX-S 1,103 550 RT54SX32S-STD 57%

ProASICPLUS 2,166 532 APA150-STD 44%

SX-A 1,085 547 A54SX32A-STD 56%

Axcelerator 1,092 546 AX500-STD 20%

v2.0 5

MIL-STD-1553B Bus Controller Core1553BBC

Message Types

The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast BC to RT data transfers,

mode code messages, and direct RT-to-RT messages. Figure 4 shows the message formats.

Figure 4 • 1553B Message Formats

BC-to-RT T ransfer

Transmit

Command Data

0Data

. . . Data

nResponse

Time Status

Word

Message

Gap Next

Command

BCBC

RT-to-RT T ransfer

Receive

Command Transmit

Command Response

Time Status

Word Data

0Data

. . .

RT1 RT2

Data

nResponse

Time Status

Word Message

Gap Next

Command

BCBC

RT-to-BC T ransfer

Receive

Command Response

Time Status

Word Data

0Data

. . . Data

RT BC

Message

Gap Next

Command

RT-to-all RTs Broadcast

Receive

Command Transmit

Command Response

Time Status

Word Data

0Data

. . .

RT BC

Data

nMessage

Gap Next

Command

Mode Command, No Data

Mode

Command Response

Time Status

Word Message

Gap Next

Command

BC BC

Mode Command, RT Transmit Data

Mode

Command Response

Time Status

Word Mode

Data Message

Gap Next

Command

BC BC

Mode Command, RT Receive Data

Mode

Command Mode

Data Response

Time Status

Word Message

Gap Next

Command

BC BC

Broadcast Mode Command with Data

Mode

Command Mode

Data Message

Gap Next

Command

BC BC

Broadcast Mode Command, No Data

Mode

Command Message

Gap Next

Command

BC BC

BC-to-all-RTs Broadcast

Transmit

Command Data

0Data

. . . Data

nMessage

Gap Next

Command

BC BC

MIL-STD-1553B Bus Controller Core1553BBC

6 v2.0

Word Formats

There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW).

Each 20-bit word consists of a three-bit sync pattern, 16 bits of data, and a parity bit (Figure 5).

I/O Signal Descriptions

Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CW 515 51

Sync RT Address T/R Sub-address Word Count/Mode Code P

DW 16 1

Sync Data P

SW 5 111 3 111111

Sync RT Address

Message Error

Instrumentation

Service Reque st

Reserved

Broadcast

Received

Busy

Subsystem Flag

Dynamic Bus

Acceptance

Terminal Flag

Parity

Figure 5 • 1553B Word Formats

1553B Bus Interface

Name Type Description

BUSAINEN Out Active high output that enables for the A receiver

BUSAINP In Positive data input from the A receiver

BUSAINN In Negative data input from the A receiver

BUSBINEN Out Active high output that enables for the B receiver

BUSBINP In Positive data input from the bus to the B receiver

BUSBINN In Negative data input from the bus to the B receiver

BUSAOUTIN Out Active high transmitter inhibit for the A transmitter

BUSAOUTP Out Positive data output to the bus A transmitter (is held high when no transmission)

BUSAOUTN Out Negative data output to the bus A transmitter (is held high when no transmission)

BUSBOUTIN Out Active high transmitter inhibits the B transmitter

BUSBOUTP Out Positive data output to the bus B transmitter (is held high when no transmission)

BUSBOUTN Out Negative data output to the bus B transmitter (is held high when no transmission)

v2.0 7

MIL-STD-1553B Bus Controller Core1553BBC

Control and Status Signals

CPU Interface

The CPU in terf ace allows the access to the Core1553BBC internal registers and direct access to the backend m emory. This

interface is synchronous to the clock (Table 2).

Name Type Description

CLK In Master clock input (either 12 MHz, 16 MHz, 20 MHz, or 24 MHz)

RSTINn In Reset input (active low)

INTOUT Out Int err upt Requ est (a cti ve high ). Th e C PU is r equir ed to r ead t he i nter nal st atu s regi ste r to fin d the

reason for the interrupt. It is cleared by the CPU writing to the interrupt register

MEMFAIL Out This goes high if the core fails to read or write data to the backend interface within the required

time. This can be caused by the backend not asserting MEMGNTn fast enough or asserting

MEMWAITn for too long. It is cleared by the CPU writing to the interrupt register

BUSY Out This is high when the core is active, i.e. processing a message list

EXTFLAG In External flag input used by the condition codes within the bus controller

Table 2 • CPU Interface Signals

Name Type Description

CPUCSn In CPU chip select input (active low)

CPUWRn[1:0] In CPU write i nput (active low). T wo wri te inputs are provided for pr ocessors that supp ort byte

operations. When CPUWRn[1] is ’0,’ data bits [15:8] are written. When CPUWRn[0] is ’0,’

data bits [7:0] are written

CPURDn In CPU read input (active low)

CPUW AITn Out

CPU wait output (active low) indicates that the CPU should hold CPURDn or CPUWRn

active while the core completes the read or write operati on. CPUWAITn is not asserted

when the internal CPU registers are accessed. When accessing the backend interface

through the core, CPUWAIT will be activated for a minimum of four clock cycles for read

operations and three f o r write operations. CPUWAITn is asserted for extra clock cycles if

the backend interface delays asserting MEMGNTn or asserts MEMWAITn.

Timing is shown in the “CPU Interface Memory Read Cycle” figure and “CPU Interface

Memory Write Cycle” f igure on pa ge 19

CPUMEM In Selects whether the CPU accesses internal registers or backend memory.

'0': Accesses internal re gisters, register number is specified on CPUADDR[2:0]

'1': Accesses the backend memory

CPUADDR[15:0] In CPU address input

CPUDOUT[15:0] Out CPU data output

CPUDIN[15:0] In CPU data input

CPUDEN Out Da ta bus e nable (acti ve high) . T his si gna l is hi gh when th e cor e is pr ovi ding dat a o utpu t on

the CPUDOUT bus. It is intended for a tristate enable function

MIL-STD-1553B Bus Controller Core1553BBC

8 v2.0

Backend Interface

The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous

operation di rectly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard

external memory devices.

Table 3 • Backend Signals

Name Type Description

MEMREQn Out Memory Request (active low) output. The BC holds MEMREQn active if it requires additional

memory access cycles to take place immediately after the current memory cycle. This occurs

during the inter-message gap

MEMGNTn In Memory Grant (active low) input. This input should be synchronous to CLK and needs to meet

the internal register setup time. This input may be held l ow if the core has continuous access to

the RAM

MEMWRn[1:0] Out

Memor y W ri te (active lo w). When M EMWRn [1] is ’ 0,’ D[15:8 ] is written. W hen MEMW Rn[0] is ’0,’

D[7:0] is written.

Synchronous mode: This output indicates that data will be written on the rising clock edge. If

MEMWAITn is asserted, the MEMWRn pulse will be extended until MEMWAITn becomes

inactive.

Asynchronous mode: This output will be low for a minimum of one clock period and can be

extended by the MEMWAITn input. The address and data are valid one clock cycle before

MEMWRn is active and held for one clock cycle after MEMWRn goes inactive

MEMRDn Out

Memory Read (active low)

Synchronous mode: This output indicates that data is read on the next rising clock edge. If

MEMWAITn is active, then the data will be sampled on the rising clock edge on which

MEMWAIT n beco mes in active. T his si gn al is inten ded a s the r ead signal fo r synch rono us RA MS.

Asynchronous mode: This output will be low for a minimum of one clock period and can be

extended by the MEMWAITn input. The address is valid one clock cycle before MEMRDn is

active and held for one clock cycle after MEMRDn goes inactive. The data is sampled as

MEMRDn goes high

MEMCSn Out Memory Chip Select (active low). This output has the same timing as MEMADDR

MEMWAITn In Memor y W ait (active low) indicates that the backend is not re ady, and the core shou ld extend the

read or write strobe period. This input should be synchronous to CLK and needs to meet the

internal register set up time. It can be permanently held high

MEMADDR[15:0] Out Memory address output

MEMDOUT[15:0] Out Memory data output

MEMDIN[15:0] In Memory data input

MEMCEN Out Control signal enable (active high). This signal is high when the core is requesting the memory

bus and has been granted control. It is intended to enable any tristate drivers that may be

implemented on the memory control and address lines

MEMDEN Out Data bus enable (active high). This signal is high when the core is requesting the memory bus

has been granted control and is waiting to write data. It is intended to enable any bidirectional

drivers that may be implemented on the memory data bus

v2.0 9

MIL-STD-1553B Bus Controller Core1553BBC

The backend interf ace must allow the bus c ontroller access

to the memory when requested. The memory access time

from MEMREQn low to completion of the access cycle

MEMRDn and MEMWR n high varies on the BC setup. When

the CPU is allowed to access the memory through the bus

controller (CPUMEMEN active), the memory access time is

reduced (Table 4).

If the backend fails to allow the bus controller access to the

memory in the required time, the bus controller will assert

its MEMFAIL output and stop operation.

Miscellaneous I/O

Several inputs are used to modify the core functionality to

simplify int egration in the application. These inputs should

be tied to logic ’0’ or logic ’1 ’ as appropriate (Table 5).

Bus Controller Registers

The bus controller has nine internal registers that are used to control the bus controller operation and to provide status

information (Table 6).

Table 4 • Memory Access Requirements

CPUMEMEN CLK Speed MHz Memory Access Time

012 9.58µs

016 9.68µs

020 9.75µs

024 9.79µs

112 4.58µs

116 4.68µs

120 4.75µs

124 4.79µs

Table 5 • Miscellaneous I/O

Name Type Description

ASYNCIF In When ’1,’ the backend interface is in asynchronous mode. When ’0,’ the backend interface is in

synchronous mode

CPUMEMEN In When ’1,’ the CPU interface has access to the backend memory. When ’0,’ the CPU cannot access

the ba ckend mem or y thr ough th e co re. Thi s mu st be set to ’0’ if the core sh ares the CP U m emor y, i.e.

the CPU and memory buses are connected to the same system bus.

Table 6 • Bus Controller Registers

Address Name Type Size Function

000 CONTROL W [3:0] Allows the CPU to control the BC

000 STATUS R [15:0] Provides status information

001 SETUP RW [15:0] BC setup register

010 LISTPTR RW [15:0]

Current LISTPTR value. The address of the current instruction

being executed. At the start of operation, the CPU should set this

to the point at the first instruction. This value will automatically

step through the BC instruction list

011 MSGPTR R [15:0] Current MSGPTR value. Provides the address of the message

block being processed

100 CLOCK RW [15:0]

BC internal clock value

This 16-bit value counts up at a 1µs, 4µs, 8µs, or 32µs rate. This

gives a m aximum timer valu e of 2 seconds. The CPU may directly

load the counter

101 ASYNCPTR RW [15:0]

Asynchronous list pointer

Provides a pointer to a list of messages that will be processed

when started by the ASYNC message list bit in the control

110 STACKPTR RW [15:0]

BC stack pointer

This is the internal stack pointer register; it is used for the CALL

and RETURN instr uctions. W hen the bus co ntro ller is sta rted, the

STACKPTR is set to FFFF. The upper eight bits are fixed to FF,

and the lower eight bits will count down and up. This allows up to

255 addresses to be stored in the stack memory

111 INTERRUPT RW [15:0] Interrupt Register

MIL-STD-1553B Bus Controller Core1553BBC

10 v2.0

Setup Register

Bits Name Type Reset Function

15 FORCEORUN RW 0

’1’: If a BC-RT me ssage w ith a w ord count betwe en 1 and 31 is carr ied out,

the BC will transmit for greater than 680us. This will cause the transmitter

timer to trigger and the BC to shutdown.

’0’: Normal operation

14 CLOCKEN RW 0

Enables the internal CLOCK to count.

’0’: Internal CLOCK will not count

’1’: Internal CLOCK enabled

The clock is automatically enabled by the WAITC instruction

13:12 CLKFREQ RW 01

Tells the core what the external clock frequency is.

00: 12 MHz

01: 16 MHz

10: 20 MHz

11 : 24 MHz

11 RETRYMODE WR 0

Sets how the retry system works

’ 0’ : Retries on th e same bus for the nu mber of times set by the retie s setting

in the m essage block. T hen on the alternate bus for the number o f times set

by the alternate bus reties in the message block

’1’: Reties alternates between the two buses. The total number of retries is

the num ber of r eties plu s alter native b us re tri es a s set in th e me ssage bl ock

10 INTENABLE RW 0 Enables the external interrupt pin, when

’1’: The INTPENDING bit will drive the INTOUT pin

’0’: The INTOUT pin is held at a ’0’

9 AUTOCLOCK RW 1 ’1’: Sets the CLOCK register to 0000 when the BC is started

’0’: The CLOCK register is not reset when the BC is started

8 AUTOSTACK RW 1 ’1’: Sets the STACKPTR register to FFFF when the BC is started

’ 0’: The STACKPTR register is not reset when the BC is started.This allows

the BC to be restarted when previously stopped.

7:6 CLKRATE RW 00

Sets the rate at which the TIMER and CLOCK count

00: 1µs

01: 4µs

10: 8µs

11: 32µs

5:4 IMG RW 00

Sets the default minimum inter-message GAP

00: 4µs

01: 8µs

10: 16µs

11: 32µs

Note: the actual inter-message GAP is a function of the memory access

times. Typically, six memory accesses need to take place in the

inter-message gap.

3:2 RESPTIME RW 01

Sets the m aximum time that the BC will wait for an RT to respond

00: 12µs

01: 16µs

10: 20µs

11: 24µs

1:0 Reserved R 00 Reserved, return 00

v2.0 11

MIL-STD-1553B Bus Controller Core1553BBC

Control Register

Bits Name Type Function

3 ASYNC W

Writing a ’1’ causes the bus controller to jump to process the asynchronous instruction list

pointed to by the ASYNCPTR register at the end of the current message. When a RETAS

instruction is found, the bus controller returns to the original instruction list. An ASYNC

instruction can be issued while the bus controller is both active and inactive

2ABORTW

Writing a ’1’ stops the bus controller immediately; both normal and asynchronous message

operation will be aborted

1 STOP W Writing a ’1’ stops the bus controller at the end of the current message

0STARTW

Writing a ’1’ starts the bus controller. The bus controller cannot be started when an

asynchrono us message is active

Status Register

Bits Name Type Function

15:8 VERSION R Indicated the Core1553BBC code revision.

Core release notes provide latest version numbers

7:6 Reserved R Reserved, set to 00

5 LOOPFAIL R Indicates that a loopback failure occurred in the current frame

4FRAMEOKR

Indicates that all the messages in the current frame have completed successfully, and no

system action is required

3 FLAG R Indicates the value of the flag condition stored by the STOREFLAG instruction

2ASYNCR

Asynchronous message requested or in progress. This bit is cleared by the RETAS

instruction. When it is active, the bus controller cannot be started

1 BUSINUSE R Indicates which bus is in use

0: Bus A

1: Bus B

0 ACTIVE R BC is Active

Interrupt Register

Bits Name Type Function

15 INTPENDING RW When set, the BC has a n int erru pt pending. T his bit is se t if a ny o f the IN T VECT bit s ar e se t

14:8 INTVECT RW

Interrupt Reason

The CPU writing a ’1’ to the bit clears the bit

14 BC has completed the message list, HALT instruction executed

13 INTREQ instruction executed

12 Memory access failure. This bit also directly drives the MEMFAIL output

11 Asynchronous message is completed, RETAS instruction is executed

10 Transmitter shutdown is set when the core detects that it has been transmitting

continuously on the bus for greater than 700µs. When se t, the BC disables its

transmitter

9Stack pointer overflow or underflow is set if the BC attempts to push more than 256

return addresses onto the stack or pop of a non-existent address from the stack. BC

stops operation when this occurs

8Corrupt instruction list or data table.

Illegal command written to the control register, e.g. start instruction while an

asynchronous message is active. BC stops operation when this occurs

7:0 USERVECT R Provides the user provided interrupt reason as set by the instruction parameter

MIL-STD-1553B Bus Controller Core1553BBC

12 v2.0

Bus Controller Operation

After power-up, the bus contro ller waits while the CP U sets

up the bus controller memory and registers. The memory

contains an instruction list, message blocks, and data

blocks. Once the instruction list, message blocks, and data

blocks are setup, the C PU starts the bus controller. Th e bus

controller works it s w ay through a ll the mes sage blocks until

it reaches the end of the instruction list (Figure 6).

The instruction list contains a list of pointers to message

blocks. The message block contains the command words

transmitted on the 1553B bus and status words received

from the 1553B bus. It also contains a pointer to a data

block. The data block contains the data transmitted on the

1553B bus, or the data received from the 1553B bus.

Instruction List

The instruction list contains pairs of words: an instruction

and a parameter. Core1553BBC supports a broad set of

instructions allowing branching and sub-routine calls with

condition code support. This allows complex instruction

lists to be supported. The instruction contains a four-bit

OPCODE and five-bit condition code field (Table 7 and

Table 8).

All of the OPCODES suppor t the condition code field. If the

condition is TRUE, then the OPCODE is carried out;

otherwise, the BC continues to the next instruction. For

RT-to-RT messages, the condition code will be true if the bit

is set in either status word or not set in either status word

(Table 9 on page13).

Figure 6 • BC Memory Usage

PARAMETER

INSTRUCTION

PARAMETER

INSTRUCTION

PARAMETER

INSTRUCTION

Instruction

List

CW (RTRT RX)

MSGCMD

DATAPTR

CW (RTRT TX)

SW (RTRT RX)

SW (RTRT TX)

TSW

Data Words

Message

Block Data

Block

Table 7 • Instru ct io n Wo rd

15:13 12:8 7:4 3:0

Reserved CONDCODE Reserved OPCODE

Table 8 • Su pp o rted In st r u c t i o ns

OPCODE Function Condition

Code Parameter Description

0000 NOP N/A N/A No operation, jumps to next message

0001 DOMSG Yes Message Bl ock Address Process the message block

0010 JUMP Yes New Instruction

Address Jumps to the new message list address

0011 INTR Yes User interrupt value

(Lower 8 bits) Force a BC interrupt

0100 HALT Yes User interrupt value

(Lower 8 bits) Stop the BC

0101 DELAY Yes Timer value

(Lower 8 bits) Loads the timer with the parameter and waits until the timer

reaches zero

0110 LOADC Yes Clock value Loads the BC clock

0111 WAITC Yes Clock value Waits until the BC clock reaches the specified value

1000 CALL Ye s New Instruction

Address Jumps to the new message list address and pushes the return

address onto the stack.

v2.0 13

MIL-STD-1553B Bus Controller Core1553BBC

1001 RET Yes N/A Gets a return instruction address from the stack and jumps to it

1010 RETAS Yes N/A Gets a retur n instructi on address from the sta ck and jump s to it.

Also clear s the A SYNC b it i n the sta tus r egister allow ing f urth er

ASYNC messages to be accepted

1011 STOREF Yes N/A S tores the select ed flag so that it ma y be tested at a later st age.

The condition code field indicates which flag to store

Others Illegal N/A N/A Will halt operation and set the illegal OPCODE interrupt

Table 9 • Con d ition Codes

Condition Code Function Description

00000 ALWAYS Always perform the associated instruction

00001 RESP Performs the instruction if there was a response to the previous message

00010 GBR Performs the instruction if the previous message was successful

00011 TF Performs the instruction if the Terminal Flag was set in the last received status word

00100 DBA Perform the instruction if the Dynamic Bus Acceptance flag was set in the last received status

word

00101 SSF Performs the instruction if the Sub-system Flag was set in the last received status word

00110 BUSY Performs the instruction if the Busy bit was set in the last received status word

00111 BR Performs the instruction if the Broadcast Received bit was set in the last received status word

01000 SR Performs the instruction if the Service Request bit was set in the last received status word

01001 ME Performs the instruction if the Message Error bit was set in the last received status word

01010 SWE Performs the instruction if the RT address field is incorrect, the instrumentation bit is set, or

any of the reserved bits was set in the last received status word

01011 SWAB Performs the instruction if any bits are set in the last received status word (ignoring the RT

address field)

01100 ASYNC Performs the instruction if asynchronous message processing is active

01101 EXT Performs the instruction if the External flag input is active ’1’

01110 SFLAG Performs the instruction if the previously stored flag bit was set

10000 NEVER Never performs the associated instruction

10001 NORESP Performs the instruction if there was no response to the previous message

10010 NGBR Performs the instruction if the previous message was unsuccessful

10011 NTF Performs the instruction if the Terminal Flag was not set in the last received status word

10100 NDBA Performs the instruction if the Dynamic Bus Acceptance flag was not set in the last received

status word

10101 NSSF Performs the instruction if the Sub-System Flag was not set in the last received status word

10110 NBUSY Performs the instruction if the Busy bit was not set in the last received status word

10111 NBR Performs the instruction if the Broadcast Received bit was not set in the last received status

word

11 000 NSR Performs the instruction if the Service Request bit was not set in the last received status word

11001 NME Performs the instruction if the Message Error bit was not set in the last received status word

110 10 NSWE Perfo rms the instruction if the RT address field is correct and the instrum entatio n bit is not set,

and none of the reserved bits are set in the last received status word

11 011 NOSWAB Performs the instruction if no bits (ignoring the RT address field) are set in the last received

status word

11100 NASYNC Performs the instruction if asynchronous message processing is not active

11101 NEXT Performs the instruction if the External flag input is inactive ’0’

11110 NSFLAG Performs the instruction if the previously stored flag bit was not set

Others 0xxxx Illegal Equivalent to NEVER

Others 1xxxx Illegal Equivalent to ALWAYS

Table 8 • Su pp o rted In st r u c t i o ns (C ontinue d)

OPCODE Function Condition

Code Parameter Description

MIL-STD-1553B Bus Controller Core1553BBC

14 v2.0

Message Block

An eight-word m essage block controls each message. Th e BC reads th e 1553B command w ords from t he message block and

will write the received status words back to message block. Message blocks must be positioned on an eight-word memory

boundary (Table 10).

Table 10 • Message Block

Offset Contents Written by D escription

0 MSGCMD CPU Type of 1553B Message

15:10

Inter-message GAP after this message, 0 to 63µs

When 000000, it uses the inter-message gap as set by the BC setup

instruction between messages.

The actual IMG may be longer than when set by this register. The BC

needs to perf orm up to si x me mory access es dur ing t he IM G per iod. If

the backend memory responds slowly, then the IMG may increase

9’0’: Normal Operation

’1 ’ : The CLOCK value at the m id-point of the data word sync is used a s

the data for the synchronize with data mode code.

8: Bus to use

’0’: Bu s A

’1’: Bu s B

7:6 Retries on Alternate Bus 0 to 3

5:4 Retries on Bus 0 to 3

3:0

0000 0 BC-to-RT

0001 1 RT-to-BC

0110 6 Mode Code with no data

0010 2 Mode Code RT RX with data

0011 3 Mode Code RT TX with data

0101 5 RT-to-RT

1000 8 Broadcast BC-to-RT

1110 E Broadcast Mode Code RT with no data

1010 A Broadcast Mode Code RX with data

1101 D Broadcast RT-to-RT

Others Illegal

1 CW CPU 1553B Command Word. For RT-to-RT messages, this is the RX command word

2 RTRT TX CW CPU RT-to-RT TX 1553B Command Word

3DATAPTRCPU or BC

Data

Messages Pointer to memory location containing the 32-word data buffer. Must

be on a 32-word boundary, i.e. bits 4:0 are 00000

Mode Code

Messages Mode code data word

4 SW BC Received status word. For RT-to-RT messages this is the status word from the TX RT

5 RTRT RX SW BC Received status word from the RX RT for RT-to-RT messages

6 TSW BC Message T ransfer S t atus W ord. P rovides status information on th e messag e block. T he

CPU should clear this field when setting up the message block

15 Message Okay

’1’: Message completed okay with no errors. May have been retried.

’0’: Message failed after all retries completed

14 No response from RT

13 RT Signaled Message Error

12 1553B Error occurred, encoding, parity, too many words, etc.

11 :9 Number of retry attempts to transmit the message (0-6)

8 Unexpected bit set in the status word

7 Got the RT-to-RT RX status word

6 Got the status word, for RT-to-RT got the TX status word

5:0 Number or data words transmitted or received.

Note: ’000000’ indicates 0 and ’100000’ indicates 32

7 Reserved -- 15:0 Not Used

v2.0 15

MIL-STD-1553B Bus Controller Core1553BBC

Detailed Operation Flow

Table 11 shows the operations the core goes through in processing a message list containing two messages. The first message

is a BC-to-RT transfer of three words, and the second is an RT-to-BC transfer of three words.

Table 11 • Typical Operation

Memory Accesses Operation 1553B Activity

Read first Instruction code

Read first Instruction parameter

Read first MSGCMD

Read first CW Wait until the Inter-message gap expired

Read the DATAPTR Transmit the command word

Read the 1st DW

Read the 2nd DW Transmit the 1st data word

Read the 3rd DW Transmit the 2nd data word

Transmit the 3rd data word

Wait for the RT Response Time RT responds with SW

Write the SW to memory

Write the TSW to memory

Read second Instruction code

Read second instruction parameter

Read second MSGCMD

Read second CW Wait until the Inter-message gap expired

Read the DATAPTR Wait for the RT Response Time Transmit the command word

RT responds with SW

Write the SW to memory RT sends 1st data word

Write the 1st DW to memory RT sends 2nd data word

Write the 2nd DW to memory RT sends 3rd data word

Write the 2nd DW to memory

Write the TSW to memory

Read third Instructi on code (HALT) Generate the complete interrupt

Time

MIL-STD-1553B Bus Controller Core1553BBC

16 v2.0

Error Conditions

Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible

(Table12).

Loop Back Tests

Core1553BBC performs loop back testing on all of its

transmissions; the transmit data is fed back into the

receiver, and each transmitted word is compared to the

original. If an error is detected, the transmitter shutdown

bit is set in the BC status register.

Message Sequence Control

Core1553BBC message sequence control enables it to

automatically sequence mess ages with out CPU intervention.

It supports conditional jumps and sub-routine calls as well

as time control functions.

All instructions make use of the condition codes. The

condition codes cover error conditions, 1553B status word

values, and an external input . Core1553BBC supports CALL

and RETURN instructions wi th the aid of a stack that allows

for 255 ret urn address es to be st or ed. The stack occupies the

top 256 words of memory.

To support message timing and minor/major frame timing,

Core1553BBC has a built-in real time clock (16-bit) and

timer (8-bit) that can be used to synchronize message

timing. The r eal time clock and timer have a pr ogrammable

resolution of 1µs, 4µs, 8µs, or 32µs. Messages can be

programmed to be sent at an absolute time or relative to the

end of the previous message.

Asynchronous Messages

Core1553BBC supports asynchronous messages. While idle

or when a normal message list is being processed, the CPU

can initiate the core to jump to a secondary (asynchronous)

message list and process these messages. When complete,

the core will go back to the original message list.

The asynchronous message list can be started dire ctly by the

CPU by writing to the control register. When the current

message completes, the core pushes the current LISTPTR

address on the stack and load the LISTPTR with the value

Table 12 • Error Conditions

Erro r C ondit i on Action

Group Error

Signaling

1553B signaling error, parity, Manchester error, too

many or to few words, or incorrect SYNC type Messag e i s retried

1553B Loopback Failure. Can occur if an RT

responds late, causing the RT response and

following command word to corrupt each other on

the bus

Messag e is re tried

Loopback bit set in BC status

BC continues to process messages

Transmitter Overrun. Internal timer detects the BC

has transmitted for greater than 688µsBC controller aborts and asserts the transmitter

shutdow n interr upt

Memory

Memory Access Failur e BC controller abo rts and asser ts the memor y failure

interrupt

Stack Overflow or Underflow BC control ler aborts and asserts the stack overflow

interrupt

Status Word

Terminal Flag in SW

Sub-system Flag in SW

Service Request Flag in SW

Broadcast bit is SW

Unexpected bit in 1553B status bit set in the TSW.

Message is not retried

Busy Flag in SW

Message Error bit in SW Messag e is re tried

Other SW bit Message is retried

RT Response No or Late Re spons e Message is retried

Miscellaneous

Corrupt Instruction List

Illegal OPCODE

Message block MSGCMD message type bits [3:0]

mismatch the provided command word

BC controller aborts and asserts the corrupt

instruction list interrupt

Retry Fails Retries do not correct the error Message Okay bit in TSW not set

CPU Interface Start or second asynchronous message command

issued while an asynchronous message is active Command is ignored and an illegal command

interrupt generated

v2.0 17

MIL-STD-1553B Bus Controller Core1553BBC

specified in the ASYNCPTR. It will execute these

instructions until an RETAS instruction is found. At this

point, the LISTPTR is reloaded from the stack and the bus

controller enters the idle state or resumes the original

instruction list. While the asynchronous message list is

being processed, the START instruction and further

asynchronous events are disabled. They are re-enabled by

the RETAS instruction.

Retry Operations

Core1553BBC supports an automatic retry system that

retries messages that fail automatically. On detecting an

error that can be retried, the BC immediately retries the

message. Each message can be retried up to six times.

Core1553BBC can be programmed to retry up to three times

on the original bus. Then retry up to three times on the

alternative bus or to simply ret ry initially on the alt ernati ve

bus and then switch buses after each attempt.

Inter-Message Gap (IMG) Control

Core1553BBC provides several ways to control the 1553B

inter-message gaps. First, a default IMG is programmed into

the Core1533BBC control register. Secondly, every message

block can be programmed with its own inter-message gap;

this specifies the delay to the next message. Finally, the

WAITC and DELAY instructions can be used to insert extra

delays between messages.

The actual IMG gap is also a function of the backend

memory access system. There is a six-cycle overhead

required between each message to read and write to the

message block. These six memory accesses directly effect

the inter -message gap. The actual IMG will be the largest of

the duration of these six memory cycles or the programmed

IMG value.

Bus Transceivers

Core1553BBC needs a 1553B transceiver t o drive the 1553B

bus. Core1553BBC is designed to directly interface to

common MIL-STD-1553 transceivers, such as the DDC

BU-63147, and the Aeroflex ACT4402. When using

ProASICPLUS or Axcelerator, level translators are required

to connect the 5V output levels of the 1553B transceivers to

the 3.3V input levels of the FPGA.

In addition to the transceiver, a pulse transformer is

required for interfacing to the 1553 B bus. Figure 7, Figure 8,

and Figure 9 on page 18 show the connections required

from the Core1553BBC to the transceivers and then to the

bus via the pulse transformers.

Development System

A complete 1553B Bus controller development system is

also available. The Actel part number is “Core1553BBC Eval

Board." The development system implements a PCI to

1553B bus controller on a single PCB using an Actel

A54SX32A FPGA.

The PCI target interface uses the Actel CorePCI66 PCI

target interface core .

Figure 7 • Core1553BBC Development System

Development PCB

Actel FPGA

Transceiver

PCI

Target

Interface

Backend

Interface

Core1553BBC

CPU

Interface

Pulse

Transformer

Pulse

Transformer

Memory

64K*16

PCI

Interface

1553B Control

Memory

Access

MIL-STD-1553B Bus Controller Core1553BBC

18 v2.0

Typical BC System

Core1553BBC requires a master CPU to set up the data

tables. The CPU needs to be able to access the internal core

registers as well as the backend memory. Core1553BBC can

be configured in two ways wi th the CPU shared memory and

with its own memory.

When configured with its own memory, only the CPU port

needs to be connected to the CPU. The CPU accesses the

backend memory via Core1553BBC. This configuration also

supports using an internal FPGA memory connected to the

core and removes the need for external bus arbitration on

the CPU bus.

Alternatively, the core can share the CPU memory as shown

in Figure 9. In this case, both the backend memory and CPU

interfaces are connected to the CPU bus. The core provides

control lines that allow the memory and CPU interfaces to

share the same top-level I/O pins. When in this

configuration, the core needs to read or wri te t he memor y it

uses MEMREQn and MEMGNTn signals to arbitrate for the

CPU bus before completing the cycle.

Figure 8 • Core1553BBC with its Own Memory

Figure 9 • Core1553BBC Using Shared Memory

Pulse

Transformer

Actel FPGA

BUSAINEN

BUSAINP

BUSAINN

BUSAOUTINH

BUSAOUTP

BUSAOUTN

BUSBINEN

BUSBINP

BUSBIN

BUSAOUTINH

BUSBOUTP

BUSBOUTN

RCVSTBA

RXDAIN

TXINHA

TXDAIN

Transceiver

RCVSTBA

RXDBIN

TXINHA

TXDBIN

Memory

CPU

Backend

Interface

Core1553BBC

CPU

Interface

Pulse

Transformer

Actel FPGA

BUSAINEN

BUSAINP

BUSAINN

BUSAOUTINH

BUSAOUTP

BUSAOUTN

BUSBINEN

BUSBINP

BUSBIN

BUSAOUTINH

BUSBOUTP

BUSBOUTN

RCVSTBA

RXDAIN

TXINHA

TXDAIN

Transceiver

RCVSTBA

RXDBIN

TXINHA

TXDBIN

Backend

Interface

Core1553BBC

CPU

Interface

Memory

CPU

Bus

Arbritator

Pulse

Transformer

Pulse

Transformer

v2.0 19

MIL-STD-1553B Bus Controller Core1553BBC

Specifications

CPU Interface Timing

CPU Interface Register Read Cycle

CPU Interface Register Write Cycle

CPU Interface Memory Read Cycle

CPU Interface Memory Write Cycle

CPUCSN

CPURDN

CPUADDR

CPUMEM

CPUDOUT

CPUDEN

CPUWAITN

ADDR

Data

Tpd Tpd

CLK

CPUCSN

CPUWRN[1:0]

CPUADDR

CPUMEM

CPUDIN

CPUWAITN

ADDR

Data

Write done

CLK

CPUCSN

CPURDN

CPUADDR

CPUMEM

CPUDOUT

CPUDEN

CPUWAITN

ADDR

Data

Tpd Tpd

CLK

CPUCSN

CPUWRN

CPUADDR

CPUMEM

CPUDIN

CPUWAITN

ADDR

Data

Tpd Tpd

Write

MIL-STD-1553B Bus Controller Core1553BBC

20 v2.0

CPUWAITn will be driven low for a minimum of three clock

cycles for write cycles and four for read cycles and the

number of clock cycles the memory backend delays the

assertion of MEMGNTn and asserts MEMWAITn. CPU WAITn

is driven low by CPURDn/CPUWRn becoming active and

returns high on the falling clock edge after data is valid.

The CPU interface signals are internally synchronized to the

Core1553BBC master clock. If these inputs are

asynchronous, then CPUCSn, CPUADDR, CPUDATA should

be valid/invalid before CPUWRn and remain valid after

CPUWRn. CPUWRn must be active for at least one clock

cycle.

Memory Timing

Interrupt Timing

CLK

INTOUT

CPURDN

Tiack

Asynchronous Memory Read Cycle

Asynchronous Memory Write Cycle

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMADDR

MEMDIN

MEMRDn

MEMWAITn

Tsu

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMADDR

MEMDOUT

MEMWRn

MEMWAITn

Tsu

v2.0 21

MIL-STD-1553B Bus Controller Core1553BBC

Synchronous Mem ory Read Cycle

Synchronous Memory Write Cycle

Synchronous Mem ory Read Cycle with MEM GNTn Active

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMRDn

MEMADDR

MEMDIN

MEMWAITn

Tsu

Tsu Tsu

Tsu

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMADDR

MEMDOUT

MEMWRn

MEMWAITn

Tsu

Tsu Tsu

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMRDn

MEMADDR

MEMDIN

MEMWAITn

Tsu

MIL-STD-1553B Bus Controller Core1553BBC

22 v2.0

Clock Requirements

To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12 MHz, 16 MHz, 20 MHz, or

24 MHz with a tolerance of ±0.01%.

Synchronous Memory Write Cycle with MEMGNTn A ctive

Memory Grant Time-out

Memo r y Wait Time-out

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMADDR

MEMDOUT

MEMWRn

MEMWAITn

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMRDn/WRn

MEMWAITn

MEMFAIL

Timeout

CLK

MEMREQn

MEMGNTn

MEMCEN

MEMDEN

MEMCSn

MEMRDn/WRn

MEMWAITn

MEMFAIL

Timeout

Tsu

v2.0 23

MIL-STD-1553B Bus Controller Core1553BBC

Ordering Information

Core1553BBC can be ordered through your local Actel sales

representative. It should be ordered using the following

number scheme: Core1553BBC-XX, where XX is (Table 13):

The Evaluation board can also be ordered using the

following order code "Core1553BBC Eval Board."

Datasheet Categories

Product Definition

This vers ion of the datasheet is the definit ion of the product. A prototype may or may not be available. Data presente d is subj ect

to significant changes.

Production (unmarked)

This version of the datasheet contains complete information on the final core. All components are fully operational and the

core has been thoroughly verified.

Advanced

This version of the datasheet provides nearly complete information for a prototype IP product. Code is fully operational, but may

not sup port all features expected in the production release. A proto type core and a preliminary testbenc h are available.

Table 13 • Orderin g Codes

XX Description

EV Evaluation Version

SN Single-use Netlist for use on Actel devices

AN Netlist for unlimited use on Actel devices

AR RT L for unlimited use on Actel devices

UR RTL for unlimited use and not restricted to Actel

devices

Actel, the Act el logo, Libe ro, and DirectCor e are registered tr ademarks of Actel Corporat ion.

All other tr ademarks are the property of thei r owners.

http://www.actel.com

Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086

USA

Tel: (408) 739-1010

Fax: (408) 739-1540

Actel Europe Ltd.

Dunlop House, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

Tel:

+44 (0)1276 401450

Fax:

+44 (0)1276 401490

Actel Japan

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Tel: +81 03-3445- 7671

Fax: +81 03-3445-7668

Actel Hong Kong

39th Floor

One Pacific Place

88 Queensway

Admiralty, Hong Kong

Tel: 852-22735712

51700015-0/3.02