IADJ
EN
CSN
LM3409/HV
UVLO
D1
L1
CIN
VIN
ILED
VCC
COFF
GND Q1
CSP
CF
ROFF
PGATE
COFF
RUV2
RUV1
DAP
VIN
VO
RSNS
1
2
3
4
5 6
7
8
9
10
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Design
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
SNVS602L MARCH 2009REVISED JUNE 2016
LM3409, -Q1, LM3409HV, -Q1 P-FET Buck Controller for High-Power LED Drivers
1
1 Features
1 LM3409-Q1 and LM3409HV-Q1 are Automotive
Grade Products: AEC-Q100 Grade 1 Qualified
2-, 1-A Peak MOSFET Gate Drive
VIN Range: 6 V to 42 V (LM3409, LM3409-Q1)
VIN Range: 6 V to 75 V (LM3409HV, LM3409HV-
Q1)
Differential, High-Side Current Sense
Cycle-by-Cycle Current Limit
No Control Loop Compensation Required
10,000:1 PWM Dimming Range
250:1 Analog Dimming Range
Supports All-Ceramic Output Capacitors and
Capacitor-less Outputs
Low-Power Shutdown and Thermal Shutdown
Thermally Enhanced 10-Pin, HVSSOP Package
2 Applications
LED Driver
Constant Current Source
Automotive Lighting
General Illumination
3 Description
The LM3409, LM3409-Q1, LM3409HV, and
LM3409HV-Q1 are P-channel MOSFET (PFET)
controllers for step-down (buck) current regulators.
They offer wide input voltage range, high-side
differential current sense with low adjustable
threshold voltage and fast output enable/disable
function and a thermally enhanced 10-pin, HVSSOP
package. These features combine to make the
LM3409 family of devices ideal for use as constant
current sources for driving LEDs where forward
currents up to 5 A are easily achievable.
The LM3409 devices use constant off-time (COFT)
control to regulate an accurate constant current
without the need for external control loop
compensation. Analog and PWM dimming are easy to
implement and result in a highly linear dimming range
with excellent achievable contrast ratios.
Programmable UVLO, low-power shutdown, and
thermal shutdown complete the feature set.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM3409 HVSSOP (10) 3.00 mm × 3.00 mm
PDIP (14) 19.177 mm × 6.35 mm
LM3409-Q1 HVSSOP (10) 3.00 mm × 3.00 mmLM3409HV
LM3409HV-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
2
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
SNVS602L MARCH 2009REVISED JUNE 2016
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Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 7
8 Detailed Description............................................ 10
8.1 Overview................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 18
9 Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 23
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support................. 38
12.1 Device Support...................................................... 38
12.2 Related Links ........................................................ 38
12.3 Community Resources.......................................... 38
12.4 Trademarks........................................................... 38
12.5 Electrostatic Discharge Caution............................ 38
12.6 Glossary................................................................ 38
13 Mechanical, Packaging, and Orderable
Information........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (July 2014) to Revision L Page
Corrected package family reference in Features section....................................................................................................... 1
Corrected package family reference in Device Information table........................................................................................... 1
Added Device Comparison table............................................................................................................................................ 3
Corrected typographical error in package name reference in Pin Configuration and Functions section............................... 3
Corrected typographical error in Absolute Maximum Ratings table....................................................................................... 4
Corrected typographical error in package name reference in ESD Ratings table ................................................................. 4
Corrected package family reference in Thermal Information table......................................................................................... 5
Changes from Revision J (May 2013) to Revision K Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision I (May 2013) to Revision J Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
UVLO
1
VCC
2
VIN
3
4
12
EN 11
IADJ
10
CSP
5
13
14
COFF CSN
NC
NC
6GND 9
8
PGATE
7NC NC
UVLO
1
CSP
2
VIN
3
4
8
COFF 7
EN
6
CSN
5
9
10
GND PGATE
DAP
VCC
IADJ
3
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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SNVS602L MARCH 2009REVISED JUNE 2016
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5 Device Comparison Table
ORDERABLE
NUMBER MAXIMUM INPUT
VOLTAGE (V) AEC-Q100 GRADE 1
QUALIFIED
LM3409 42 N
LM3409-Q1 Y
LM3409HV 75 N
LM3409HV-Q1 Y
6 Pin Configuration and Functions
DGQ Package
10-Pin HVSSOP
Top View NFF Package
14-Pin PDIP
Top View
Pin Functions
PIN DESCRIPTION
NAME PDIP HVSSOP
UVLO 1 1 Input undervoltage lockout. Connect to a resistor divider from VIN and GND. Turn-on threshold is
1.24 V and hysteresis for turnoff is provided by a 22 µA current source.
IADJ 3 2 Analog LED current adjust. Apply a voltage from 0 to 1.24 V, connect a resistor to GND, or leave
open to set the current sense threshold voltage.
EN 4 3 Logic level enable and PWM dimming. Apply a voltage >1.74 V to enable device, a PWM signal to
dim, or a voltage < 0.5 V for low-power shutdown.
COFF 5 4 Off-time programming. Connect resistor from VO, capacitor to GND to set off-time.
GND 6 5 Connect to system ground.
PGATE 9 6 Gate drive. Connect to gate of external P-channel MOSFET.
CSN 10 7 Negative current sense. Connect to negative side of sense resistor.
CSP 11 8 Positive current sense. Connect to positive side of sense resistor (also to VIN).
VCC 12 9 VIN referenced linear regulator output. Connect at least a 1-µF ceramic capacitor to VIN. The
regulator provides power for the P-channel MOSFET drive.
VIN 14 10 Input voltage. Connect to the input voltage.
Thermal pad Connect to GND pin. Place 4 to 6 vias from thermal pad to GND plane.
4
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN, EN, UVLO to GND
LM3409,
LM3409-Q1 –0.3 45 V
LM3409HV,
LM3409HV-Q1 –0.3 76
VIN to VCC, PGATE –0.3 7 V
VIN to PGATE for 100 ns –2.8 9.5 V
VIN to CSP, CSN –0.3 0.3 V
COFF to GND –0.3 4 V
COFF Current continuous ±1 mA
IADJ Current continuous ±5 mA
Junction temperature 150 °C
Soldering information Lead temperature (Soldering, 10 s) 260 °C
Infrared and convection reflow (15 s) 260 °C
Storage temperature, Tstg –65 125 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(4) The human body model is a 100 pF capacitor discharged through a 1.5-kresistor into each pin.
7.2 ESD Ratings VALUE UNIT
LM3409 IN DGQ AND NFF PACKAGES
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2) ±1000
LM3409-Q1 IN DGQ AND NFF PACKAGES
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(3)(4) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±1000
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN
LM3409,
LM3409-Q1 6 42 V
LM3409HV,
LM3409HV-Q1 6 75
Junction temperature range, TJ40 125 °C
5
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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SNVS602L MARCH 2009REVISED JUNE 2016
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.4 Thermal Information
THERMAL METRIC(1)
LM3409,
LM3409-Q1,
LM3409HV,
LM3409HV-Q1
LM3409
UNIT
DGQ
(HVSSOP) NFF
(PDIP)
10 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 54.4 49 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.7 36.3 °C/W
RθJB Junction-to-board thermal resistance 33.8 28.9 °C/W
ψJT Junction-to-top characterization parameter 3.9 21.1 °C/W
ψJB Junction-to-board characterization parameter 33.5 28.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.5 N/A °C/W
6
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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(1) Typical values represent most likely parametric norms at the conditions specified and are not ensured.
(2) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument's Average Outgoing Quality
Level (AOQL).
(3) The current sense threshold limits are calculated by averaging the results from the two polarities of the high-side differential amplifier.
7.5 Electrical Characteristics
VIN = 24 V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C (1). Data sheet
minimum and maximum specification limits are specified by design, test, or statistical analysis.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
PEAK CURRENT COMPARATOR
VCST VCSP VCSN average peak
current threshold(3) VADJ = 1 V 188 198 208 mV
VADJ = VADJ-OC 231 246 261
AADJ VADJ to VCSP VCSN threshold
gain 0.1 < VADJ < 1.2 V
VADJ = VADJ-OC 0.2 V/V
VADJ-OC IADJ pin open circuit voltage 1.189 1.243 1.297 V
IADJ IADJ pin current 3.8 5 6.4 µA
tDEL CSN pin falling delay CSN fall - PGATE rise 38 ns
SYSTEM CURRENTS
IIN Operating input current Not switching 2 mA
ISD Shutdown input current EN = 0 V 110 µA
PFET DRIVER
RPGATE Driver output resistance Sourcing 50 mA 2
Sinking 50 mA 2
VCC REGULATOR
VCC VIN pin voltage - VCC pin voltage VIN > 9 V
0 < ICC < 20 mA 5.5 6 6.5 V
VCC-UVLO VCC undervoltage lockout
threshold VCC increasing 3.73 V
VCC-HYS VCC UVLO hysteresis VCC decreasing 283 mV
ICC-LIM VCC regulator current limit 30 45 mA
OFF-TIMER AND ON-TIMER
VOFT Off-time threshold 1.122 1.243 1.364 V
tD-OFF COFF threshold to PGATE falling
delay 25 ns
tON-MIN Minimum ON-time 115 211 ns
tOFF-MAX Maximum OFF-time 300 µs
UNDERVOLTAGE LOCKOUT
IUVLO UVLO pin current VUVLO = 1 V 10 nA
VUVLO-R Rising UVLO threshold 1.175 1.243 1.311 V
IUVLO-HYS UVLO hysteresis current 22 µA
ENABLE
IEN EN pin current 10 nA
VEN-TH EN pin threshold VEN rising 1.74 V
VEN falling .5
VEN-HYS EN pin hysteresis 420 mV
tEN-R EN pin rising delay EN rise - PGATE fall 42 ns
tEN-F EN pin falling delay EN fall - PGATE rise 21 ns
TEMPERATURE (°C)
VOFT (V)
1.26
1.25
1.24
1.23
1.22
-50 -14 22 58 94 130
TEMPERATURE (°C)
tON-MIN (ns)
180
160
140
120
100
80
60
-50 -14 22 58 94 130
TEMPERATURE (°C)
VADJ (V)
1.260
1.255
1.250
1.245
1.240
1.235
1.230
-50 -14 22 58 94 130
TEMPERATURE (°C)
IADJ (#A)
-5.05
-5.10
-5.15
-5.20
-5.25
-5.30
-5.35
-50 -14 22 58 94 130
TEMPERATURE (°C)
VCST (mV)
250
248
246
244
242
-50 -14 22 58 94 130
TEMPERATURE (°C)
VCC (V)
6.125
6.100
6.075
6.050
6.025
-50 -14 22 58 94 130
7
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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SNVS602L MARCH 2009REVISED JUNE 2016
Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
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7.6 Typical Characteristics
TA= 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
Figure 1. VCST vs Junction Temperature Figure 2. VCC vs Junction Temperature
Figure 3. VADJ vs Junction Temperature Figure 4. IADJ vs Junction Temperature
Figure 5. VOFT vs Junction Temperature Figure 6. tON-MIN vs Junction Temperature
VADJ (V)
ILED (A)
2.3
1.8
1.4
0.9
0.5
0.0
0.0 0.3 0.5 0.8 1.0 1.3
INPUT VOLTAGE (V)
ILED (A)
2.40
2.35
2.30
2.25
2.20
2.15
2.10
20 24 28 32 36 40 44
INPUT VOLTAGE (V)
ILED (A)
2.5
2.4
2.3
2.2
2.1
2.0
20 32 44 56 68 80
INPUT VOLTAGE (V)
EFFICIENCY (%)
100
95
90
85
80
75
700 10 20 30 40 50
INPUT VOLTAGE (V)
EFFICIENCY (%)
100
95
90
85
80
75
700 20 40 60 80
8
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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Typical Characteristics (continued)
TA= 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
Figure 7. LM3409 Efficiency vs Input Voltage VO= 17 V (5
LEDs); ILED = 2 A
Figure 8. LM3409HV Efficiency vs Input Voltage VO= 17 V (5
LEDs); ILED = 2 A
Figure 9. LM3409 LED Current vs Input Voltage VO= 17 V (5
LEDs) Figure 10. LM3409HV LED Current vs Input Voltage VO= 17
V (5 LEDs)
Figure 11. Normalized Switching Frequency vs Input
Voltage Figure 12. Amplitude Dimming Using IADJ Pin VO= 17 V (5
LEDs); VIN = 24 V
ILED (A)
VEN (V)
7
6
5
4
3
2
1
0
-1
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
ILED
2 és/DIV
3.5 és
VEN
ILED (A)
VPWM2 (V)
7
6
5
4
3
2
1
0
-1
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
ILED
200 ns/DIV
VPWM2
ILED (A)
VEN (V)
14
12
10
8
6
4
2
0
-2
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
ILED
10 és/DIV
VEN
ILED (A)
VPWM2 (V)
14
12
10
8
6
4
2
0
-2
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
ILED
2 és/DIV
VPWM2
DUTY CYCLE (%)
ILED (A)
2.3
1.8
1.4
0.9
0.5
0.00 20 40 60 80 100
1kHz
20kHz
DUTY CYCLE (%)
ILED (A)
2.3
1.8
1.4
0.9
0.5
0.00 20 40 60 80 100
50 kHz
100 kHz
9
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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Typical Characteristics (continued)
TA= 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
Figure 13. Internal EN Pin PWM Dimming VO= 17 V (5
LEDs); VIN = 24 V Figure 14. External Parallel FET PWM Dimming VO= 17 V (5
LEDs); VIN = 24 V
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
Figure 15. 20 kHz 50% EN Pin PWM Dimming VO= 42 V (12
LEDs); VIN = 48 V
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
Figure 16. 100 kHz 50% External FET PWM Dimming VO= 42
V (12 LEDs); VIN = 48 V
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
Figure 17. 20 kHz 50% EN Pin PWM Dimming (Rising Edge)
VO= 42 V (12 LEDs); VIN = 48 V
The waveforms were acquired using the standard evaluation board
from AN-1953 (SNVA390).
Figure 18. 100 kHz 50% External FET PWM Dimming (Rising
Edge) VO= 42 V (12 LEDs); VIN = 48 V
VCC
VIN
PGATE
IADJ
EN
COFF
GND
THERMAL
SHUTDOWN
OFF TIMER
Complete
Start
LOGIC +
-
CSP
+
-
UVLO
VIN
CSN
VCC
REGULATOR
VCC
VCC
UVLO
1.24 V
5 µA
5R
R
R
1.24 V
22 µA
COFF
+
-
10
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
SNVS602L MARCH 2009REVISED JUNE 2016
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8 Detailed Description
8.1 Overview
The LM3409/09HV are P-channel MOSFET (PFET) controllers for step-down (buck) current regulators which are
ideal for driving LED loads. They have wide input voltage range allowing for regulation of a variety of LED loads.
The high-side differential current sense, with low adjustable threshold voltage, provides an excellent method for
regulating output current while maintaining high system efficiency.
The LM3409/09HV uses a Controlled Off-Time (COFT) architecture that allows the converter to be operated in
both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) with no external control
loop compensation, while providing an inherent cycle-by-cycle current limit. The adjustable current sense
threshold provides the capability to amplitude (analog) dim the LED current over the full range and the fast output
enable/disable function allows for high frequency PWM dimming using no external components.
When designing, the maximum attainable LED current is not internally limited because the LM3409/09HV is a
controller. Instead it is a function of the system operating point, component choices, and switching frequency
allowing the LM3409/09HV to easily provide constant currents up to 5A. This simple controller contains all the
features necessary to implement a high-efficiency versatile LED driver.
8.2 Functional Block Diagram
t
iL (t)
üiL-
PP
IL-MAX
IL-MIN
IL
0
TS
tON = DTStOFF = (1-D)TS
D = IN
VxO
V
11
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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8.3 Feature Description
8.3.1 Buck Current Regulators
The buck regulator is unique among non-isolated topologies due to the direct connection of the inductor to the
load during the entire switching cycle. An inductor will control the rate of change of current that flows through it,
therefore a direct connection to the load is excellent for current regulation. A buck current regulator, using the
LM3409/09HV, is shown in the Application and Implementation section. During the time that the PFET (Q1) is
turned on (tON), the input voltage charges up the inductor (L1). When Q1 is turned off (tOFF), the re-circulating
diode (D1) becomes forward biased and L1 discharges. During both intervals, the current is supplied to the load
keeping the LEDs forward biased. Figure 19 shows the inductor current (iL(t)) waveform for a buck converter
operating in CCM.
The average inductor current (IL) is equal to the average output LED current (ILED), therefore if ILis tightly
controlled, ILED will be well regulated. As the system changes input voltage or output voltage, duty cycle (D) is
varied to regulate ILand ultimately ILED. For any buck regulator, D is simply the conversion ratio divided by the
efficiency (η):
(1)
Figure 19. Ideal CCM Buck Converter Inductor Current iL(t)
8.3.2 Controlled Off-Time (COFT) Architecture
The COFT architecture is used by the LM3409/09HV to control ILED. It is a combination of peak current detection
and a one-shot off-timer that varies with output voltage. D is indirectly controlled by changes in both tOFF and tON,
which vary depending on the operating point. This creates a variable switching frequency over the entire
operating range. This type of hysteretic control eliminates the need for control loop compensation necessary in
many switching regulators, simplifying the design process and providing fast transient response.
8.3.2.1 Adjustable Peak Current Control
At the beginning of a switching period, PFET Q1 is turned on and inductor current increases. Once peak current
is detected, Q1 is turned off, the diode D1 forward biases, and inductor current decreases. Figure 20 shows how
peak current detection is accomplished using the differential voltage signal created as current flows through the
current setting resistor (RSNS). The voltage across RSNS (VSNS) is compared to the adjustable current sense
threshold (VCST) and Q1 is turned off when VSNS exceeds VCST, providing that tON is greater than the minimum
possible tON (typically 115ns).
CST 5
V=ADJ
V5
5
=EXT
RA1 x
=#
EXT
RAx#
=5
R=
x248 mV
5
1.24V ==
VADJ
R5x
VADJ
VCST
CSP
5 V
1.24 V
5 µA
5R
R
R
+
-
-
+
IT
ENDS
VIN
+
-
CSN
IADJ
+
-
GND
Optional
PGATE
LED+
LED-
RSNS
+- VSNS
D1
L1
Q1
VADJ REXT
IL
VCST
tON
LM3409/09HV
12
LM3409
,
LM3409-Q1
,
LM3409HV
,
LM3409HV-Q1
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Feature Description (continued)
Figure 20. Peak Current Control Circuit
There are three different methods to set the current sense threshold (VCST) using the multi-function IADJ pin:
1. IADJ pin left open: 5 µA internal current source biases the Zener diode and clamps the IADJ pin voltage
(VADJ) at 1.24 V causing the maximum threshold voltage:
(2)
2. External voltage (VADJ) of 0 V to 1.24 V: Apply to the IADJ pin to adjust VCST from 0V to 248mV. If the VADJ
voltage is adjustable, analog dimming can be achieved.
3. External resistor (REXT) placed from IADJ pin to ground: 5 µA current source sets the VADJ voltage and
corresponding threshold voltage:
(3)
8.3.2.2 Controlled Off-Time
Once Q1 is turned off, it remains off for a constant time (tOFF) which is preset by an external resistor (ROFF), an
external capacitor (COFF), and the output voltage (VO) as shown in Figure 21. Because ILED is tightly regulated,
VOwill remain nearly constant over widely varying input voltage and temperature yielding a nearly constant tOFF.
OFF
OFF OFF
t
R C
COFF O
OFF OFF
dv (t) V e
dt R C
æ ö
-ç ÷
´
è ø
=´
vCOFF(t)
t
VO
0
ROFF x COFF
dvCOFF
dt
1.24
tOFF
-1 1.24V
O
V
x-
=OFFOFF (COFF + 20 pF)Rt xln ¸
¸
¹
·
¨
¨
©
§
VO
ROFF
COFF
+
-
COFF
1.24 V
tOFF
Control
Logic
to
PGATE
Drive -
+
vCOFF
LM3409/09HV
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,
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,
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Feature Description (continued)
Figure 21. Off-Time Control Circuit
At the start of tOFF, the voltage across COFF (vCOFF(t)) is zero and the capacitor begins charging according to the
time constant provided by ROFF and COFF. When vCOFF(t) reaches the off-time threshold (VOFT = 1.24 V), then the
off-time is terminated and vCOFF(t) is reset to zero. tOFF is calculated as follows:
(4)
In reality, there is typically 20 pF parasitic capacitance at the off-timer pin in parallel with COFF, which is
accounted for in the calculation of tOFF. Also, it should be noted that the tOFF equation has a preceding negative
sign because the result of the logarithm should be negative for a properly designed circuit. The resulting tOFF is a
positive value as long as VO> 1.24 V. If VO< 1.24 V, the off-timer cannot reach VOFT and an internally limited
maximum off-time (typically 300 µs) will occur.
Figure 22. Exponential Charging Function vCOFF(t)
Although the tOFF equation is non-linear, tOFF is actually very linear in most applications. Ignoring the 20-pF
parasitic capacitance at the COFF pin, vCOFF(t) is plotted in Figure 22. The time derivative of vCOFF(t) can be
calculated to find a linear approximation to the tOFF equation:
(5)
When tOFF << ROFF x COFF (equivalent to when VO>> 1.24V), the slope of the function is essentially linear and
tOFF can be approximated as a current source charging COFF:
MAXLLLED 2
III -
== --
=OFFO tV x
ADJ
V
SNS
R5x
PPL
i'-L12x
-SNS
MAXTMAXL R
II == -=SNS
R5xADJ
V
CST
V
vSNS (t)
VCST
t
0tON tOFF
|OFFOFF CR24.1 xx L1
PPL
i'-
iPPL =
'-L1
OFFO (COFF + 20 pF)RV xx- 1ln -x ¸
¸
¹
·
¨
¨
©
§
O
VV24.1
OFF
t|
O
OFFOFF
VCRV24.1 xx
14
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Feature Description (continued)
(6)
Using the actual tOFF equation, the inductor current ripple (ΔiL-PP) of a buck current regulator operating in CCM is:
(7)
Using the tOFF approximation, the equation is reduced to:
(8)
NOTE
ΔiL-PP is independent of both VIN and VOwhen in CCM.
The ΔiL-PP approximation only depends on ROFF, COFF, and L1, therefore the ripple is essentially constant over
the operating range as long as VO>> 1.24V (when the tOFF approximation is valid). An exception to the tOFF
approximation occurs if the IADJ pin is used to analog dim. As the LED/inductor current decreases, the converter
will eventually enter DCM and the ripple will decrease with the peak current threshold. The approximation shows
how the LM3409/09HV achieves constant ripple over a wide operating range, however tOFF should be calculated
using the actual equation first presented.
8.3.3 Average LED Current
For a buck converter, the average LED current is simply the average inductor current.
Figure 23. Sense Voltage vSNS(t)
Using the COFT architecture, the peak transistor current (IT-MAX) is sensed as shown in Figure 23, which is equal
to the peak inductor current (IL-MAX) given by the following equation:
(9)
Because IL-MAX is set using peak current control and ΔiL-PP is set using the controlled off-timer, ILand
correspondingly ILED can be calculated as follows:
(10)
SW 1
f=1
=
OFF
t+
¸
¸
¹
·
¨
¨
©
§1MAXL LI x
-
OIN VV -
OFFON tt +
SW
f= =
1IN
V
¨
¨
©
§
xK
-¸
¸
¹
·
O
V
OFF
t
D1-
OFF
t
MINPPL
i>
'-- mV24
SNS
R
iL(t)
t
0tOFF
0
IL-MAX-H
IL-MAX-L
IL-MAX
tOFF
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Feature Description (continued)
The threshold voltage VCST seen by the high-side sense comparator is affected by the comparator’s input offset
voltage, which causes an error in the calculation of IL-MAX and ultimately ILED. To mitigate this problem, the
polarity of the comparator inputs is swapped every cycle, which causes the actual IL-MAX to alternate between two
peak values (IL-MAXH and IL-MAXL), equidistant from the theoretical IL-MAX as shown in Figure 24. ILED remains
accurate through this averaging.
Figure 24. Inductor Current iL(t) Showing IL-MAX Offset
8.3.4 Inductor Current Ripple
Because the LM3409/09HV swaps the polarity of the differential current sense comparator every cycle, a
minimum inductor current ripple (ΔiL-PP) is necessary to maintain accurate ILED regulation. Referring to Figure 24,
the first tON is terminated at the higher of the two polarity-swapped thresholds (corresponding to IL-MAXH). During
the following tOFF, iLdecreases until the second tON begins. If tOFF is too short, then as the second tON begins, iL
will still be above the lower peak current threshold (corresponding to IL-MAXL) and a minimum tON pulse will follow.
This will result in degraded ILED regulation. The minimum inductor current ripple (ΔiL-PP-MIN) should adhere to the
following equation to ensure accurate ILED regulation:
(11)
8.3.5 Switching Frequency
The switching frequency is dependent upon the actual operating point (VIN and VO). VOwill remain relatively
constant for a given application, therefore the switching frequency will vary with VIN (frequency increases as VIN
increases). The target switching frequency (fSW) at the nominal operating point is selected based on the tradeoffs
between efficiency (better at low frequency) and solution size/cost (smaller at high frequency). The off-time of the
LM3409/09HV can be programmed for switching frequencies up to 5 MHz (theoretical limit imposed by minimum
tON). In practice, switching frequencies higher than 1MHz may be difficult to obtain due to gate drive limitations,
high input voltage, and thermal considerations.
At CCM operating points, fSW is defined as:
(12)
At DCM operating points, fSW is defined as:
(13)
LEDDIMLEDDIM IDI x
=
-
tOFF
iLED (t)
ILED-MAX
t
IDIM-LED
0
DDIM x TDIM
TDIM
ILED
>IN
VO
V
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Feature Description (continued)
In the CCM equation, it is apparent that the efficiency (η) factors into the switching frequency calculation.
Efficiency is hard to estimate and, because switching frequency varies with input voltage, accuracy in setting the
nominal switching frequency is not critical. Therefore, a general rule of thumb for the LM3409/09HV is to assume
an efficiency between 85% and 100%. When approximating efficiency to target a nominal switching frequency,
the following condition must be met:
(14)
Figure 25. LED Current iLED(t) During EN Pin PWM Dimming
8.3.6 PWM Dimming Using the EN Pin
The enable pin (EN) is a TTL compatible input for PWM dimming of the LED. A logic low (below 0.5V) at EN will
disable the internal driver and shut off the current flow to the LED array. While the EN pin is in a logic low state
the support circuitry (driver, bandgap, VCC regulator) remains active to minimize the time needed to turn the LED
array back on when the EN pin sees a logic high (above 1.74 V).
Figure 25 shows the LED current (iLED(t)) during PWM dimming where duty cycle (DDIM) is the percentage of the
dimming period (TDIM) that the PFET is switching. For the remainder of TDIM, the PFET is disabled. The resulting
dimmed average LED current (IDIM-LED) is:
(15)
The LED current rise and fall times (which are limited by the slew rate of the inductor as well as the delay from
activation of the EN pin to the response of the external PFET) limit the achievable TDIM and DDIM. In general,
dimming frequency should be at least one order of magnitude lower than the steady state switching frequency to
prevent aliasing. However, for good linear response across the entire dimming range, the dimming frequency
may need to be even lower.
8.3.7 High Voltage Negative BIAS Regulator
The LM3409/09HV contains an internal linear regulator where the steady state VCC pin voltage is typically 6.2 V
below the voltage at the VIN pin. The VCC pin should be bypassed to the VIN pin with at least 1µF of ceramic
capacitance connected as close as possible to the IC.
ROFF2 = ROFF1 × VDD
ILED × RDS (on )
VDD
ILED Dim
FET
ROFF2
COFF
COFF
PWM
Gate
Driver
VDD
LM3409/09HV
ROFF1
tOFF
iLED (t)
ILED-MAX
t
IDIM-LED
0
DDIM x TDIM
TDIM
ILED
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Feature Description (continued)
8.3.8 External Parallel FET PWM Dimming
Figure 26. Ideal LED Current iLED(t) During Parallel FET Dimming
Any buck topology LED driver is a good candidate for parallel FET dimming because high slew rates are
achievable, due to the fact that no output capacitance is required. This allows for much higher dimming
frequencies than are achievable using the EN pin. When using external parallel FET dimming, a situation can
arise where maximum off-time occurs due to a shorted output. To mitigate this situation, a secondary voltage
(VDD) should be used as shown in Figure 27.
Figure 27. External Parallel FET Dimming Circuit
A small diode is connected in series with the off time resistor calculated for nominal operation from the output,
ROFF1. Then connect a small diode from the secondary voltage along with another resistor, ROFF2. The secondary
voltage can be any voltage as long as it is greater than 2V. The value of ROFF2 can be calculated using
Equation 16.
(16)
The ideal LED current waveform iLED(t) during parallel FET PWM dimming is very similar to the EN pin PWM
dimming shown previously. The LED current does not rise and fall infinitely fast as shown in Figure 26 however
with this method, only the speed of the parallel Dim FET ultimately limits the dimming frequency and dimming
duty cycle. This allows for much faster PWM dimming than can be attained with the EN pin.
18
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8.4 Device Functional Modes
8.4.1 Low-Power Shutdown
The LM3409/09HV can be placed into a low-power shutdown (typically 110 µA) by grounding the EN terminal
(any voltage below 0.5 V) until VCC drops below the VCC UVLO threshold (typically 3.73 V). During normal
operation this terminal should be tied to a voltage above 1.74 V and below absolute maximum input voltage
rating.
8.4.2 Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction
temperature is exceeded. The threshold for thermal shutdown is 160°C with 15°C of hysteresis (both values
typical). During thermal shutdown the PFET and driver are disabled.