PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD44165084, 44165184, 44165364 18M-BIT QDRTMII SRAM 4-WORD BURST OPERATION Description The PD44165084 is a 2,097,152-word by 8-bit, the PD44165184 is a 1,048,576-word by 18-bit and the PD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The PD44165084, PD44165184 and PD44165364 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC FBGA. Features * 1.8 0.1 V power supply and HSTL I/O * DLL circuitry for wide output data valid window and future frequency scaling * Separate independent read and write data ports with concurrent transactions * 100% bus utilization DDR READ and WRITE operation * Four-tick burst for reduced address frequency * Two input clocks (K and /K) for precise DDR timing at clock rising edges only * Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device * Internally self-timed write control * Clock-stop capability with s restart * User programmable impedence output * Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz) * Simple control logic for easy depth expansion * JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M15825EJ2V0DS00 (2nd edition) Date Published April 2002 NS CP(K) Printed in Japan The mark shows major revised points. (c) 2001 PD44165084, 44165184, 44165364 Ordering Information Part number Cycle Clock Time Frequency ns MHz PD44165084F5-E30-EQ1 3.0 333 PD44165084F5-E33-EQ1 3.3 300 PD44165084F5-E40-EQ1 4.0 250 PD44165084F5-E50-EQ1 5.0 200 PD44165084F5-E60-EQ1 6.0 167 PD44165184F5-E30-EQ1 3.0 333 PD44165184F5-E33-EQ1 3.3 300 PD44165184F5-E40-EQ1 4.0 250 PD44165184F5-E50-EQ1 5.0 200 PD44165184F5-E60-EQ1 6.0 167 PD44165364F5-E30-EQ1 3.0 333 PD44165364F5-E33-EQ1 3.3 300 PD44165364F5-E40-EQ1 4.0 250 PD44165364F5-E50-EQ1 5.0 200 PD44165364F5-E60-EQ1 6.0 167 2 Organization Core Supply (word x bit) Voltage I/O Package Interface V 2 M x 8-bit 1.8 0.1 HSTL 165-pin PLASTIC FBGA (13 x 15) 1 M x 18-bit 512 K x 36-bit Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Pin Configurations (Marking Side) /xxx indicates active low signal. 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44165084F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS A /W /NW1 /K NC /R A VSS CQ B NC NC NC A NC K /NW0 A NC NC Q3 C NC NC NC VSS A NC A VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D7 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q7 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /NW0, /NW1 : Nybble Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground ZQ : Output impedance matching NC : No connection /DLL : DLL disable Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M15825EJ2V0DS 3 PD44165084, 44165184, 44165364 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44165184F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS NC /W /BW1 /K NC /R A VSS CQ B NC Q9 D9 A NC K /BW0 A NC NC Q8 C NC NC D10 VSS A NC A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D17 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q17 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /BW0, /BW1 : Byte Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground ZQ : Output impedance matching NC : No connection /DLL : DLL disable Remark Refer to Package Drawing for the index mark. 4 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 165-pin PLASTIC FBGA (13 x 15) (Top View) [PD44165364F5-EQ1] 1 2 3 4 5 6 7 8 9 10 11 A /CQ VSS NC /W /BW2 /K /BW1 /R NC VSS CQ B Q27 Q18 D18 A /BW3 K /BW0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H /DLL VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A /C A A A TMS TDI A : Address inputs TMS : IEEE 1149.1 Test input D0 to D35 : Data inputs TDI : IEEE 1149.1 Test input Q0 to Q35 : Data outputs TCK : IEEE 1149.1 Clock input /R : Read input TDO : IEEE 1149.1 Test output /W : Write input VREF : HSTL input reference input /BW0 to /BW3 : Byte Write data select VDD : Power Supply K, /K : Input clock VDDQ : Power Supply C, /C : Output clock VSS : Ground ZQ : Output impedance matching NC : No connection /DLL : DLL disable Remark Refer to Package Drawing for the index mark. Preliminary Data Sheet M15825EJ2V0DS 5 PD44165084, 44165184, 44165364 Pin Identification Symbol A /R /W /NWx /BWx K, /K C, /C Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices. All transactions operate on a burst of four words (two clock period of bus activity). These inputs are ignored when device is deselected. Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the subsequent rising edge of K. Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K and is ignored on the subsequent rising edge of K. Synchronous Byte Writes (Nybble Writes on x8): When LOW these inputs cause their respective byte or nybble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of C is used as the output timing reference for first and third output data. The rising edge of /C is used as the output reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. /DLL DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. TMS TDI TCK Description VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Configurations for ball site location of individual signals. x8 device uses D0-D7. Remaining signals are NC. x18 device uses D0-D17. Remaining signals are NC. x36 device uses D0-D35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. CQ, /CQ TDO IEEE 1149.1 Test Output: 1.8V I/O level. Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site location of individual signals. x8 device uses Q0-Q7. Remaining signals are NC. x18 device uses Q0-Q17. Remaining signals are NC. x36 device uses Q0-Q35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. VDD Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. VSS Power Supply: Ground NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. 6 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Block Diagram [PD44165084] 19 ADDRESS /R ADDRESS /W 19 REGISTRY & LOGIC K /W MUX /NW0 MEMORY ARRAY 16 Q0 - Q7 OUTPUT BUFFER 16 16 OUTPUT SELECT & LOGIC OUTPUT REGISTER REGISTRY /R 2 x 32 SENSE AMPS D0 - D7 19 WRITE DRIVER 8 DATA WRITE REGISTER /NW1 8 16 16 2 CQ, /CQ MUX K K /K C C, /C OR K, /K [PD44165184] 18 ADDRESS /R ADDRESS /W 18 REGISTRY & LOGIC K /W MUX /BW0 36 36 MEMORY ARRAY 36 OUTPUT BUFFER 36 36 OUTPUT SELECT & LOGIC 18 OUTPUT REGISTER REGISTRY /R 2 x 72 SENSE AMPS D0 - D17 18 WRITE DRIVER 18 DATA WRITE REGISTER /BW1 Q0 - Q17 2 CQ, /CQ MUX K K /K C C, /C OR K, /K [PD44165364] 17 ADDRESS /R ADDRESS /W 17 REGISTRY & LOGIC K /W MUX ARRAY 72 OUTPUT BUFFER /R MEMORY 36 72 OUTPUT SELECT 72 2 x 144 SENSE AMPS & LOGIC 17 WRITE DRIVER REGISTRY WRITE REGISTER DATA 36 D0 - D35 72 72 OUTPUT REGISTER /BW0 /BW1 /BW2 /BW3 Q0 - Q35 2 CQ, /CQ MUX K /K K C Preliminary Data Sheet M15825EJ2V0DS C, /C OR K, /K 7 PD44165084, 44165184, 44165364 Truth Table Operation WRITE cycle CLK /R /W LH H L D or Q Data in Load address, input write data on two Input data DA(A+0) DA(A+1) DA(A+2) DA(A+3) consecutive K and /K rising edge Input clock K(t+1) /K(t+1) K(t+2) /K(t+2) Load address, read data on two Output data QA(A+0) QA(A+1) QA(A+2) QA(A+3) consecutive C and /C rising edge Output clock /C(t+1) C(t+2) /C(t+2) C(t+3) LH READ cycle NOP (No operation) STANDBY(Clock stopped) L X Data out LH H H D=X or Q=Hi-Z Stopped X X Previous state Remarks 1. H : High level, L : Low level, x : don't care, : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then data outputs are delivered at K and /K rising edges. 3. /R and /W must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. If this signal was LOW to initiate the previous cycle, this signal becomes a don't care for this operation however it is strongly recommended that this signal is brought HIGH as shown in the truth table. 8. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The device will ignore the second request. 8 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Byte Write Operation [PD44165084] Operation Write D0-7 Write D0-3 Write D4-7 Write nothing K /K /NW0 /NW1 LH - 0 0 - LH 0 0 LH - 0 1 - LH 0 1 LH - 1 0 - LH 1 0 LH - 1 1 - LH 1 1 Remarks 1. H : High level, L : Low level, : rising edge. 2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [PD44165184] K /K /BW0 /BW1 Write D0-17 Operation LH - 0 0 - LH 0 0 Write D0-8 LH - 0 1 - LH 0 1 Write D9-17 LH - 1 0 - LH 1 0 Write nothing LH - 1 1 - LH 1 1 Remarks 1. H : High level, L : Low level, : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [PD44165364] Operation Write D0-35 Write D0-8 K /K /BW0 /BW1 /BW2 /BW3 LH - 0 0 0 0 - LH 0 0 0 0 LH - 0 1 1 1 - LH 0 1 1 1 LH - 1 0 1 1 - LH 1 0 1 1 LH - 1 1 0 1 - LH 1 1 0 1 Write D27-35 LH - 1 1 1 0 - LH 1 1 1 0 Write nothing LH - 1 1 1 1 - LH 1 1 1 1 Write D9-17 Write D18-26 Remarks 1. H : High level, L : Low level, : rising edge. 2. Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Preliminary Data Sheet M15825EJ2V0DS 9 PD44165084, 44165184, 44165364 Bus Cycle State Diagram LOAD NEW READ ADDRESS; R_Count = 0; R_Init = 1 LOAD NEW WRITE ADDRESS; W_Count = 0 Always /W = L & W_Count = 4 /R = L & R_Count = 4 WRITE DOUBLE; W_count = W_Count+2 /W = L R_Init = 0 Always READ DOUBLE; R_Count = R_Count+2 /R = H & R_Count = 4 W_Count = 2 Always R_Count = 2 Always /R = L INCREMENT WRITE Note 1 ADDRESS BY TWO /W = H & W_Count = 4 INCREMENT READ Note 1 ADDRESS BY TWO R_Init = 0 /R = H /W = H WRITE PORT NOP Power UP Supply voltage provided Supply voltage provided READ PORT NOP R_Init = 0 Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 3. State machine control timing is controlled by K. 10 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD -0.5 +2.9 V VDDQ -0.5 VDD V Input voltage VIN -0.5 VDD + 0.5 (2.9 V MAX.) V Input / Output voltage VI/O -0.5 VDDQ + 0.5 (2.9 V MAX.) V Junction temperature Tj +125 C Storage temperature Tstg +125 C Supply voltage Output supply voltage Caution -55 Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (Tj = 20 to 110 C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit Note VDD 1.7 1.9 V VDDQ 1.4 VDD V High level input voltage VIH VREF + 0.1 VDDQ + 0.3 V 1 Low level input voltage VIL -0.3 VREF - 0.1 V 1 Clock input voltage VIN -0.3 VDDQ + 0.3 V 1 Reference voltage VREF 0.68 0.95 V Output supply voltage Note1 Overshoot: VIH (AC) VDD + 0.7 V for t TKHKH/2 Undershoot: VIL (AC) - 0.5V for t TKHKH/2 Power-up: VIH VDDQ + 0.3V and VDD 1.7V and VDDQ 1.4V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than TKHKH (MIN.). Capacitance (TA = 25 C, f = 1MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance(Address, Control) CIN VIN = 0 V 4 5 pF Input / Output capacitance(D, Q) CI/O VI/O = 0 V 6 7 pF Clock Input capacitance Cclk Vclk = 0 V 5 6 pF Remark These parameters are periodically sampled and not 100% tested. Preliminary Data Sheet M15825EJ2V0DS 11 PD44165084, 44165184, 44165364 DC Characteristics (Tj = 20 to 110C, VDD = 1.8 0.1 V) Parameter Symbol Test condition MIN. TYP. MAX. x8, x18 Unit x36 Input leakage current ILI -2 - +2 A I/O leakage current ILO -2 - +2 A Operating supply current IDD (Read Write cycle) Standby supply current ISB1 (NOP) High level output voltage VOH Low level output voltage VIN VIL or VIN VIH, -E30 525 710 II/O = 0 mA -E33 475 640 Cycle = MAX. -E40 400 545 -E50 330 445 -E60 280 380 VIN VIL or VIN VIH, -E30 255 265 II/O = 0 mA -E33 235 245 Cycle = MAX. -E40 200 210 -E50 170 180 -E60 145 155 VOH(Low) |IOH| 0.1 mA Note1 VOL(Low) IOL 0.1 mA VOL Note2 VDDQ - 0.2 - VDDQ VDDQ/2-0.08 - VDDQ/2+0.08 VSS - 0.2 VDDQ/2-0.08 - VDDQ/2+0.08 mA mA V V 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 3. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 12 Preliminary Data Sheet M15825EJ2V0DS 3,4 3,4 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . 4. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Note 3,4 3,4 PD44165084, 44165184, 44165364 AC Characteristics (Tj = 20 C to 110 C, VDD = 1.8 0.1 V) AC Test Conditions Input waveform (Rise / Fall time 0.3 ns) 1.25 V 0.75 V Test Points 0.75 V 0.25 V Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition Figure 1. External load at test VDDQ / 2 0.75 V 50 VREF ZO = 50 SRAM 250 ZQ Remark CL includes capacitances of the probe and jig, and stray capacitances. Preliminary Data Sheet M15825EJ2V0DS 13 PD44165084, 44165184, 44165364 Read and Write Cycle Parameter Symbol -E30 -E33 -E40 -E50 -E60 (333 MHz) (300 MHz) (250 MHz) (200 MHz) (167 MHz) Unit Note MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Clock Average Clock cycle time (K, /K, C, /C) TKHKH Clock phase jitter (K, /K, C, /C) Clock HIGH time (K, /K, C, /C) Clock LOW time (K, /K, C, /C) 3.6 3.3 4.0 TKC var - TKHKL 1.20 4.0 5.0 0.2 - - 1.32 0.2 - - 1.6 6.0 7.5 ns 1 0.2 - 0.2 ns 2 - 2.4 - ns 5.0 6.0 0.2 - - 2.0 TKLKH 1.20 - 1.32 - 1.6 - 2.0 - 2.4 - ns Clock to /clock (K/K., C/C.) TKH /KH 1.35 - 1.49 - 1.8 - 2.2 - 2.7 - ns Clock to /clock (/KK., /CC.) T /KHKH 1.35 - 1.49 - 1.8 - 2.2 - 2.7 - ns TKHCH 0 Clock to data clock (KC., /K/C.) 3.0 1.30 0 1.45 0 1.8 0 2.3 0 2.8 ns DLL lock time (K, C) TKC lock 1,024 - 1,024 - 1,024 - 1,024 - 1,024 - Cycle K static to DLL reset TKC reset 30 - 30 - 30 - 30 - 30 - ns 3 Output Times C, /C HIGH to output valid TCHQV - 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns C, /C HIGH to output hold TCHQX - 0.27 - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns C, /C HIGH to echo clock valid TCHCQV - 0.25 - 0.27 - 0.33 - 0.36 - 0.38 ns C, /C HIGH to echo clock hold TCHCQX - 0.25 - - 0.27 - - 0.33 - - 0.36 - - 0.38 - ns CQ, /CQ HIGH to output valid TCQHQV 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns 4 CQ, /CQ HIGH to output hold TCQHQX - 0.27 - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns 4 0.27 - 0.29 - 0.35 - 0.38 - 0.40 ns - - 0.29 - - 0.35 - - 0.38 - - 0.40 - ns C HIGH to output High-Z C HIGH to output Low-Z TCHQZ - - TCHQX1 - 0.27 Setup Times Address valid to K rising edge TAVKH 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 Control inputs valid to K rising edge TIVKH 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 Data-in valid to K, /K rising edge TDVKH 0.3 - 0.33 - 0.4 - 0.5 - 0.6 - ns 5 TKHAX 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 K rising edge to control inputs hold TKHIX 0.4 - 0.4 - 0.5 - 0.6 - 0.7 - ns 5 K, /K rising edge to data-in hold TKHDX 0.3 - 0.33 - 0.4 - 0.5 - 0.6 - ns 5 Hold Times K rising edge to address hold Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.). 2. Clock phase jitter is the variance from clock rising edge to the next expected colck rising edge. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 5. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN). 4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters. 5. VDDQ is 1.5 VDC. 14 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Read and Write Timing 1 2 WRITE READ WRITE READ NOP 3 4 5 NOP 6 7 K TKHKL TKLKH TKHKH TKH/KH T/KHKH /K /R TKHIX TIVKH TKHIX TIVKH /W A0 Address A2 A1 TDVKH TAVKH TKHAX Data in Data out Qx2 Qx3 A3 TKHDX TDVKH TKHDX D10 D11 D12 D13 D30 D31 Q00 Q01 Q02 Q03 Q20 Q21 TCHQX1 TCHQX Q22 TCQHQV TCHQX TCHQV D32 D33 Q23 TCHQZ TCHQV CQ TCHCQX TCHCQV /CQ TKHCH TCHCQX TCHCQV C TKHKL TKLKH TKHKH TKH/KH T/KHKH TKHCH /C Remarks 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following A0,i.e.,A0+1. 2. Outputs are disable (High-Z) one clock cycle after a NOP. 3. In this example, if address A0=A1, data Q00=D10, Q01=D11. Write data is forwarded immediately as read results. Preliminary Data Sheet M15825EJ2V0DS 15 PD44165084, 44165184, 44165364 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name TCK Pin assignments 2R Description Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test Mode Select. This is the command input for the TAP controller state machine. TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is deter-mined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (20 C Tj 110 C, 1.7 V VDD 1.9 V, unless otherwise noted) Parameter Symbol Conditions MIN. TYP. MAX. Unit JTAG Input leakage current ILI 0 V VIN VDD -5.0 - +5.0 A JTAG I/O leakage current ILO 0 V VIN VDDQ , -5.0 - +5.0 A Outputs disabled JTAG input high voltage VIH 1.3 - VDD+0.3 V JTAG input low voltage VIL -0.3 - +0.5 V JTAG output high voltage JTAG output low voltage 16 VOH1 | IOHC | = 100 A 1.6 - - V VOH2 | IOHT | = 2 mA 1.4 - - V VOL1 IOLC = 100 A - - 0.2 V VOL2 IOLT = 2 mA - - 0.4 V Preliminary Data Sheet M15825EJ2V0DS Note PD44165084, 44165184, 44165364 JTAG AC Test Conditions Input waveform (Rise / Fall time 1 ns) 1.8 V 0.9 V Test Points 0.9 V 0.9 V Test Points 0.9 V 0V Output waveform Output load Figure 2. External load at test VTT = 0.9 V 50 ZO = 50 TDO 20 pF Preliminary Data Sheet M15825EJ2V0DS 17 PD44165084, 44165184, 44165364 JTAG AC Characteristics (Tj = 5 to 110 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 100 - - ns Clock Clock cycle time tTHTH Clock frequency fTF - - 10 MHz Clock high time tTHTL 40 - - ns Clock low time tTLTH 40 - - ns TCK low to TDO unknown tTLOX 0 - - ns TCK low to TDO valid tTLOV - - 20 ns TDI valid to TCK high tDVTH 10 - - ns TCK high to TDI invalid tTHDX 10 - - ns tMVTH 10 - - ns tCS 10 - - ns tTHMX 10 - - ns tCH 10 - - ns Output time Setup time TMS setup time Capture setup time Hold time TDI hold time Capture hold time JTAG Timing Diagram 18 Preliminary Data Sheet M15825EJ2V0DS Note PD44165084, 44165184, 44165364 Scan Register Definition (1) Register name Instruction register Description The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. Scan Register Definition (2) Register name Bit size Unit Instruction register 3 bit Bypass register 1 bit ID register 32 bit Boundary register 107 bit ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit PD44165084 2M x 8 XXXX 0000 0000 0000 1111 00000010000 1 PD44165184 1M x 18 XXXX 0000 0000 0001 0000 00000010000 1 PD44165364 512K x 36 XXXX 0000 0000 0001 0001 00000010000 1 Preliminary Data Sheet M15825EJ2V0DS 19 PD44165084, 44165184, 44165364 SCAN Exit Order Bit no. Signal name x8 x36 Bit Signal name ID no. x8 x18 Bump Bit Signal name Bump x36 ID no. x8 x18 x36 ID 1 /C 6R 37 NC NC D15 10D 73 NC NC Q28 2C 2 C 6P 38 NC NC Q15 9E 74 Q4 Q11 Q20 3E 3 A 6N 39 NC Q7 Q7 10C 75 D4 D11 D20 2D 4 A 7P 40 NC D7 D7 11D 76 NC NC D29 2E 5 A 7N 41 NC NC D16 9C 77 NC NC Q29 1E 6 A 7R 42 NC NC Q16 9D 78 NC Q12 Q21 2F 7 A 8R 43 Q3 Q8 Q8 11B 79 NC D12 D21 3F 8 A 8P 44 D3 D8 D8 11C 80 NC NC D30 1G 9 A 9R 45 NC NC D17 9B 81 NC NC Q30 1F NC NC Q17 10B 82 Q5 Q13 Q22 3G 10 NC Q0 Q0 11P 46 11 NC D0 D0 10P 47 CQ 11A 83 D5 D13 D22 2G 12 NC NC D9 10N 48 Vss 10A 84 NC NC D31 1J 13 NC NC Q9 9P 49 9A 85 NC NC Q31 2J 14 NC Q1 Q1 10M 50 A 8B 86 NC Q14 Q23 3K 15 NC D1 D1 11N 51 A 7C 87 NC D14 D23 3J 16 NC NC D10 9M 52 NC 6C 88 NC NC D32 2K 17 NC NC Q10 9N 53 /R 8A 89 NC NC Q32 1K 18 Q0 Q2 Q2 11L 54 /BW1 7A 90 Q6 Q15 Q24 2L 19 D0 D2 D2 11M 55 /NW0 /BW0 /BW0 7B 91 D6 D15 D24 3L 20 NC NC D11 9L 56 K 6B 92 NC NC D33 1M 21 NC NC Q11 10L 57 /K 6A 93 NC NC Q33 1L 22 NC Q3 Q3 11K 58 /BW3 5B 94 NC Q16 Q25 3N 23 NC D3 D3 10K 59 /NW1 /BW1 /BW2 5A 95 NC D16 D25 3M 24 NC NC D12 9J 60 /W 4A 96 NC NC D34 1N 25 NC NC Q12 9K 61 A 5C 97 NC NC Q34 2M 26 Q1 Q4 Q4 10J 62 A 4B 98 Q7 Q17 Q26 3P 27 D1 D4 D4 11J 63 3A 99 D7 D17 D26 2N 11H 64 Vss 2A 100 NC NC D35 2P /CQ 1A 101 NC NC Q35 1P 28 20 x18 Bump ZQ A NC NC A A NC NC NC NC NC 29 NC NC D13 10G 65 30 NC NC Q13 9G 66 NC Q9 Q18 2B 102 A 3R 31 NC Q5 Q5 11F 67 NC D9 D18 3B 103 A 4R 32 NC D5 D5 11G 68 NC NC D27 1C 104 A 4P 33 NC NC D14 9F 69 NC NC Q27 1B 105 A 5P 34 NC NC Q14 10F 70 NC Q10 Q19 3D 106 A 5N 35 Q2 Q6 Q6 11E 71 NC D10 D19 3C 107 A 5R 36 D2 D6 D6 10E 72 NC NC D28 1D Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 JTAG Instructions Instructions EXTEST Description EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the RAM output are forced to Hi-Z any time the instruction is loaded. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE SAMPLE is a Standard 1149.1 mandatory public instruction. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1 compliant. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (Hi-Z) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Coding IR2 IR1 IR0 Instruction Note 0 0 0 EXTEST 1 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 RESERVED 1 0 0 SAMPLE 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS 1 Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH. Preliminary Data Sheet M15825EJ2V0DS 21 PD44165084, 44165184, 44165364 TAP Controller State Diagram Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected. 22 Preliminary Data Sheet M15825EJ2V0DS Test Logic Operation (Instruction Scan) TCK Run-Test/Idle Update-IR Exit1-IR Shift-IR TDI 23 PD44165084, 44165184, 44165364 Output from Instruction Register Output from Instruction Register Exit2-IR Pause-IR Exit1-IR Shift-IR Capture-IR Output Inactive New Instruction IDCODE Instruction Register state Select-IR-Scan Select-DR-Scan Run-Test/Idle TDO Test-Logic-Reset Controller state Preliminary Data Sheet M15825EJ2V0DS TMS 24 Test Logic Operation (Data Scan) TCK Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR TDI PD44165084, 44165184, 44165364 Output from Instruction Register Output from Instruction Register Exit2-DR Pause-DR Exit1-DR Shift-DR Output Inactive IDCODE Instruction Instruction Register state Capture-DR Select-DR-Scan TDO Run-Test/Idle Controller state Preliminary Data Sheet M15825EJ2V0DS TMS PD44165084, 44165184, 44165364 Package Drawing 165-PIN PLASTIC FBGA (13x15) E w S B ZD ZE B 11 10 9 8 7 6 5 4 3 2 1 A D R P N M L K J H G F E D C B A w S A INDEX MARK A2 y1 S h A S e y S b x M A1 S AB This package drawing is a preliminary version. It may be changed in the future. Preliminary Data Sheet M15825EJ2V0DS ITEM D E ZD ZE e h A A1 A2 b y x w y1 MILLIMETERS 13.00 15.00 1.50 0.50 1.00 0.60 1.40 0.40 1.00 0.45 0.08 0.08 0.15 0.20 25 PD44165084, 44165184, 44165364 Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices PD44165084F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) PD44165184F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) PD44165364F5-EQ1: 165-pin PLASTIC FBGA (13 x 15) 26 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 Revision History Edition/ Date 2nd edition/ Page Type of This Previous edition edition Throughout Location (Previous edition This edition) revision Throughout Modification Pin Configurations, Pin Identification, March 2002 Description Address inputs: Ax A Scan Exit Order p.1 p.1 Modification Function Name 18M-BIT CMOS SYNCHRONOUS FAST SRAM QUAD DATA RATE 18M-BIT QDR II SRAM TM Addition p.2 p.2 p.3-5 p. 3-5 p.6 p.6 Description PD44165364 Modification Ordering Information Package code: Fx-EQx F5-EQ1 Deletion Remark Modification Pin Configurations Package code: Fx F5-EQ1 Modification Pin Identification ZQ: VDD VDDQ D0 to Dxx: K# /K p.14 p.14 Modification TKC var (MAX.) -E30: 0.08 0.2, -E33: 0.08 0.2, -E40: 0.10 0.2, -E50: 0.13 0.2, -E60: 0.15 0.2 TKH /KH (MAX.) -E30: 1.65 -, -E33: 1.82 -, -E40: 2.2 -, -E50: 2.75 -, -E60: 3.3 - Addition T /KHKH Modification TAVKH, TIVKH, TKHAX, TKHIX (MIN.) -E40: 0.4 0.5 TDVKH, TKHDX (MIN.) -E30: 0.4 0.3, -E33: 0.4 0.33, -E50: 0.6 0.5, -E60: 0.7 0.6 Addition Note 1, 2, 4 Modification Note 1 5, Note 2 3 Modification Note 3 Addition Remark 5 p.15 p.15 Addition Read and Write Timing T/KHKH p.25 p.25 Addition Package Drawing Package drawing (Preliminary version) p.26 p.26 Modification Types of Surface Mount Devices Preliminary Data Sheet M15825EJ2V0DS Package code: Fx F5-EQ1 27 PD44165084, 44165184, 44165364 [MEMO] 28 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 [MEMO] Preliminary Data Sheet M15825EJ2V0DS 29 PD44165084, 44165184, 44165364 [MEMO] 30 Preliminary Data Sheet M15825EJ2V0DS PD44165084, 44165184, 44165364 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet M15825EJ2V0DS 31 PD44165084, 44165184, 44165364 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, Hitachi, IDT, Micron Technology, Inc., NEC, and Samsung. * The information in this document is current as of April, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4