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Rev. 0.1 / Jun. 2010 1
240pin DDR3 SDRAM Unbuffered DIMM
* Hynix Semiconductor reserves the right to change products or specifications with out notice.
DDR3 SDRAM
Unbuffered DIMMs
Based on 1Gb D-Die
HMT112U6DFR8C
HMT125U6DFR8C
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Revision History
Revision No. History Draft Date Remark
0.1 Initial Release Jun. 2010 Preliminary
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Description
Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM
devices. These Unbuff ered SDRAM DIMMs are intended f or use as main memory when installed in systems
such as PCs and workstations.
Features
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number Density Organization Component Composition # of
ranks FDHS
HMT112U6DFR8C-G7/H9/PB 1GB 128Mx64 128Mx8(H5TQ1G83DFR)*8 1 X
HMT125U6DFR8C-G7/H9/PB 2GB 256Mx64 128Mx8(H5TQ1G83DFR)*16 2 X
• VDD=1.5V +/- 0.075V
• VDDQ=1.5V +/- 0.075V
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the
DDR3 SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
• Bi-directional Differential Data Strobe
• 8 bit pre- fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC
(Burst Chop) 4
• Supports ECC error correction and detection
• On Die Termination (ODT) supported
• Temperature sensor with integrated SPD (Serial
Presence Detect) EEPROM
• RoHS compliant
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Key Parameters
Speed Grade
Address Table
MT/s Grade tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns) tRP
(ns) tRAS
(ns) tRC
(ns) CL-tRCD-tRP
DDR3-1066 -G7 1.875 713.125 13.125 37.5 50.625 7-7-7
DDR3-1333 -H9 1.5 9 13.5 13.5 36 49.5 9-9-9
DDR3-1600 -PB 1.25 11 13.75 13.75 35 48.75 11-11-11
Grade Frequency [MHz] Remark
CL6 CL7 CL8 CL9 CL10 CL11
-G7 800 1066 1066
-H9 800 1066 1066 1333 1333
-PB 800 1066 1066 1333 1333 1600
1GB(1Rx8) 2GB(2Rx8)
Refresh Method 8K/64ms 8K/64ms
Row Address A0-A13 A0-A13
Column Address A0-A9 A0-A9
Bank Address BA0-BA2 BA0-BA2
Page Size 1KB 1KB
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Pin Descriptions
Pin Name Description Pin Name Description
A0–A15 SDRAM address bus SCL I2C serial bus clock for EEPROM
BA0–BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM
RAS SDRAM row address strobe SA0–SA2 I2C slave address select for EEPROM
CAS SDRAM column address strobe VDD*SDRAM core power supply
WE SDRAM write enable VDDQ*SDRAM I/O Driver power supply
S0–S1 DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply
CKE0–CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference
supply
ODT0–ODT1 On-die termination control lines VSS Power supply return (ground)
DQ0–DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply
CB0–CB7 DIMM ECC check bits NC Spare pins (no connect)
DQS0–DQS8 SDRAM data strobes
(positive line of differential pair) TEST Memory bus analysis tools
(unused on memory DIMMS)
DQS0–DQS8SDRAM data strobes
(negative line of differential pair) RESET Set DRAMs to Known State
DM0–DM8 SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
V
TT
SDRAM I/O termination supply
CK0–CK1 SDRAM clocks
(positive line of differential pair) RSVD Reserved for future use
CK0–CK1SDRAM clocks
(negative line of differential pair) - -
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
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Input/Output Functional Descriptions
Symbol Type Polarity Function
CK0–CK1
CK0–CK1SSTL Differential
crossing
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl
inputs are sampled on the crossing of positive edge of CK and negative
edge of CK. Output (read) data is reference to the crossing of CK and CK
(Both directions of crossing).
CKE0–CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down
mode, or the Self Refresh mode.
S0–S1SSTLActive Low
Enables the associated SDRAM command decoder when low and disables
the command decoder when high. When the command decoder is dis-
abled, new commands are ignored but previous operations continue. This
signal provides for external rank selection on systems with multiple ranks.
RAS, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.
ODT0–ODT1 SSTL Active High When high, termination resistance is enabled for all DQ, DQS, DQS and DM
pins, assuming this function is enabled in the Mode Register 1 (MR1).
VREFDQ Supply Reference voltage for SSTL15 I/O inputs.
VREFCA Supply Reference voltage for SSTL 15 command/address inputs.
VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
BA0–BA2 SSTL — Selects which SDRAM bank of eight is activated.
A0–A15 SSTL —
During a Bank Activate command cycle, Address input defines the row
address (RA0–RA15).
During a Read or Write command cycle, Address input defines the column
address. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled. During a Precharge com-
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which
bank(s) to precharge. If AP is high, all ba nks will be precharged regardles s
of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to
define which bank to precharge. A12(BC) is sampled during READ and
WRITE commands to determine if burst chop (on-the-fly) will be per-
formed (HIGH, no burst chop; LOW, burst chopped).
DQ0–DQ63,
CB0–CB7 SSTL — Data and Check Bit Input/Output pins.
DM0–DM8 SSTL Active High
DM is an input mask signal for write data. Input data is masked when DM
is sampled High coincident with that input data during a write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
VDD, VSS Supply Power and ground for the D DR3 SD RAM input buf fers, and core logic. VDD
and VDDQ pins are tied to VDD/VDDQ planes on these modules.
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Pin Assignments
DQS0–DQS8
DQS0–DQS8SSTL Differential
crossing Data strobe for input and output data.
SA0–SA2 — These signals are tied at the system planar to either VSS or VDDSPD to con-
figure the serial SPD EEPROM address range.
SDA — This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
VDDSPD to act as a pullup on the system board.
SCL — This signal is used to clock data into and out of the SPD EEPROM. An
external resistor may be connected from the SCL bus time to V DDSPD to act
as a pullup on the system board.
VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ
power plane. EEPROM supply is operable from 3.0V to 3.6V.
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)
Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC
1V
REFDQ VREFDQ 121
V
SS
V
SS
61 A2 A2 181 A1 A1
2V
SS
V
SS
122 DQ4 DQ4 62 VDD VDD 182 VDD VDD
3 DQ0 DQ0 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD
4DQ1 DQ1124
V
SS
V
SS
64 CK1CK1184 CK0 CK0
5
V
SS
V
SS
125 DM0 DM0 65 VDD VDD 185 CK0CK0
6DQS
0DQS0 126 NC NC 66 VDD VDD 186 VDD VDD
7 DQS0 DQS0 127
V
SS
V
SS
67 VREFCA VREFCA 187 NC EVENT
8
V
SS
V
SS
128 DQ6 DQ6 68 NC NC 188 A0 A0
9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD
10 DQ3 DQ3 130
V
SS
V
SS
70 A10 A10 190 BA12BA12
11
V
SS
V
SS
131 DQ12 DQ12 71 BA02BA02191 VDD VDD
12 DQ8 DQ8 132 DQ13 DQ13 72 VDD VDD 192 RAS RAS
13 DQ9 DQ9 133
V
SS
V
SS
73 WE WE 193 S0S0
14
V
SS
V
SS
134 DM1 DM1 74 CAS CAS 194 VDD VDD
15 DQS1DQS1 135 NC NC 75 VDD VDD 195 ODT0 ODT0
16 DQS1 DQS1 136
V
SS
V
SS
76 S1 S1 196 A13 A13
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.
Symbol Type Polarity Function
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17
V
SS
V
SS
137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD
18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC
19 DQ11 DQ11 139
V
SS
V
SS
79 NC NC 199
V
SS
V
SS
20
V
SS
V
SS
140 DQ20 DQ20 80
V
SS
V
SS
200 DQ36 DQ36
21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37
22 DQ17 DQ17 142
V
SS
V
SS
82 DQ33 DQ33 202
V
SS
V
SS
23
V
SS
V
SS
143 DM2 DM2 83
V
SS
V
SS
203 DM4 DM4
24 DQS2DQS2144 NC NC 84 DQS4DQS4 204 NC NC
25 DQS2 DQS2 145
V
SS
V
SS
85 DQS4 DQS4 205
V
SS
V
SS
26
V
SS
V
SS
146 DQ22 DQ22 86
V
SS
V
SS
206 DQ38 DQ38
27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39
28 DQ19 DQ19 148
V
SS
V
SS
88 DQ35 DQ35 208
V
SS
V
SS
29
V
SS
V
SS
149 DQ28 DQ28 89
V
SS
V
SS
209 DQ44 DQ44
30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45
31 DQ25 DQ25 151
V
SS
V
SS
91 DQ41 DQ41 211
V
SS
V
SS
32
V
SS
V
SS
152 DM3 DM3 92
V
SS
V
SS
212 DM5 DM5
33 DQS3DQS3 153 NC NC 93 DQS5DQS5 213 NC NC
34 DQS3 DQS3 154
V
SS
V
SS
94 DQS5 DQS5 214
V
SS
V
SS
35
V
SS
V
SS
155 DQ30 DQ30 95
V
SS
V
SS
215 DQ46 DQ46
36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47
37 DQ27 DQ27 157
V
SS
V
SS
97 DQ43 DQ43 217
V
SS
V
SS
38
V
SS
V
SS
158 NC CB4 98
V
SS
V
SS
218 DQ52 DQ52
39 NC CB0 159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53
40 NC CB1 160
V
SS
V
SS
100 DQ49 DQ49 220
V
SS
V
SS
41
V
SS
V
SS
161 DM8 DM8 101
V
SS
V
SS
221 DM6 DM6
42 NC DQS8 162 NC NC 102 DQS6DQS6 222 NC NC
43 NC DQS8 163
V
SS
V
SS
103 DQS6 DQS6 223
V
SS
V
SS
44
V
SS
V
SS
164 NC CB6 104
V
SS
V
SS
224 DQ54 DQ54
45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55
46 NC CB3 166
V
SS
V
SS
106 DQ51 DQ51 226
V
SS
V
SS
47
V
SS
V
SS
167 NC NC 107
V
SS
V
SS
227 DQ60 DQ60
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)
Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.
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48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61
KEY KEY 109 DQ57 DQ57 229
V
SS
V
SS
49 NC NC 169 CKE1/NC CKE1/NC 110
V
SS
V
SS
230 DM7 DM7
50 CKE0 CKE0 170 VDD VDD 111 DQS7DQS7 231 NC NC
51 VDD VDD 171 NC NC 112 DQS7 DQS7 232
V
SS
V
SS
52 BA2 BA2 172 NC NC 113
V
SS
V
SS
233 DQ62 DQ62
53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63
54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235
V
SS
V
SS
55 All All 175 A9 A9 116
V
SS
V
SS
236 VDDSPD VDDSPD
56 A72A72176 VDD VDD 117 SA0 SA0 237 SA1 SA1
57 VDD VDD 177 A82A82118 SCL SCL 238 SDA SDA
58 A52A52178 A62A62119
SA2 SA2
239
V
SS
V
SS
59 A42A42179 VDD VDD 120 VTT VTT 240 VTT VTT
60 VDD VDD 180 A32A32
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)
Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC Pin
#x64
Non-ECC x72
ECC
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.
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On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal
sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
Temperature-to-Digital Conversion Performance
Parameter Condition Min Typ Max Unit
Temperature Sensor Accuracy (Grade B)
Active Range,
75°C < TA < 95°C -± 0.5 ± 1.0 °C
Monitor Range,
40°C < TA < 125°C -± 1.0 ± 2.0 °C
-20°C < TA < 125°C -± 2.0 ± 3.0 °C
Resolution 0.25 °C
EVENT
SCL
SDA
SA0
SA1
SA2
EVENT
SCL
SDA
SA0
SA1
SA2
SPD with
Integrated
TS
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Functional Block Diagram
1GB, 128Mx64 Module(1Rank of x8)
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 0
I/O 1
I/O 2
I/O 3
D0
DM0
I/O 4
I/O 5
I/O 6
I/O 7
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
I/O 0
I/O 1
I/O 2
I/O 3
D1
I/O 4
I/O 5
I/O 6
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 0
I/O 1
I/O 2
I/O 3
D2
I/O 4
I/O 5
I/O 6
I/O 7
DM2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 4
I/O 5
I/O 6
I/O 7
DM3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 0
I/O 1
I/O 2
I/O 3
D4
DM4
I/O 4
I/O 5
I/O 6
I/O 7
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 0
I/O 1
I/O 2
I/O 3
D5
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 0
I/O 1
I/O 2
I/O 3
D6
I/O 4
I/O 5
I/O 6
I/O 7
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 0
I/O 1
I/O 2
I/O 3
D7
I/O 4
I/O 5
I/O 6
I/O 7
DM7
A0–A15 A0–A15: SDRAMs D0–D7
A0
Serial PD
A1
SA0 SA1
SDA
RAS RAS: SDRAMs D0–D7
CAS CAS: SDRAMs D0–D7
CKE0 CKE: SDRAMs D0–D7
WE WE: SDRAMs D0–D7
CS CS
CS CS
CS
CS
CS
CS
BA0–BA2 BA0–BA2: SDRAMs D0–D7
DQS0
DQS
DQS4
DQS1 DQS5
DQS
DQS2
DQS
DQS3
DQS
DM6
DQS6
DQS7
DQ15 I/O 7
DQS
DQS
DQS
DQS
V
SS
D0–D7
V
DD
/V
DD
Q
D0–D7
D0–D7
V
REF
DQ
SCL WP
SPD
V
DDSPD
ODT0
DQS0
DQS DQS
DQS4
DQS1
DQS
DQS
DQS2
DQS
DQS3
DQS
DQS5
DQS6
DQS
DQS7
DQS
ODT: SDRAMs D0–D7
S0
CK0 CK: SDRAMs D0–D7
SA2
D0–D7
V
REF
CA
A2
CK0CK: SDRAMs D0–D7
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
RESET RESET: SDRAMs D0-D7
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relati o n -
ships must be maintained as shown.
3. DQ,DM,DQS/DQS resistors;Refer to
associated topolo gy diagram.
4. Ref er to the appropriate clock wiring
topology under the DIMM wiring details
section of this document .
5. Ref er to Section 3.1 of this document for
details on address mirroring.
6. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
7. One SPD exists per module.
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2GB, 256Mx64 Module(2Rank of x8)
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 0
I/O 1
I/O 2
I/O 3
D0
DM0
D8
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
D1 D9
I/O 4
I/O 5
I/O 6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
I/O 0
I/O 1
I/O 2
I/O 3
D2 D10
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
I/O 0
I/O 1
I/O 2
I/O 3
D3 D11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
D4
DM4
D12
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
I/O 0
I/O 1
I/O 2
I/O 3
D5 D13
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
D6 D14
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
D7 D15
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM7
A0–A15 A0-A15: SDRAMs D0–D15
A0
Serial PD
A1
SA0 SA1
SDA
RAS RAS: SDRAMs D0–D15
CAS CAS: SDRAMs D0–D15
WE WE: SDRAMs D0–D15
S0 S1
CS
CKE1 CKE: SDRAMs D8–D15
BA0–BA2 BA0–BA2: SDRAMs D0–D15
DQS0
DQS
DQS4
DQS1 DQS5
DQS2
DQS3
DM6
DQS6
DQS7
DQ15 I/O 7 I/O 7
VSS D0–D15
VDD/VDDQD0–D15
D0–D15
VREFDQ
SCL
WP
SPD
VDDSPD
DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQS
DM CS DQS DQSDM CS DQS DQS
DM CS DQS DQS DM CS DQS DQS
DM CS DQS DQS DM CS DQS DQS
DM CS DQS DQS DM CS DQS DQS
DM CS DQS DQS DM CS DQS DQS
DM CS DQS DQS
DQS0DQS4
DQS1 DQS5
DQS2DQS6
DQS3DQS7
ODT0 ODT: SDRAMs D0–D7
ODT1 ODT: SDRAMs D8–D15
CKE0 CKE: SDRAMs D0–D7
CK0 CK: SDRAMs D0–D7
CK0CK: SDRAMs D0–D7
SA2
D0–D15
V
REF
CA
A2
CK1 CK: SDRAMs D8–D15
CK1CK: SDRAMs D8–D15
ZQ ZQ
ZQ
ZQ
ZQ ZQ
ZQ ZQ
ZQ
ZQ
ZQ ZQ
ZQ
ZQ
ZQ ZQ
RESET RESET: SDRAMs D0-D3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-
ships must be maintained as shown.
3. DQ,DM,DQS,DQS resistors;Refer to
associated topology diagram.
4. R efer to Section 3.1 of this document for
details on address mirroring.
5. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
6. One SPD exists per module.
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Absolute Maximum Ratings
Absolute Maximum DC Ratings
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temper atur e Range.
Please refer to the DIMM SPD for option availability
b. Hynix DDR3 SDRAMs support Auto Self-Refresh and Extended Temperature Range and please refer to Hynix
component datasheet and/or the DIMM SPD for tREFI requirement in the Extended Temperature Range.
Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 oC1, 2
Temperature Range
Symbol Parameter Rating Units Notes
TOPER Normal Operating Temperature Range 0 to 85 oC 1,2
Extended Temperature Range 85 to 95 oC1,3
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AC & DC Operating Conditions
Recommended DC Operating Conditions
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC p arameters are measured with VDD and VDDQ tied together.
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specificatio ns” on page 27.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Recommended DC Operating Conditions
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.500 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2
Single Ended AC and DC Input Levels for Command and Address
Symbol Parameter DDR3-800/1066/1333/1600 Unit Notes
Min Max
VIH.CA(DC100) DC input logic high V ref + 0.100 VDD V 1
VIL.CA(DC100) DC input logic low VSS Vref - 0.100 V 1
VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 V 1, 2
VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 V 1, 2
VIH.CA(AC150) AC Input logic high Vref + 0.150 Note2 V 1, 2
VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 V 1, 2
VRefCA(DC)Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4
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AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “DDR3 Device
Operation”) as well as der ating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Notes:
1. Vref = VrefDQ (DC).
2. Refer to “Overshoot and Undershoot Specificatio ns” on page 27.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single Ended AC and DC Input Levels for DQ and DM
Symbol Parameter DDR3-800/1066 DDR3-1333/1600 Unit Notes
Min Max Min Max
VIH.CA(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1
VIL.CA(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1
VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 - - V 1, 2
VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 - - V 1, 2
VIH.CA(AC150) AC Input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 V 1, 2
VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 Note2 Vref - 0.150 V 1, 2
VRefDQ(DC)Reference Voltage for DQ,
DM inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4
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Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page24. Further-
more VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
Illustration of VRef(DC) tolerance and VRef ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are depen-
dent on VRef.
“VRef” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
VDD
VSS
VDD/2
VRef(DC)
VRef ac-noise
voltage
time
VRef(DC)max
VRef(DC)min
VRef(t)
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AC and DC Logic Input Levels for Differential Signals
Differential signal definition
Definition of differential ac-swing and “time above ac-level” tDVAC
time
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
V
IL.DIFF.AC.MAX
V
IL.DIFF.MAX
0
V
IL.DIFF.MIN
V
IL.DIFF.AC.MIN
t
DVAC
half cycle
t
DVAC
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. F or CK - CK use VIH/VIL (ac) of AADD/CM D and VREFCA; for DQ S - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 27.
Differential AC and DC Input Levels
Symbol Parameter DDR3-800, 1066, 1333, & 1600 Unit Notes
Min Max
VIHdiff Differential input high + 0.200 Note 3 V 1
VILdiff Dif ferential input logic low Note 3 - 0.200 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vr ef) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns] tDVAC [ps]
@ |VIH/Ldiff (ac)| = 350mV tDVAC [ps]
@ |VIH/Ldiff (ac)| = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
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Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL hav e to reach VSEHmin / VSELmax (approximately the ac -levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-lev els apply also for the single-
ended signals CK and CK.
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differ ential signals the r equirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
VDD or VDDQ
VSEHmin
VDD/2 or VDDQ/2
VSEH
VSELmax
VSS or VSSQ
CK or DQS
VSEL
time
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Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD /CMD is based on VREFCA; if a reduce d
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 27.
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross poi nt voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol Parameter DDR3-800, 1066, 1333, & 1600 Unit Notes
Min Max
VSEH Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V1,2
Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V1,2
VSEL Single-ended low level for strobes Note 3 (VDD / 2) = 0.175 V1,2
Single-ended low level for CK, CK Note 3 (VDD / 2) = 0.175 V1,2
VDD
VSS
VDD/2
VIX
VIX
VIX
CK, DQS
CK, DQS
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Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the different ial
slew rate of CK - CK is larger than 3 V/ns.
2. Ref er to the table “Single-ended levels f or CK, DQS , DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 20
for VSEL and VSEH standard values.
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-
ended slew rate definition for data signals.
Cross point voltage for differential input signals (CK, DQS)
Symbol Parameter DDR3-800, 1066, 1333, & 1600 Unit Notes
Min Max
VIX Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK -150 150 mV
-175 175 mV 1
VIX Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS -150 150 mV
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Slew Rate Definitions for Differential Input Signals
Input slew r ate for diff erential signals (CK, CK and DQS, DQS) ar e defined and measured as shown in table
and Figure below.
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Differential Input Slew Rate Definition
Description Measured Defined by
Min Max
Diffe rential input slew rate for rising edge
(CK-CK and DQS-DQS)VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
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AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low
swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low
swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
Single-ended AC and DC Output Levels
Symbol Parameter DDR3-800, 1066,
1333 and 1600 Unit Notes
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V1
Differential AC and DC Output Levels
Symbol Parameter DDR3-800, 1066,
1333 and 1600 Unit Notes
VOHdiff (AC) AC differential output high measurement level (for output SR) + 0.2 x VDDQ V1
VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ V1
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Single Ended Output Slew Rate
When the Refer ence load for timing measurement s, output slew rate for f alling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output slew Rate Definition
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Single-ended Output slew Rate Definition
Description Measured Defined by
From To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTF se
Output Slew Rate (single-ended)
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units
Parameter Symbol Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 2.5 52.5 52.5 5TBD 5V/ns
Delta TFse
Delta TRse
vOH(AC)
vOl(AC)
V∏
Single Ended Output Voltage(l.e.DQ)
Single Ended Ou tput S lew R ate D e finition
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Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdif f (AC) for dif ferential signals as shown in table and Figure
below.
Differential Output slew Rate Definition
Differential Output Slew Rate Definition
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC ) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdif f
Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Slew Rate
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units
Parameter Symbol Min Max Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 TBD 10 V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
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Reference Load for AC Timing and Output Slew Rate
Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Reference Load for AC Timing and Output Slew Rate
DUT DQ
DQS
DQS
VDDQ
25 Oh m VTT = VDDQ /2
CK, CK
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Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter DDR3-
800
DDR3-
1066
DDR3-
1333
DDR3-
1600 Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.67 0.5 0.4 0.33 V-ns
Maximum undershoot area below VSS (See Figure below) 0.67 0.5 0.4 0.33 V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDD
VSS
Ma x imu m A mp lit u d e Undershoot Area
Tim e (ns)
Address and Control O vershoot and Undershoot Definition
Volts
(V)
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter DDR3-
800
DDR3-
1066
DDR3-
1333
DDR3-
1600 Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area . (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.25 0.19 0.15 0.13 V-ns
Maximum undershoot area below VSS (See Figure below) 0.25 0.19 0.15 0.13 V-ns
(CK, CK, DQ, DQS, DQS, DM)
See figure below for each parameter definition
Maximum Am plitude
Overshoot Area
VDDQ
VSSQ
Ma x imu m Amp lit u d e Undershoot Area
Tim e (ns)
Clock, Data Strobe and M ask Overshoot and Undershoot Definition
Volts
(V)
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Refresh parameters by device density
Refresh parameters by device density
Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes
REF command ACT or
REF command time tRFC 90 110 160 300 350 ns
Average periodic
refresh interval tREFI 0 C TCASE 85 C7.8 7.8 7.8 7.8 7.8 us
85 C TCASE 95 C3.9 3.9 3.9 3.9 3.9 us
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Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin DDR3-800E Unit Notes
CL - nRCD - nRP 6-6-6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 — ns
PRE command period tRP 15 — ns
ACT to ACT or REF command period tRC 52.5 — ns
ACT to PRE command period tRAS 37.5 9 * tREFI ns
CL = 5 CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3
Supported CL Settings 6nCK
Supported CWL Settings 5nCK
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DDR3-1066 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin DDR3-1066F Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to
first data
t
AA 13.125 20 ns
ACT to internal read or
write delay time
t
RCD 13.125 — ns
PRE command period
t
RP 13.125 — ns
ACT to ACT or REF
command period
t
RC 50.625 — ns
ACT to PRE command
period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) Reserved ns 1, 2, 3, 4, 5
CWL = 6
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 5
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 7 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4
CL = 8 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3
Supported CL Settings 6, 7, 8
n
CK
Supported CWL Settings 5, 6
n
CK
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DDR3-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin DDR3-1333H Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read command
to first data
t
AA 13.5
(13.125)8 20 ns
ACT to internal read or
write delay time
t
RCD 13.5
(13.125)8 —ns
PRE command period
t
RP 13.5
(13.125)8 —ns
ACT to ACT or REF
command period
t
RC 49.5
(49.125)8 —ns
ACT to PRE command
period
t
RAS 36 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) Reserved ns 1,2, 3,4, 6
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 6
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 6
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 6
Reserved
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 6
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 9 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3
Reserved ns
Supported CL Settings 6, 8, (7), 9, (10)
n
CK
Supported CWL Settings 5, 6, 7
n
CK
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DDR3-1600 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 34.
Speed Bin DDR3-1600K Unit Note
CL - nRCD - nRP 11-11-11
Parameter Symbol min max
Internal read command
to first data
t
AA 13.75
(13.125)8 20 ns
ACT to internal read or
write delay time
t
RCD 13.75
(13.125)8 —ns
PRE command period
t
RP 13.75
(13.125)8 —ns
ACT to ACT or REF
command period
t
RC 48.75
(48.125)8 —ns
ACT to PRE command
period
t
RAS 35 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 7
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 7
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 8
t
CK(AVG) Reserved ns 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 7
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 9
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 4, 7
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 7
CWL = 8
t
CK(AVG) Reserved ns 1,2,3,4
CL = 11 CWL = 5, 6,7
t
CK(AVG) Reserved ns 4
CWL = 8
t
CK(AVG) 1.25 <1.5 ns 1, 2, 3
Supported CL Settings 6, (7), 8, (9), 10, 11
n
CK
Supported CWL Settings 5, 6, 7, 8
n
CK
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Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(A VG).MAX requirements. When making
a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements
from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - dat a and str o be output ar e synchro niz ed
by the DLL - all possib le intermediate frequencies may not be guaranteed. An application should use the
next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] =
tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’.
3. tCK(A VG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX
corresponding to CLSE LECTED.
4. ‘Reserved’ settings are not allowed. User must program a different va lue.
5. Any DDR3-1066 speed bin also supports functional oper ation at lower frequen cies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
6. Any DDR3-1333 speed bin also supports functional oper ation at lower frequen cies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1600 speed bin also supports f unctional oper ation at lower f requencies as shown in the table
which are not subject to Production Tests but verified by Design/Characterization.
8. Hynix DDR3 SDRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini-
mum value of 13.125ns. SPD settings are also programmed to match. For example, DDR3 1333H devices
supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16),
tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning t o DDR3-1333H
or DDR3 1600F should progr am 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRP-
min (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be pro-
grammed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H
and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
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Environmental Parameters
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating
only, and device functional operation at or above the conditions indicated is not implied. Expousure to
absolute maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The component maximum case Temperature (TCASE) shall not exceed the value specified in the DDR3
DRAM component specification.
Symbol Parameter Rating Units Notes
TOPR Operating temperature (ambient) 0 to +55 oC3
HOPR Operating humidity (relative) 10 to 90 %
TSTG Storage temperature -50 to +100 oC1
HSTG Storage humidity (without condensation) 5 to 95 % 1
PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2
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Pin Capacitance (VDD=1.5V, VDDQ=1.5V)
1GB: HMT112U6DFR8C
2GB: HMT125U6DFR8C
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
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IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measur ement condit ions such as test load and patterns are defined. F igur e
below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup
and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied togeth er. Any IDD curr ent is not included in IDDQ cur-
rents.
Attention: IDDQ va lues cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in the Figure
below (Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement). In DRAM module application, IDDQ cannot be measured separately since VDD and
VDDQ are using on merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= VILAC(max).
• ”1” and “HIGH” is defined as VIN >= VIHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
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Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
VDD
DDR3
SDRAM
VDDQ
RESET
CK/CK
DQS, DQS
CS
RAS, CAS, WE
A, BA
ODT
ZQ VSS VSSQ
DQ, DM,
TDQS, TDQS
CKE RTT = 25 OhmVDDQ/2
IDD IDDQ (optional)
Application specific
memory channel
environment
Channel
IO Power
Simulation IDDQ
Simulation
IDDQ
Simulation
Channel IO Power
Number
IDDQ
Test Load
Correction
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol DDR3-1066 DDR3-1333 DDR3-1600 Unit
7-7-7 9-9-9 11-11-11
t
CK 1.875 1.5 1.25 ns
CL 7 9 11 nCK
n
RCD 7911nCK
n
RC 27 33 39 nCK
n
RAS 20 24 28 nCK
n
RP 7911nCK
n
FAW 1KB page size 20 20 24 nCK
2KB page size 27 30 32 nCK
n
RRD 1KB page size 4 4 5 nCK
2KB page size 6 5 6 nCK
n
RFC -512Mb 48 60 72 nCK
n
RFC-1 Gb 59 74 88 nCK
n
RFC- 2 Gb 86 107 128 nCK
n
RFC- 4 Gb 160 200 240 nCK
n
RFC- 8 Gb 187 234 280 nCK
Symbol Description
I
DD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
I
DD1
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active a t a time: 0,0,1,1,2,2,... (see Table 4); Output Buff er and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
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I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exitc)
I
DD2P1
Precharge Power-Down C u rrent Fast Exi t
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and R T T: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Po wer Down Mode: Fast Exitc)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: st able at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Outp ut Buffer and RTT: Enabled in Mode Registersb); ODT S ignal: stable at 0; Pattern Details: see
Table 5.
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID _LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Symbol Description
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I
DD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: s table at 0 ; Bank Activity: all banks ope n,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
I
DD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: s table at 0 ; Bank Activity: all banks ope n,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
I
DD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
I
DD6
Self-Refresh Current: Normal Temperature Range
T
CASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD6ET
Self-Refresh Current: Extended Temperature Range
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
CKE: Low; External clock: Off; CK and CK: LOW ; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD6TC
Auto Self-Refresh Current
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Symbol Description
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a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; R TT_Nom enable: set MR1 A[9,6 ,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature
range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
I
DD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
Symbol Description
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Table 3 - IDD0 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1111000000 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3, 4 D, D 1111000000 F 0 -
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
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Table 4 - IDD1 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT001100000000 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3,4 D, D 1111000000F0 -
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
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Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D1111 000 0 0 F0 -
3D
1111 000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D1111000 0 0 F0 -
3D
1111000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
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Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
a) DM must be driven LOW all the ti me. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
a) DM must be driven LOW all the ti me. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1D100000000000-
2,3 D,D 111100000 0 00 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5D1000000000F0-
6,7 D,D 111100000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1D100010000000-
2,3 D,D 111110000 0 00 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5D1000100000F0-
6,7 D,D 111110000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
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Table 9 - IDD5B Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00REF 0 0 0 1 0 0 0 0 0 0 0 -
11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 111100000 0 F0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
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Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
22*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
33*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
44*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
Assert and repeat above D Command until nFAW - 1, if necessary
5nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
9nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Assert and repeat above D Command until 2* nFAW - 1, if necessary
10
2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
2&nFAW+2 D 1 0 0 0 0 0 00 0 0 F 0 -
Repeat above D Command until 2* nFAW + nRRD - 1
11
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
2&nFAW+nRRD+2 D 1 0 0 0 0 1 00 0 0 0 0 -
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 0 0 0 0 -
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 0 0 -
Assert and repeat above D Command until 4* nFAW - 1, if necessary
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IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
1GB, 128M x 64 U-DIMM: HMT112U6DFR8C
1GB, 128M x 72 U-DIMM: HMT125U6DFR8C
Symbol DDR3 1066 DDR3 1333 Unit note
IDD0 TBD TBD mA
IDD1 TBD TBD mA
IDD2N TBD TBD mA
IDD2NT TBD TBD mA
IDD2P0 TBD TBD mA
IDD2P1 TBD TBD mA
IDD2Q TBD TBD mA
IDD3N TBD TBD mA
IDD3P TBD TBD mA
IDD4R TBD TBD mA
IDD4W TBD TBD mA
IDD5B TBD TBD mA
IDD6 TBD TBD mA
IDD6ET TBD TBD mA
IDD6TC TBD TBD mA
IDD7 TBD TBD mA
Symbol DDR3 1066 DDR3 1333 Unit note
IDD0 TBD TBD mA
IDD1 TBD TBD mA
IDD2N TBD TBD mA
IDD2NT TBD TBD mA
IDD2P0 TBD TBD mA
IDD2P1 TBD TBD mA
IDD2Q TBD TBD mA
IDD3N TBD TBD mA
IDD3P TBD TBD mA
IDD4R TBD TBD mA
IDD4W TBD TBD mA
IDD5B TBD TBD mA
IDD6 TBD TBD mA
IDD6ET TBD TBD mA
IDD6TC TBD TBD mA
IDD7 TBD TBD mA
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Module Dimensions
128Mx64 - HMT112U6DFR8C
9.50
17.30
Max R0.70
2
x
2.50 0.10
Min 1.45
DETAIL-A DETAIL-B
2.10 0.15
4
x
3.00 0.10
2
x
2.30 0.10
5.175 47.00 71.00
128.95
133.35
0.35
1.00
0.3~1.0
Detail - B
5.00
3.80
0.05
2.50 0.20
0.80 0.05
0.3 0.15
1.50 0.10
2.50 FULL R
Detail - A
1.27
±
0.10
3.18
Back
Side
30.00
Front
SPD
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13
Units: millimeters
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256Mx64 - HMT125U6DFR8C
9.50
17.30
Max R0.70
2
x
2.50 0.10
Min 1.45
DETAIL-A DETAIL-B
2.10 0.15
4
x
3.00 0.10
2
x
2.30 0.10
5.175 47.00 71.00
128.95
133.35
0.35
1.00
0.3~1.0
Detail - B
5.00
3.80
0.05
2.50 0.20
0.80 0.05
0.3 0.15
1.50 0.10
2.50 FULL R
Detail - A
1.27
±
0.10
4.00
Back
Side
30.00
Front
SPD
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13
Units: millimeters
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