© Semiconductor Components Industries, LLC, 2015
October, 2017 − Rev. 5
1Publication Order Number:
ESD8008/D
ESD8008
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8008 is designed specifically to protect four high speed
differential pairs. Ultra−low capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines. The flow−through style package
allows for easy PCB layout and matched trace lengths necessary to
maintain consistent impedance for the high speed lines.
Features
•Integrated 4 Pairs (8 Lines) High Speed Data
•Single Connect, Flow through Routing
•Low Capacitance (0.35 pF Max, I/O to GND)
•Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (ESD) ±15 kV (Contact)
IEC 61000−4−5 (Lightning) 5 A (8/20 ms)
•UL Flammability Rating of 94 V−0
•SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•V−by−One HS
•LVDS
•Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ−55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Maximum Peak Pulse Current
8/20 ms @ TA = 25°C (I/O−GND)
IPP 5.0 A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN14
CASE 517CN
www.onsemi.com
ESD8008MUTAG UDFN14
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
8008 = Specific Device Code
M = Date Code
G= Pb−Free Package
8008M
G
1
14
SZESD8008MUTAG UDFN14
(Pb−Free)
3000 / Tape &
Reel
ESD8008
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2
I/O
Figure 1. Pin Schematic
Figure 2. Pin Configuration
Note: Only minimum of one pin needs to be connected to
ground for functionality of all pins.
I/O
Pin 1
I/O
Pin 2
I/O
Pin 4
I/O
Pin 5
I/O
Pin 7
I/O
Pin 8
I/O
Pin 10
I/O
Pin 11
Center Pins, Pin 3, 6, 9, 12, 13, 14
Note: Common GND − Only Minimum of 1 GND connection required
GND
GND
GND
I/O
GND
I/O
I/O
GND
I/O
I/O
GND
I/O
I/O
=
1
2
3
4
5
6
7
8
9
10
11
14
13
12
ESD8008
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3
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
VRWM Working Peak Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
VHOLD Holding Reverse Voltage
IHOLD Holding Reverse Current
RDYN Dynamic Resistance
IPP Maximum Peak Pulse Current
VCClamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
I
V
VCVRWM
VHOLD
VBR
RDYN
VC
IR
IT
IHOLD
−IPP
RDYN
IPP
VC = VHOLD + (IPP * RDYN)
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 3.3 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 7.0 8.5 V
Reverse Leakage Current IRVRWM = 3.3 V, I/O Pin to GND 0.5 mA
Holding Reverse Voltage VHOLD I/O Pin to GND 1.19 V
Holding Reverse Current IHOLD I/O Pin to GND 25 mA
Clamping Voltage (Note 1) VCIEC61000−4−2, ±8 KV Contact See Figures 3 and 4 V
Clamping Voltage VCIPP = 1 A, Any I/O to GND (8/20 ms pulse) 1.5 V
Clamping Voltage VCIPP = 5 A, Any I/O to GND (8/20 ms pulse) 5.0 V
Clamping Voltage
TLP (Note 2)
See Figures 7 through 10
VCIPP = 8 A
IPP = −8 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
4.6
−5.1
V
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.1
−10.3
Dynamic Resistance RDYN I/O Pin to GND
GND to I/O Pin
0.43
0.50
W
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 2.5 GHz between I/O Pins and GND
VR = 0 V, f = 5.0 GHz between I/O Pins and GND
VR = 0 V, f = 1 MHz, between I/O Pins
0.30
0.20
0.20
0.10
0.35
0.16
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−20 0 20 40 60 80 100 140120
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
Figure 4. IEC61000−4−2 −8 kV Contact
Clamping Voltage
−20 0 20 40 60 80 100 140120
90
TIME (ns) TIME (ns)
VOLTAGE (V)
VOLTAGE (V)
80
70
60
50
40
30
20
10
0
−10
ESD8008
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4
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Figure 6. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD8008
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5
Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve
TLP CURRENT (A)
VC, VOLTAGE (V)
EQUIVALENT VIEC (kV)
20
18
16
14
12
10
8
6
4
2
00
8
6
4
2
0201816142468 1210
TLP CURRENT (A)
VC, VOLTAGE (V)
EQUIVALENT VIEC (kV)
−20
0
8
6
4
2
0201816142468 1210
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
VC = VHOLD + (IPP * RDYN)
10 10
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
Figure 9. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD8008
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6
Figure 11. IEC61000−4−5 8/20 ms Pulse
Waveform
TIME (ms)
50
0
Ipp - PEAK PULSE CURRENT - %Ipp
100
tr = rise time to peak value [8 ms]
tf = decay time to half value [20 ms]
trtf
Peak
Value
Half Value
0
Figure 12. Clamping Voltage vs. Peak Pulse Current
(tp = 8/20 ms per Figure 11)
8
7
6
5
4
3
2
1
0087651234
Ipk (A)
Vpk (V)
I/O−GND
Figure 13. Junction Capacitance; VR = 0, f = 500 MHz − 10 GHz
Interface
Data Rate
(Gbps)
Fundamental
Frequency (GHz)
3rd Harmonic
Frequency (GHz)
ESD8008 Insertion
Loss (−dB)
V−by−One HS
Full HD (1920 x 1080p)
240 Hz, 36bit color depth
3.71 1.854 (m1) 5.562 (m3) m1 = 0.146
m3 = 0.451
Figure 14. ESD8008 Insertion Loss
ESD8008
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7
Figure 15. V−by−One HS Layout Diagram (for LCD Panel)
ESD8008
ESD8008
Rx0p
Rx0n
Rx1p
Rx1n
Rx2p
Rx2n
Rx3p
Rx3n
Rx4p
Rx4n
Rx5p
Rx5n
Rx6p
Rx6n
Rx7p
Rx7n
TCON Board
Connector
Timing Controller
PCB Layout Guidelines
Steps must be taken for proper placement and signal trace
routing of the ESD protection device in order to ensure the
maximum ESD survivability and signal integrity for the
application. Such steps are listed below.
•Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground and
improve the protection performance.
•Make sure to use differential design methodology and
impedance matching of all high speed signal traces.
♦Use curved traces when possible to avoid unwanted
reflections.
♦Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦Place grounds between high speed pairs and keep as
much distance between pairs as possible to reduce
crosstalk.
ESD8008
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8
Latch-Up Considerations
ON Semiconductor’s 8000 series of ESD protection
devices utilize a snap-back, SCR type structure. By using
this technology, the potential for a latch-up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch-up free applications and applications with the potential
for latch-up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch-up free load line case, the IV
characteristic of the snapback protection device intersects
the load-line in one unique point (VOP
, IOP). This is the only
stable operating point of the circuit and the system is
therefore latch-up free. In the non-latch up free load line
case, the IV characteristic of the snapback protection device
intersects the load-line in two points (VOPA, IOPA) and
(VOPB, IOPB). Therefore in this case, the potential for
latch-up exists if the system settles at (VOPB, IOPB) after a
transient. Because of this, ESD8008 should not be used for
HDMI applications – ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch-up. Please refer to Application Note AND9116/D for
a more in-depth explanation of latch-up considerations
using ESD8000 series devices.
Figure 16. Example Load Lines for Latch-up Free Applications and Applications with the Potential for Latch-up
I
V
VDD
ISSMAX
IOP
VOP
I
V
VDD
ISSMAX
IOPA
VOPA
IOPB
VOPB
ESD8008 Latch−up free:
V−by−One HS, DisplayPort, LVDS
ESD8008 Potential Latch−up:
HDMI 1.4/1.3a TMDS
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH-UP FREE APPLICATIONS
Application
VBR (min)
(V)
IH (min)
(mA)
VH (min)
(V)
ON Semiconductor ESD8000 Series
Recommended PN
HDMI 1.4/1.3a TMDS 3.465 54.78 1.0 ESD8104, ESD8040
DisplayPort 3.600 25.00 1.0 ESD8004, ESD8006, ESD8008
V−by−One HS 1.980 21.70 1.0 ESD8008
LVDS 1.829 9.20 1.0 ESD8008
ESD8008
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9
PACKAGE DIMENSIONS
ÉÉ
ÉÉ
UDFN14, 5.5x1.5, 0.5P
CASE 517CN
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b0.15 0.25
D5.50 BSC
D2 0.45 0.55
E1.50 BSC
e0.50 BSC
L0.20 0.40
0.10 C
D
E
B
A
2X
2X
NOTE 4
A
A1
(A3)
0.10 C
PIN ONE
REFERENCE
0.10 C
0.05 C
CSEATING
PLANE
BOTTOM VIEW
b
14X
0.10 B
0.05
AC
C
L
SIDE VIEW
TOP VIEW
NOTE 3
111
1412
3X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DETAIL C
L1 0.00 0.05
DIMENSION: MILLIMETERS
RECOMMENDED
L1
DETAIL A
L
OPTIONAL
CONSTRUCTION
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
0.62
1.80
0.50
PITCH
PACKAGE
0.26
14X
E2 0.50 0.70
e
M
M
E2
0.10
DETAIL C
14X
0.50
DETAIL A
D2
REF
6X
0.43
OUTLINE 0.56
3X
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ESD8008/D
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