LDS8710
© 2010 IXYS Corp. 7Doc. No. 8710DS, Rev. N1.0
Characteristics subject to change without notice
External Components Selection
The LDS8710 requires four external components
only. The recommended input capacitor value is
between 1.0 and 10 µF, while the output cap
selection is function of desired output ripple, loop
stability, and inrush current. We recommend COUT =
1 µF.
The inductor should allow around 20% higher peak
current than LDS8710 Switch Current Limit ILIM (see
table Electrical Operating Characteristics on page 2).
However, the maximum ripple current through
inductor IRshould not exceed
IN
dFLED
LIMR V
VNVI
II 2, where
VF- is a LED forward voltage, V
N – is number of LEDs per string
Vd - is a current regulator voltage drop = 0.25 V,
VIN - is an input voltage, V
We recommend continuous conduction mode for
inductor to achieve highest efficiency. That limits IR
value as
IN
dFLED
RVVNVI
I
2
Inductor value L is a function of switching frequency,
input and output voltage and is determined by
following equation:
ININPMdF
RVVVVNV
fI
L11
1, where
VPM - is a voltage drop across synchronous rectifier
(PMOSFET) = 1.5 ohms x ILED, (A),
L - is an inductance, H, and
f - is a switching frequency, 700 kHz.
Inductor should have minimum DC resistance to
avoid driver’s efficiency degradation.
The equation for the output capacitor selection is:
fVVNV
IVVNV
C
RdF
OUTINdF
OUT )(
)(
, where
VR– is a ripple voltage at the output.
For example:
If VIN = 2.7 V, N = 10, VF= 3.6 V, Vd = 0.25 V, f =
0.7 MHz, IOUT = 30 mA, and ripple voltage VR= 0.05
V, COUT = 0.77 µF so 1 µF is a good choice.
We recommend COUT = 1 µF to achieve better
efficiency and driver’s stability.
Recommended Layout
In active mode, the driver switches internally at a high
frequency. We recommend minimize trace length to
all external capacitors and inductor. The input and
output ceramic capacitors (X5R or X7R type) should
located as close to the device’ pins as possible to
prevent from EMI distribution
A ground plane should cover the area under the
driver IC as well as the bypass capacitors. Short
connection to ground on capacitors CIN and COUT can
be implemented with the use of multiple via. A copper
area matching the TDFN exposed pad (PAD) must
be connected to the ground plane underneath. The
use of multiple via improves the package heat
dissipation.
Figure 3. Recommended layout
.