SCAN921821
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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed
BIST
Check for Samples: SCAN921821
1FEATURES DESCRIPTION
The SCAN921821 is a dual channel 18-bit serializer
2• 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps featuring signal conditioning, boundary SCAN, and at-
Total Throughput speed BIST. Each serializer block transforms an 18-
• 8-level Selectable Pre-emphasis on Each bit parallel LVCMOS/LVTTL data bus into a single
Channel Drives Lossy Cables and Backplanes Bus LVDS data stream with embedded clock. This
single serial data stream with embedded clock
• >15kV HBM ESD Protection on Bus LVDS I/O simplifies PCB design and reduces PCB cost by
Pins narrowing data paths that in turn reduce PCB size
• Robust BLVDS Serial Data Transmission with and layers. The single serial data stream also
Embedded Clock for Exceptional Noise reduces cable size, the number of connectors, and
Immunity and Low EMI eliminates clock-to-data and data-to-data skew.
• Power Saving Control Pin for Each Channel Each channel also has an 8-level selectable pre-
• IEEE 1149.1 "JTAG" Compliant emphasis feature that significantly extends
performance over lossy interconnect. Each channel
• At-Speed BIST - PRBS Generation also has its own powerdown pin that saves power by
• No External Coding Required reducing supply current when the channel is not
• Internal PLL, No External PLL Components being used.
Required The SCAN921821 also incorporates advanced
• Single +3.3V Power Supply testability features including IEEE 1149.1 and at-
• Low Power: 260 mW (typ) Per Channel at 66 speed BIST PRBS pattern generation to facilitate
MHz with PRBS-15 Pattern verification of board and link integrity
• Single 3.3 V Supply
• Fabricated with Advanced CMOS Process
Technology
• Industrial −40 to +85°C Temperature Range
• Compact 100-ball NFBGA Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Parallel to Serial
Input Latch
Parallel to Serial
Input Latch
PLL Timing
and
Control
IEEE 1149.1
Test Access Port
DINA
DINB
DOUTAP
DOUTAN
DOUTBP
DOUTBN
TDI
TDO
TMS
TCK
BIST
18
18
PWDNA
SYNCA
TxCLK
PWDNB
SYNCB
TRST
3
3
PEMB
PEMA
BISTA
BISTB
ENA
ENB
SCAN921821
SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
www.ti.com
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage (VDD)−0.3V to +4V
Supply Voltage (VDD) Ramp Rate < 30 V/ms
LVCMOS/LVTTL Input Voltage −0.3V to (VDD +0.3V)
LVCMOS/LVTTL Output Voltage −0.3V to (VDD +0.3V)
Bus LVDS Driver Output Voltage −0.3V to +3.9V
Bus LVDS Output Short Circuit Duration 10ms
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 4 seconds) +220°C
Maximum Package Power Dissipation at 25°C NFBGA-100 3.57 W
Derating Above 25°C 28.57 mW/°C
Thermal resistance θJA 35°C/W
θJC 11.1°C/W
ESD Rating HBM, 1.5 KΩ, 100 pF All pins >8 kV
Bus LVDS pins >15 kV
MM, 0Ω, 200 pF >1200 V
CDM >2 kV
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
Recommended Operating Conditions Min Nom Max Units
Supply Voltage (VDD) 3.15 3.3 3.45 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
Clock Rate 15 66 MHz
Supply Noise 100 mV p-p
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL Input DC Specifications
High Level Input
VIH 2.0 VDD V
Voltage
Low Level Input
VIL GND 0.8 V
Voltage
VCL Input Clamp Voltage ICL =−18 mA −1.5 -0.7 V
High Level Input
IINH VIN = VDD = VDDMAX −20 ±2 +20 μA
Current
Low Level Output
IINL VIN = VSS, VDD = VDDMAX −10 ±2 +10 μA
Current
1149.1 (JTAG) DC Specifications
High Level Input
VIH 2.0 VDD V
Voltage
Low Level Input
VIL GND 0.8 V
Voltage
VCL Input Clamp Voltage ICL =−18 mA −1.5 -0.7 V
High Level Input
IINH VIN = VDD = VDDMAX -20 +20 μA
Current
Low Level Output
IINL VIN = VSS, VDD = VDDMAX -200 +200 μA
Current
High Level Output
VOH IOH =−9 mA 2.3 VDD mV
Voltage
Low Level Output
VOL IOL = 9 mA GND 0.5 mV
Voltage
Output Short Circuit
IOS VOUT = 0 V -100 -80 -50 mA
Current PWDN or EN = 0.8V, VOUT = 0 V -10 +10 μA
Output Tri-state
IOZ Current PWDN or EN = 0.8V, VOUT = VDD -30 +30 μA
Bus LVDS Output DC Specifications
Output Differential
VOD See Figure 10, RL= 100Ω450 500 550 mV
Voltage (DO+) - (DO-)
Output Differential
ΔVOD 2 15 mV
Voltage Unbalance
VOS Offset Voltage 1.05 1.2 1.25 V
Offset Voltage
ΔVOS 2.7 15 mV
Unbalance
(1) Typical values are given for VCC = 3.3V and TA= +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol Parameter Conditions Min Typ Max Units
Pre-Emphasis Level = 1 1.10 1.24 1.35
Pre-Emphasis Level = 2 1.35 1.47 1.55
Pre-Emphasis Level = 3 1.55 1.70 1.80
Pre-Emphasis Output
QPOV Voltage Ratio Pre-Emphasis Level = 4 1.80 1.91 1.95
| VODPRE / VOD |Pre-Emphasis Level = 5 1.95 2.08 2.20
Pre-Emphasis Level = 6 2.10 2.21 2.35
Pre-Emphasis Level = 7 2.15 2.30 2.50
Output Short Circuit
IOS DO = 0V, Din = H, PWDN and EN = 2.4V -10 -25 -75 mA
Current PWDN or EN = 0.8V, DO = 0V (3) -10 ± 1 +10 µA
TRI-STATE Output
IOZ Current PWDN or EN = 0.8V, DO = VDD (3) -55 ± 6 +55 µA
Power Supply Current (DVDD, PVDD and AVDD Pins)
f = 66 MHz, PRBS-15 160 225 mA
Pattern
Total Supply Current CL= 15pF,
IDD f = 66 MHz, Worst Case
(includes load current) RL= 100 ΩPattern (Checker-Board 180 mA
Pattern)
f = 66 MHz, PRBS-15 240 mA
Pattern
Total Supply Current CL= 15pF,
IDDP with Pre-Emphasis f = 66 MHz, Worst Case
RL= 100 Ω
(includes load current) Pattern (Checker-Board 280 325 mA
Pattern)
Supply Current
IDDX PWDN = 0.8V, EN = 0.8V 1.0 3.0 mA
Powerdown
(3) IOZ is measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow.
Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol Parameter Conditions Min Typ Max Units
tTCP Transmit Clock Period 15.2 T 66.7 ns
Transmit Clock High
tTCIH 0.4T 0.5T 0.6T ns
Time
Transmit Clock Low
tTCIL 0.4T 0.5T 0.6T ns
Time
TCLK Input Transition
tCLKT 3 6 ns
Time
tJIT TCLK Input Jitter See (3) 80 ps (RMS)
(1) Typical values are given for VCC = 3.3V and TA= +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Specified by design using statistical analysis.
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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Symbol Parameter Conditions Min Typ Max Units
Serializer AC Specifications
Bus LVDS Low-to-High
tLLHT 0.3 0.4 ns
See Figure 2,(3)
Transition Time RL= 100Ω,
Bus LVDS High-to-Low CL=10pF to GND
tLHLT 0.3 0.4 ns
Transition Time
DIN (0-17) Setup to
tDIS 1.9 ns
See Figure 4,(3)
TCLK RL= 100Ω,
DIN (0-17) Hold from CL=10pF to GND
tDIH 0.6 ns
TCLK
DO ± HIGH to
tHZD 3.9 10 ns
TRI-STATE Delay
DO ± LOW to TRI-
tLZD 3.5 10 ns
See Figure 5
STATE Delay RL= 100Ω,
DO ± TRI-STATE to CL=10pF to GND
tZHD 3.2 10 ns
HIGH Delay
DO ± TRI-STATE to
tZLD 2.4 10 ns
LOW Delay See Figure 7,
tSPW SYNC Pulse Width 5*tTCP 6*tTCP ns
RL= 100Ω
Serializer PLL Lock See Figure 6,
tPLD 510*tTCP 1024*tTCP ns
Time RL= 100Ω
tSD Serializer Delay See Figure 8 , RL= 100ΩtTCP + 2.5 tTCP + 4.5 tTCP + 6.5 ns
Channel to Channel
tSKCC 70 ps
Skew Room Temperature, VDD = 3.3V, ps
tRJIT Random Jitter 6.1
66 MHz (RMS)
15 MHz -390 320 ps
Deterministic Jitter
tDJIT Figure 9,(3) 66 MHz -60 30 ps
1149.1 (JTAG) AC Specifications
Maximum TCK Clock
fMAX 25 MHz
Frequency
TDI or TMS Setup to
tS2.4 ns
TCK, H or L
TDI or TMS Hold from
tH2.8 ns
CL= 15pF,
TCK, H or L RL= 500 Ω
TCK Pulse Width, H or
tW1 10 ns
L
tW2 TRST Pulse Width, L 10 ns
Recovery Time, TRST
tREC 2 ns
to TCK
(1) Typical values are given for VCC = 3.3V and TA= +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Specified by design using statistical analysis.
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AC Timing Diagrams and Test Circuits
Figure 1. “Worst Case” Serializer IDD Test Pattern
Figure 2. Serializer Bus LVDS Distributed Output Load and Transition Times
Figure 3. Serializer Input Clock Transition Time
Figure 4. Serializer Setup/Hold Times
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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
Figure 9. Deterministic Jitter and Ideal Bit Position
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
Figure 10. VOD Diagram
Pre-emphasis Truth Table
PEM LEVEL PEM2 PEM1 PEM0
0LLL
1 L L H
2 L H L
3 L H H
4 H L L
5 H L H
6 H H L
7 H H H
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A1
BISTB
A2 A3 A4 A5 A6 A7 A8
PVSS DOUTBN AVDD ENB AVDD
A9 A10
DOUTAN DOUTAP
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
DINB16 AVDD DOUTBP AVDD PEMB1 AVSS PEMB0
C1
DINB14
C2 C3 C4 C5 C6 C7 C8
DVDD DVSS
PVDD
DVDD PEMA0
AVDD PEMA2
C9 C10
PEMA1
AVDD
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
DINB12
DINB15 DVSS
AVSS
DVSS
DINA17 DINA13
BISTA
ENA
E1
DINB11
E2 E3 E4 E5 E6 E7 E8
DINB9
DINB5 PVDD DINA11
DINA14 DINA12 DINA9
E9 E10
SYNCA DINA16
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
DINB10 DINB7
DINB2
DVSS DINA4 DINA10 DINA8
DINA0 DINA5
G1 G2 G3 G4 G5 G6 G7 G8
DINB4 DINA2
DVDD
DVSS DVDD DINA1 DINA7
G9 G10
DINA3
DVDD
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
DINB0 DVDD TRST PVDD PVSS PVDD NC
H1 H2 H3 H4 H5 H6 H7 H8
DINB1 TxCLK TCK
DVSS PVDD PVSS DVSS
H9 H10
DVDD
PWDNB
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
DVSS TMS DVSS TDO DVDD PVSS PVSS
DINB13
DINB6
DINB3
SYNCB
TDI
PWDNA
DINA6
DINA15
AVSS AVSS
DINB17 AVSS
DINB8 PEMB2 DVSS
SCAN921821
SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
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Pin Diagram
Figure 11. SCAN921821TVV
Top View
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SNLS173C –SEPTEMBER 2004–REVISED APRIL 2013
Pin Descriptions
Pin Name Pin Count I/O, Type Description
DATA PINS
DINA0-17 18 Transmitter inputs. There is a pull-down circuitry on each of these pins which are active
I, LVCMOS if respective PWDNA or PWDNB pin is pulled high.
DINB0-17 18
DOUTAP 1
DOUTAN 1 O,BLVDS Inverting and non-inverting differential transmitter outputs.
DOUTBP 1
DOUTAN 1
TIMING AND CONTROL PINS
Transmitter reference clock. Used to strobe data at the inputs and to drive the
TxCLK 1 I, LVCMOS transmitter PLL. There is a pull-up circuitry on this pin which is always active.
ENA 1 Transmitter outputs enable pins. There is a pull-down circuitry on each of these pins that
I, LVCMOS are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are
ENB 1 set to LOW, the transmitter outputs will be disabled. The PLL will remain locked.
PWDNA 1 Stand-by mode pins. There is a pull-down circuitry on each of these pins that are always
I, LVCMOS active. When these pins are set to LOW, the transmitter will be put in low power mode
PWDNB 1 and the PLL will lose lock.
SYNCA 1 Transmitter synchronization pins. There is a pull-down circuitry on each of these pins
that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins
I, LVCMOS are set to HIGH, the transmitter will ignore incoming data and send SYNC patterns to
SYNCB 1 provide a locking reference to receiver(s).
PRE-EMPHASIS PINS
PEMA0-2 3 8-level pre-emphasis selection pins. There is a pull-down circuitry on each of these pins
I, LVCMOS which are active if corresponding PWDNA or PWDNB pin is pulled high.
PEMB0-2 3
JTAG PINS
Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is
TDI 1 I, LVCMOS always active.
TDO 1 O, LVCMOS Test Data Output to support IEEE 1149.1.
Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on this pin
TMS 1 I, LVCMOS which is always active.
TCK 1 I, LVCMOS Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin.
Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is
TRST 1 I, LVCMOS always active.
BIST PINS
BISTA 1 BIST selection pins. These pins select which transmitter will generate a PRBS like data.
I, LVCMOS There is a pull-down circuitry on these pins which are active if corresponding PWDNA or
BISTB 1 PWDNB pin is pulled high.
POWER PINS
AVDD 6 I, POWER Power Supply for the LVDS circuitry.
DVDD 8 I, POWER Power Supply for the digital circuitry.
PVDD 5 I, POWER Power Supply for the PLL and BG circuitry.
AVSS 5 I, POWER Ground reference for the LVDS circuitry.
DVSS 10 I, POWER Ground reference for the digital circuitry.
PVSS 5 I, POWER Ground reference for the PLL and BG circuitry.
OTHER PINS
NC 1 N/A Not connected.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SCAN921821TSM/NOPB ACTIVE NFBGA NZD 100 240 Green (RoHS
& no Sb/Br) SNAGCU Level-4-260C-72 HR -40 to 85 SCAN921821
TSM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Nov-2013
Addendum-Page 2
MECHANICAL DATA
NZD0100A
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