1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
SEPTEMBER 2001
2001 Integrated Device Technology, Inc. DSC 5963/3c
IDT5V991A
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V991A-2: tSKEW0<250ps
IDT5V991A-5: tSKEW0<500ps
IDT5V991A-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in 32-pin PLCC Package
DESCRIPTION:
The IDT5V991A is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When VCCQ/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
GND/sOE
1Q0
Skew
Select
1Q1
1F1:0
33
2Q0
Skew
Select
2Q1
2F1:0
FS
3
REF
PLL
FB
3
3Q0
Skew
Select
3Q1
3F1:0
33
4Q0
4Q1
Skew
Select
4F1:0
33
3
VCCQ/PE
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F1
4F0
4F1
VCCQ/PE
4Q1
4Q0
GND
GND
2F0
GND/sOE
1F1
1F0
1Q0
1Q1
GND
GND
4 3 2 1 32 31 30
14 15 16 17 18 19 20
3F
0
FS
REF
GND
TEST
2F
1
3Q
1
3Q
0
FB
2Q
1
2Q
0
VCCN
V
CCN
V
CCN
V
CCQ
VCCN
PLCC
TOP VIEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
PROGRAMMABLE SKEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max Unit
Supply Voltage to Ground –0.5 to +7 V
VIDC Input Voltage –0.5 to VCC+0.5 V
REF Input Voltage –0.5 to +5.5 V
TJJunction Temperature 1 5 0 °C
TSTG Storage Temperature –65 to +150 °C
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Typ. Max. Unit
CIN Input Capacitance 5 7 pF
PIN DESCRIPTION
Pin Name Type Description
REF IN Reference Clock Input
FB IN Feedback Input
TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
GND/ sOE (1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used
as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
VCCQ/PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
nQ[1:0] OUT Four banks of two outputs with programmable skew
VCCN PWR Power supply for output buffers
VCCQ PWR Power supply for phase locked loop and other internal circuitry
GND PWR Ground
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[1:0] = LL.
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V991A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q 1:0, 2Q1:0, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
FS = LOW FS = MID FS = HIGH Comments
Timing Unit Calculation (tU) 1/(44 x FNOM) 1/(26 x FNOM) 1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2) 15 to 35MHz 25 to 60MHz 40 to 85 MHz
Skew Adjustment Range(3)
Max Adjustment: ±9.09ns ±9.23ns ±9.38ns ns
±49º ±83º ±135º Phase Degrees
±14% ±23% ±37% % of Cycle Time
Example 1, FNOM = 15MHz tU = 1.52ns
Example 2, FNOM = 25MHz tU = 0.91ns tU = 1.54ns
Example 3, FNOM = 30MHz tU = 0.76ns tU = 1.28ns
Example 4, FNOM = 40MHz tU = 0.96ns tU = 1.56ns
Example 5, FNOM = 50MHz tU = 0.77ns tU = 1.25ns
Example 6, FNOM = 80MHz tU = 0.78ns
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF 1 : 0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4)
LL(1) –4tUDivide by 2 Divide by 2
LM –3tU–6tU–6tU
LH –2tU–4tU–4tU
ML –1tU–2tU–2tU
MM Zero Skew Zero Skew Zero Skew
MH 1tU2tU2tU
HL 2tU4tU4tU
HM 3tU6tU6tU
HH 4tUDivide by 4 Inverted(2)
NOTES:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW.
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Conditions Min. Max. Unit
VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 V
VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) 0.8 V
VIHH Input HIGH Voltage(1) 3-Level Inputs Only VCC0.6 V
VIMM Input MID Voltage(1) 3-Level Inputs Only VCC/20.3 VCC/2+0.3 V
VILL Input LOW Voltage(1) 3-Level Inputs Only 0.6 V
IIN Input Leakage Current VIN = VCC or GND ±5 µA
(REF, FB Inputs Only) VCC = Max.
VIN = VCC HIGH Level ±200
I33-Level Input DC Current (TEST, FS, nF1:0)VIN = VCC/2 MID Level ± 50 µA
VIN = GND LOW Level ±200
IPU Input Pull-Up Current (VCCQ/PE) VCC = Max., VIN = GND ±100 µA
IPD Input Pull-Down Current (GND/sOE)VCC = Max., VIN = VCC ±100 µA
VOH Output HIGH Voltage VCC = Min., IOH = 12mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 12mA 0.55 V
NOTE:
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
RECOMMENDED OPERATING RANGE IDT5V991A-2, -5, -7 IDT5V991A-2
(Industrial) (Commercial)
Symbol Description Min. Max. Min. Max. Unit
Vcc Power Supply Voltage 3 3.6 3 3.6 V
TAAmbient Operating Temperature -40 +85 0 +70 °C
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Typ.(2) Max. Unit
ICCQ Quiescent Power Supply Current VCC = Max., TEST = MID, REF = LOW, 8 25 mA
VCCQ/PE = LOW, GND/sOE = LOW
All outputs unloaded
ΔICC Power Supply Current per Input HIGH VCC = Max., VIN = 3V 1 30 μA
ICCD Dynamic Power Supply Current per Output VCC = Max., CL = 0pF 55 90 μA/MHz
ITOT Total Power Supply Current VCC = 3.3V, FREF = 20MHz, CL = 160pF(1) 29
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1) 42 mA
VCC = 3.3V, FREF = 66MHz, CL = 160pF(1) 76
NOTE:
1. For eight outputs, each loaded with 20pF.
INPUT TIMING REQUIREMENTS
Symbol Description (1) Min. Max. Unit
tR, tFMaximum input rise and fall times, 0.8V to 2V 10 ns/V
tPWC Input clock pulse, HIGH or LOW 3 n s
DHInput duty cycle 1 0 9 0 %
REF Reference Clock Input 3.75 85 MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V991A-2 IDT5V991A-5 IDT5V991A-7
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
FNOM VCO Frequency Range See PLL Programmable Skew Range and Resolution Table
tRPWH REF Pulse Width HIGH(11) 3— 33ns
tRPWL REF Pulse Width LOW(11) 3— 33ns
tUProgrammable Skew Time Unit See Control Summary Table
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3) 0.05 0.2 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs)(1,4,5) 0.1 0.25 0.25 0.5 0.3 0.75 ns
tSKEW1 Output Skew 0.25 0.5 0.6 0.7 0.6 1 ns
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,6)
tSKEW2 Output Skew 0.3 1.2 0.5 1.2 1 1.5 ns
(Rise-Fall, Nominal-Inverted, Divided-Divided)(1,6)
tSKEW3 Output Skew 0.25 0.5 0.5 0.7 0.7 1.2 ns
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)
tSKEW4 Output Skew 0.5 0.9 0.5 1 1.2 1.7 ns
(Rise-Fall, Nominal-Divided, Divided-Inverted)(1,2)
tDEV Device-to-Device Skew(1,2,7) 0.75 1.25 1.65 ns
tPD REF Input to FB Propagation Delay(1,9) 0.25 0 0.25 0.5 0 0.5 0.7 0 0.7 ns
tODCV Output Duty Cycle Variation from 50%(1) 1.2 0 1.2 1.2 0 1.2 1.2 0 1.2 ns
tPWH Output HIGH Time Deviation from 50%(1,10) 2 2.5 3 ns
tPWL Output LOW Time Deviation from 50%(1,11) 1.5 3 3.5 ns
tORISE Output Rise Time(1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns
tOFALL Output Fall Time(1) 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns
tLOCK PLL Lock Time(1,8) 0.5 0.5 0.5 ms
tJR Cycle-to-Cycle Output Jitter(1) RMS 25 25 25 ps
Peak-to-Peak 200 200 200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5V991A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
6
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
AC TEST LOADS AND WAVEFORMS
2.0V
tPWL
tPWH
tORISE tOFALL
0.8V
1ns 1ns
2.0V
0.8V
3.0V
0V
Vth = 1.5V
150Ω
VCC
Output
150Ω20pF
LVTTL Input Test Waveform
LVTTL Output Waveform
Test Load
7
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
REF
FB
Q
OTHER Q
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
tJR
tREF
tPD
tSKEW2
tSKEW3, 4
tSKEW1, 3, 4 tSKEW2, 4
tSKEW3, 4
tSKEW3, 4
tSKEW2
tSKEWPR
tSKEW0, 1
tODCV tODCV
tRPWH
tRPWL
tSKEWPR
tSKEW0, 1
AC TIMING DIAGRAM
NOTES:
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VCC/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0: The skew between outputs when they are selected for 0tU.
tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
8
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
ORDERING INFORMATION
IDT XXXXX XX X
Package Process
Device Type
Blank
I
5V991A-2
5V991A-5
5V991A-7
3.3V Programmable Skew PLL Clock Driver TurboClock
Rectangular Plastic Leaded Chip Carrier
PLCC - Green
J
JG
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com