A1357-DS
Features and Benefits
Two-wire output enables reduced wiring costs in
long wire systems
Simultaneous programming of PWM carrier frequency,
quiescent duty cycle (QDC), and sensitivity for system
optimization
Fully differential signal path increases EMC immunity and
reduces output offset drifts
Factory programmed sensitivity temperature coefficient
and quiescent duty cycle drift
Programmability at end-of-line
Pulse width modulated (PWM) current output provides
increased noise and EMC immunity compared to an
analog output
Precise recoverability after temperature cycling
• Duty cycle clamps provide short circuit diagnostic
capabilities
Optional 50% duty cycle calibration test mode at device
power up
Wide ambient temperature range: –40°C to 150°C
Resistant to mechanical stress
T wo-Wire High Precision Linear Hall-Ef fect Sensor IC
W ith Pulse Width Modulated Output Current
Package: 3-pin SIP (suffix KB)
Functional Block Diagram
Not to scale
A1357
Description
The A1357 device is a high precision, programmable two-wire
Hall-effect linear sensor IC with a pulse width modulated
(PWM) current. The A1357 device converts an analog signal
from its internal Hall sensor element to a digitally encoded
PWM signal. The coupled noise immunity of the digitally
encoded PWM is far superior to the noise immunity of an
analog output signal.
The BiCMOS, monolithic circuit inside of the A1357 integrates
a Hall element, precision temperature-compensating circuitry
to reduce the intrinsic sensitivity and offset drift of the Hall
element, a small-signal high-gain amplifier, proprietary
dynamic offset cancellation circuits, and PWM conversion
circuitry. The dynamic offset cancellation circuits reduce the
residual offset voltage of the Hall element that is normally
caused by device overmolding, temperature dependencies,
and thermal stress. The high frequency offset cancellation
(chopping) clock allows for a greater sampling rate, which
increases the accuracy of the output current signal and results
in faster signal processing capability.
The A1357 sensor is provided in a lead (Pb) free 3-pin single
inline package (KB suffix), with 100% matte tin leadframe
plating.
VCC (and
programming)
CBYBASS
VSUPPLY
GND
1
2
2
1
Temperature
Compensation
Chopper
Switches
Voltage Controlled
Current Source
PWM
Frequency Trim
Signal
Recovery
PWM Carrier
Generation
Regulator
Signal
Conditioning
% Duty Cycle
Temperature
Coefficient
% Duty
Cycle
Sensitivity
Trim
Amp
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pin-out Diagram
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Forward Supply Current ICC 50 mA
Reverse Supply Current IRCC –50 mA
Operating Ambient Temperature TAL temperature range –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg VCC = 0 V –65 to 170 ºC
Selection Guide
Part Number Packing*
A1357LKB-T 500 pieces per bag
A1357LKBTN-T 4000 pieces per 13-in. reel
*Contact Allegro™ for additional packing options
231
Terminal List Table
Number Name Function
1 VCC Input power supply; use bypass capacitor to connect to ground; also
used for programming
2 GND Ground
3 NC No connect
OPERATING CHARACTERISTICS Valid over full operating temperature range, TA , VCC = 4.5 to 18 V, CBYPASS = 0.1 μF, unless
otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit1
Electrical Characteristics
Supply Voltage2VCC 4.5 – 18 V
Supply Current ICC_LOW –68mA
ICC_HIGH 12 – 16.5 mA
Supply Current Ratio 2–– –
Supply Zener Clamp Voltage VZsupply ICC = 18 mA, TA = 25ºC 28 – – V
Power-On Time3,4 tPO fpwm = 1 kHz – – 5 ms
Internal Bandwidth BWi
Small signal –3 dB, 100 G(P-P) magnetic input
signal, TA = 25 C° – 400 – Hz
Chopping Frequency5fCTA = 25°C – 200 – kHz
Output Current Characteristics
PWMOUT Rise Time3,4 trVCC pin, No CBYPASS
or RSENSE, TA = 25 C° – 6.5 – mA/μs
PWMOUT Fall Time3,4 tfVCC pin, No CBYPASS
or RSENSE, TA = 25 C° – 6.5 – mA/μs
Maximum Propagation Delay3,4 tPROP TA = 25 C° – 2 3 ms
Response Time3,4 tRESPONSE
Impulse magnetic field of 300 G, fpwm = 1 kHz,
slew rate < 120 G/ms, TA = 25 C° – 2 3.125 ms
Duty Cycle Jitter3,4,6 JitterPWM
Measured over 1000 output PWM clock periods,
3 sigma values, Sens = 60 m% / G, TA = 25 C° – – ±0.090 % D
Clamp Duty Cycle DCLP(HIGH) 90 – 95 % D
DCLP(LOW) 5 – 10 % D
Pre-Programming Target7
Pre-Programming Quiescent Current
Duty Cycle D(Q)PRE B = 0 G, TA = 25°C – 50 – % D
Pre-Programming Sensitivity SensPRE TA = 25°C – 25 – (m% D)/G
Pre-Programming PWMOUT Carrier
Frequency fPWMPRE TA = 25°C – 1.5 – kHz
Quiescent Current Duty Cycle Programming
Initial Quiescent Current Duty Cycle D(Q)init B = 0 G, TA = 25°C – D(Q)PRE –% D
Guaranteed Quiescent Current Duty
Cycle Output Range8D(Q) B = 0 G, TA = 25°C 40 – 60 % D
Quiescent Current Duty Cycle
Programming Bits – 9 – bit
Average Quiescent Current Duty Cycle
Step Size9,10 StepD(Q) TA = 25°C 0.091 0.103 0.115 % D
Quiescent Current Duty Cycle
Programming Resolution11 ErrPGD(Q) TA = 25°C – StepD(Q)
× ±0. 5 –% D
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Continued on the next page…
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 μF, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
Sensitivity Programming
Initial Sensitivity Sensinit TA = 25°C – SensPRE – (% D)/G
Sensitivity Programming Bits
Range_
Selection TA = 25°C – 1 – bit
Fine TA = 25°C – 8 – bit
Guaranteed Sensitivity Range SensRange1 TA = 25°C 35 – 70 (m% D)/G
SensRange2 TA = 25°C 70 – 145 (m% D)/G
Average Sensitivity Step Size9,10 StepSENS1 TA = 25°C 215 300 375 (μ% D)/G
StepSENS2 TA = 25°C 430 600 750 (μ% D)/G
Sensitivity Programming Resolution11 ErrPGSENS TA = 25°C – StepSENS
× ±0. 5 –(μ% D)/G
Carrier Frequency Programming
Initial Carrier Frequency fPWMinit T
A = 25°C – fPWMPRE –Hz
Carrier Frequency Programming Range fPWM TA = 25°C 0.9 1 1.1 kHz
Carrier Frequency Programming Bits – 4 – bit
Average Carrier Frequency Step Size9,10 StepfPWM TA = 25°C 38 54 70 Hz
Carrier Frequency Programming
Resolution11 ErrPGfPWM TA = 25°C – StepfPWM
× ±0. 5 –Hz
Calibration Test Mode
Calibration Test Mode Selection Bit – 1 – bit
Calibration Test Mode Duration4tCAL fPWM = 1 kHz 45 50 55 ms
Output Duty Cycle During Calibration
Mode4DCAL 49 50 51 % D
Lock Bit Programming
Overall Programming Lock Bit LOCK – 1 – bit
Factory Programmed Sensitivity Temperature Coefficient And Drift Characteristics
Sensitivity Temperature Coefficient12 SensTC_
NdFeB
TA = 150°C – 0.11 – %/°C
Sensitivity Drift Through Temperature
Range13 SensTC TA = 150°C – < ±3 – %
Sensitivity Drift Due to Package
Hysteresis3SensPKG TA = 150°C, after temperature cycling – < ±1 – %
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , VCC = 4.5 to 18 V,
CBYPASS = 0.1 μF, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Factory Programmed Quiescent Current Duty Cycle Drift
Quiescent Current Duty Cycle
Temperature Coefficient12 DTC(Q) TA = 150°C – 0 – (% D)/°C
Quiescent Current Duty Cycle Drift
Through Temperature Range14 D(Q) Sens = SensPRE, TA = 150°C – < ±0.35 – % D
Error Components
Linearity Sensitivity Error LinERR – < ±1.5 – %
Symmetry Sensitivity Error SymERR – < ±1.5 – %
11 G (gauss) = 0.1 mT (millitesla).
2Supply Voltage is the voltage drop between device supply and ground pins. It does not include a drop through a sense resistor.
3See Characteristic Definitions section.
4Guaranteed by design only. Characterized but not tested in production.
5fC varies up to approximately ±20% through the full operating ambient temperature range, TA , and process.
6Jitter is dependent on the sensitivity of the device.
7Raw device characteristic values before any programming.
8D(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The D(Q) range is the total range from D(Q)(min)
up to and including D(Q)(max). See Characteristic Definitions section.
9Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
10Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum
specified value of StepD(Q) , StepSENS , or StepfPWM
.
11Overall programming value accuracy. See Characteristic Definitions section.
12Programmed at 150°C and calculated relative to 25°C.
13Sensitivity drift from expected value at TA after programming SENSTC. See Characteristic Definitions section.
14D(Q) drift from expected value at TA after programming DTC(Q).
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RJA 1-layer PCB with copper limited to solder pads 177 ºC/W
*Additional thermal data available on the Allegro Web site.
Ambient Temperature, TA (ºC)
Ambient Temperature, TA (ºC)
Maximum Allowable VCC (V)
Power Dissipation, P
D
(mW)
VCC(max)
VCC(min)
20
15
10
5
0
900
800
700
600
500
400
300
200
100
0
20 40 8060 100 120 140 160
20 40 8060 100 120 140 160
Power Dissipation versus Ambient Temperature
Power Derating Curve
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Definitions
Power-On Time When the supply is ramped to its operating
voltage, the device requires a finite time to power its internal
components before supplying a valid PWM output duty-cycle.
Power-On Time, tPO, is defined as the time it takes for the output
voltage to settle within ±10% of its steady state value after the
power supply has reached its minimum specified operating volt-
age, VCC(min). (See figure 1.)
Propagation Delay Traveling time of signal from input Hall
plate to output stage of device. (See figure 2.)
Response Time The time interval, tRESPONSE
, between
a) when the applied magnetic field reaches 90% of its final value,
and b) when the sensor IC reaches 90% of its output correspond-
ing to the applied magnetic field. (See figure 2.)
PWMOUT Rise Time The time, tr
, elapsed between 10% and
90% of the rising signal value when output current switches from
low to high states.
PWMOUT Fall Time The time, tf
, elapsed between 90% and
10% of the falling signal value when output current switches
from high to low states.
Quiescent Current Duty Cycle In the quiescent state (no
significant magnetic field: B = 0 G), the Quiescent Current Duty
Cycle, D(Q), equals a specific programmed duty cycle throughout
the entire operating ranges of VCC and ambient temperature, TA.
Guaranteed Quiescent Current Duty Cycle Range The
Quiescent Current Duty Cycle, D(Q), can be programmed around
its nominal value of 50% D, within the Guaranteed Quiescent
Duty Cycle Range limits: D(Q)(min) and D(Q)(max). The available
guaranteed programming range for D(Q) falls within the distribu-
tions of the minimum and the maximum programming code for
setting D(Q). (See figure 3.)
Average Quiescent Current Duty Cycle Step Size The
Average Quiescent Current Duty Cycle Step Size, StepD(Q) , for a
single device is determined using the following calculation:
D(Q)(max) – D(Q)(min)
2n –1
StepD(Q) =, (1)
where:
n is the number of available programming bits in the trim range,
2n – 1 is the value of programming steps in the range,
D(Q)(max) is the maximum reached quiescent duty cycle, and
D(Q)(min) is minimum reached quiescent duty cycle.
Figure 1. Definition of Power-On Time
Figure 2. Definitions of Propagation Delay and Response Time
Figure 3. Definition of Guaranteed Quiescent Voltage Output Range
Guaranteed D(Q)
Programming
Range
D(Q)(min) D(Q)(max)
Max Code D(Q)
Distribution
Min Code D(Q)
Distribution
Initial D(Q)
Distribution
Time
Time
VCC(min)
tPO
First valid duty cycle
VCC
ICC
Time
B-field
Icc
Propagation
Delay
1ms
AB
ADC BDC
ADC – DC corr esponds to the A fiel d
BDC – DC corr esponds to the B fiel d
C
Response
Time
0.9 ×
C
CDC
CDC – DC corresponds to the 0.9
×
C field
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quiescent Current Duty Cycle Output Programming
Resolution The programming resolution for any device is half
of its programming step size. Therefore, the typical programming
resolution will be:
ErrPGD(Q)(typ) =0.5 × StepD(Q)(typ) . (2)
Quiescent Duty Cycle Output Drift through Tempera-
ture Range Due to internal component tolerances and thermal
considerations, the Quiescent Duty Cycle Temperature Coef-
ficient, DTC(Q), may drift from its nominal value over the operat-
ing ambient temperature, TA. For purposes of specification, the
Quiescent Duty Cycle Output Drift Through Temperature Range,
D(Q) (% D), is defined as:
D(Q)(TA) – D(Q)(25°C)
∆D(Q) =, (3)
where D(Q)(TA) is the quiescent duty cycle measured at TA and
D(Q)(25°C) is the quiescent duty cycle measured at 25°C.
Sensitivity The presence of a south polarity magnetic field,
perpendicular to the branded surface of the package face,
increases the current duty cycle from its quiescent value toward
the maximum duty cycle limit. The amount of the current duty
cycle increase is proportional to the magnitude of the magnetic
field applied. Conversely, the application of a north polarity
field decreases the current duty cycle from its quiescent value.
This proportionality is specified as the magnetic Sensitiv-
ity, Sens ((% D)/G), of the device, and it is defined for bipolar
devices as:
D(BPOS) – D(BNEG)
BPOS – BNEG
Sens =, (4)
and for unipolar devices as:
D(BPOS) – D(Q)
BPOS
Sens =, (5)
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Guaranteed Sensitivity Range The magnetic Sensitivity can
be programmed from its initial value, Sensinit , to a value within
the Guaranteed Sensitivity Range limits: SensRange(min) and
SensRange(max).
Average Sensitivity Step Size Refer to the Average Qui-
escent Current Duty Cycle Step Size section for a conceptual
explanation.
Sensitivity Programming Resolution Refer to the Quies-
cent Current Duty Cycle Programming Resolution section for a
conceptual explanation.
Carrier Frequency Target The PWMOUT signal Carrier
Frequency Programming Range, fPWM, can be programmed to its
typical value of 1 kHz.
Average Carrier Frequency Step Size Refer to the Average
Quiescent Current Duty Cycle Step Size section for a conceptual
explanation.
Carrier Frequency Programming Resolution Refer to the
Quiescent Durrent Duty Cycle Programming Resolution section
for a conceptual explanation.
Sensitivity Temperature Coefficient Device sensitiv-
ity changes as temperature changes, with respect to its pro-
grammed Sensitivity Temperature Coefficient, SensTC. SensTC
is programmed at 150°C, and calculated relative to the nominal
sensitivity programming temperature of 25°C. SensTC (%/°C) is
defined as:
SensT2 – SensT1
SensT1 T2–T1
1
SensTC =×
100% ,
(6)
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the programming temperature of 150°C. The expected
value of Sens through the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensT1× [100% +SensTC (TA –T1)]
SensEXPECTED(TA) =.
100 % (7)
SensEXPECTED (TA) should be calculated using the actual measured
values of SensT1 and SensTC rather than programming target
values.
Sensitivity Drift Through Temperature Range Second
order Sensitivity Temperature Coefficient effects cause the mag-
netic Sensitivity, Sens, to drift from its expected value through
the operating ambient temperature range, TA. For purposes of
specification, the Sensitivity Drift Through Temperature Range,
SensTC
, is defined as:
SensTA – SensEXPECTED(TA)
SensEXPECTED(TA)
∆SensTC =×
100% .
(8)
Sensitivity Drift Due to Package Hysteresis Package
stress and relaxation can cause the device Sensitivity at TA =
25°C to change during and after temperature cycling.
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For purposes of specification, the Sensitivity Drift Due to Pack-
age Hysteresis, SensPKG, is defined as:
Sens(25°C)2 – Sens(25°C)1
Sens(25°C)1
∆SensPKG =×
100% ,
(9)
where Sens(25°C)1 is the programmed value of sensitivity at TA =
25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C,
after temperature cycling TA up to 150°C, down to –40°C, and
back to up 25°C.
Linearity Sensitivity Error The A1357 is designed to provide
a linear current output in response to a ramping applied magnetic
field. Consider two magnetic fields, B1 and B2. Ideally, the sen-
sitivity of a device is the same for both fields, for a given supply
voltage and temperature. Linearity error is present when there is a
difference between the sensitivities measured at B1 and B2.
Linearity Sensitivity Error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
Linearity error (%) is measured and defined as:
SensBPOS2
SensBPOS1
SensBNEG2
SensBNEG1
1–
LinERRPOS =×
100% ,
1–
LinERRNEG =×
100% ,
(10)
where:
|D(Bx) – D(Q)|
Bx
SensBx=.
(11)
and BPOSx and BNEGx are positive and negative magnetic fields,
with respect to the quiescent current duty cycle such that BPOS2 =
2 × BPOS1 and BNEG2 = 2 × BNEG1.
Then:
LinERR max(
LinERRPOS
, LinERRNEG)
=.
(12)
Note that unipolar devices only have positive linearity error
(LinERRPOS).
Symmetry Sensitivity Error The magnetic sensitivity of the
A1357 device is constant for any two applied magnetic fields of
equal magnitude and opposite polarities. Symmetry Sensitivity
Error, SymERR (%), is measured and defined as:
SensBPOS
SensBNEG
1–
SymERR =×
100% ,
(13)
where SensBx is as defined in equation 11, and BPOS and BNEG
are positive and negative magnetic fields such that |BPOS| =
|BNEG|. Note that the Symmetry Sensitivity Error specification is
valid only for bipolar devices.
Duty Cycle Jitter The duty cycle of the PWMOUT output may
vary slightly over time despite the presence of a constant applied
magnetic field and a constant Carrier Frequency, fPWM , for the
PWMOUT signal. This phenomenon is known as jitter, and is
defined as:
JitterPWM = ,
3 S
DBi±
1
n
n
i=1 (14)
where DB1 ,…, DBn are the sampled duty cycles in a constant
applied magnetic field, B, measured over 1000 PWM clock peri-
ods, and JitterPWM is given in % D.
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Application Circuit
GND
A1357
VCC
1
2
VSUPPLY
RSENSE
CBYPASS
0.1 μF
GND
A1357
VCC
1
2
VSUPPLY
RSENSE
CBYPASS
0.1 μF
The current switching performed by the Hall sensor IC can be
observed as voltage switching. To do so, place a sense resistor,
RSENSE , between the supply and the A1357 VCC pin (see figure
4), or between the A1357 GND pin and ground (figure 5). There
is an advantage to putting the sense resistor between the supply
and the A1357 VCC pin, because the resistor can then provide
additional device protection from supply transients.
When specifying value of the RSENSE and the applied supply volt-
age in the application, the following equation must be applied, in
order to provide enough voltage to allow the A1357 to power-up:
VSUPPLY > RSENSE × ICC_HIGH(max) + VCC(min) , (15)
where ICC(max) is the maximum A1357 supply current and
VCC(min) is the A1357 minimum supply voltage.
Substituting into equation 15:
12 V > RSENSE × 16.5 mA + 4.5 V ,
therefore:
RSENSE ≤ (12 – 4.5) V / 16.5 mA
≤ 454 .
It can be seen that RSENSE is proportional to VSUPPLY . The higher
the value of RSENSE , the higher the application supply voltage
required.
The recommended minimum CBYPASS value is 0.01 F.
Figure 4. High-side PWM voltage sensing configuration Figure 5. Low-side PWM voltage sensing configuration
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Overview
Programming is accomplished by sending a series of input volt-
age pulses serially through the VCC pin of the device. A unique
combination of different voltage level pulses controls the internal
programming logic of the device to select a programmable
parameter and change its value. There are three voltage levels
that must be taken into account when programming. These levels
are referred to as high, VP(HIGH)
, mid, VP(M ID), and low, VP(LOW)
.
The A1357 features Try mode, Blow mode and Lock mode:
• In Try mode, the value of multiple programmable parameters
may be set and measured simultaneously. The parameter values
are stored temporarily, and reset after cycling the supply volt-
age.
• In Blow mode, the value of a single programmable parameter
may be set and measured, and then permanently set by blowing
solid-state fuses internal to the device. Additional parameters
may be blown sequentially. This mode also is used for blow-
ing the device-level fuse (when Lock mode is enabled), which
permanently blocks the further programming of all parameters.
• Lock mode prevents all future programming of the device. This
is accomplished by blowing a special fuse using Blow mode.
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line. Although any programmable
variable power supply can be used to generate the pulse wave-
forms, Allegro highly recommends using the Allegro Sensor
Evaluation Kit, available on the Allegro website On-line Store.
The manual for that kit is available for download free of charge,
and provides additional information on programming this device.
Definition of Terms
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
register causes its programmable parameter to change, based on
the internal programming logic.
Key A series of mid-level voltage pulses used to select a register,
with a value expressed as the decimal equivalent of the binary
value. The LSB of a register is denoted as key 1, or bit 0.
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the program-
ming code (and parameter value) becomes permanent.
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. After a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the program-
ming settings in Try mode.
Programming Guidelines
Programming Pulse Requirements, Protocol at TA = 25 °C
Characteristic Symbol Notes Min. Typ. Max. Unit
Programming
Voltage
VP(LOW)
Measured at the VCC pin.
4.5 5 5.5 V
VP(MID) 13 15 16 V
VP(HIGH) 26 27 28 V
Programming
Current IP
Minimum supply current required to ensure proper fuse blowing. In addition, a
minimum capacitance, CBLOW = 0.1 μF, must be connected between the supply and
GND pins during programming to provide the current necessary for fuse blowing.
The blowing capacitor should be removed and the load capacitance used for properly
programming duty cycle measurements.
300 – – mA
Pulse Width
tLOW Duration of VP(LOW) for separating VP(MID) and VP(HIGH) pulses. 40 – – μs
tACTIVE Duration of VP(MID) and VP(HIGH) pulses for register selection or bit field addressing. 40 – – μs
tBLOW Duration of VP(HIGH) pulses for fuse blowing. 40 – – μs
Pulse Rise Time tPr Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH). 5 – 100 μs
Pulse Fall Time tPf Fall time required for transitions from VP(HIGH) to either VP(MID) or VP(LOW). 5 – 100 μs
T wo-Wire High Precision Linear Hall-Effect Sensor IC
W ith Pulse Width Modulated Output Current
A1357
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Mode and Parameter Selection
Each programmable mode and parameter can be accessed through
specific registers. To select a register, a sequence of voltage
pulses consisting of a VP(HIGH) pulse, a series of VP(MID) pulses,
and a VP(HIGH) pulse (with no VCC supply interruptions) must be
applied serially to the supply pin. The quantity of VP(MID) pulses
is called the key, and uniquely identifies each register. The pulse
train used for selection of the first register, key 1, is shown in
figure 6.
The A1357 has two registers that select among the three program-
mable modes:
• Register Mode 1:
Blow and Lock modes
• Register Mode 2:
Try mode
And there are four registers that select among the four program-
mable parameters:
• Register 1:
Sensitivity, Sens
• Register 2:
Quiescent Current Duty Cycle, D(Q)
• Register 3:
Pulse width modulated carrier frequency , fPWM
• Register 6:
Lock (device locking)
Bit Field Addressing
After a programmable parameter has been selected, a VP(HIGH)
pulse transitions the programming logic into the bit field address-
ing state. Applying a series of VP(MID) pulses to the VCC pin of
the device, as shown in figure 7, increases by one the bit field of
the selected parameter.
When addressing the bit field, the quantity of VP(MID) pulses
is represented by a decimal number called a code. Addressing
activates the corresponding fuse locations in the given bit field
by increasing the binary value of an internal DAC. The value of
the bit field (and code) increases by one with the falling edge
of each VP(MID) pulse, up to the maximum possible code (see
the Programming Logic table). As the value of the bit field code
increases, the value of the programmable parameter changes.
Measurements can be taken after each pulse to determine if the
required result for the programmable parameter has been reached.
Cycling the supply voltage resets all the locations in the bit field
that have unblown fuses to their initial states.
Fuse Blowing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appro-
priate register bit field. Blowing is accomplished by applying a
VP(HIGH) pulse, called a blow pulse, of sufficient duration at the
VP(HIGH) level to permanently set an addressed bit by blowing a
fuse internal to the device. Due to power requirements, the fuse
for each bit in the bit field must be blown individually. To accom-
plish this, the code representing the required parameter value
must be translated to a binary number. For example, as shown
in figure 8, decimal code 5 is equivalent to the binary number
101. Therefore bit 2 (code 4) must be addressed and blown, the
device power supply cycled, and then bit 0 (code 1) addressed
Programming Procedures
Figure 6. Parameter selection pulse train. This shows the sequence for
selecting the register corresponding to key 1, indicated by a single VP(MID)
pulse.
V+
0
t
LOW
t
ACTIVE
V
P(HIGH)
V
P(MID)
V
P(LOW)
Figure 7. Bit field addressing pulse train. Addressing the bit field by
increasing the code causes the programmable parameter value to change.
The number of bits available for a given programming code, n, varies
among parameters; for example, the bit field for D(Q) has 8 bits available,
which allows 255 separate codes to be used.
V+
0
V
P(HIGH)
V
P(MID)
V
P(LOW)
Code 1
Code 2
Code 2
n
– 2
Code 2
n
– 1
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and blown. An appropriate sequence for blowing code 5 is shown
in figure 9. The order of blowing bits, however, is not important.
Blowing bit 0 first, and then bit 2 is acceptable.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters.
Additional Guidelines
The additional guidelines presented in this section should be fol-
lowed to ensure the proper behavior of these devices:
• A 0.1 F blowing capacitor, CBLOW
, must be mounted between
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
• The application load capacitance, CL , should be used when
measuring the duty cycle during programming. The blowing
capacitor, CBLOW
, should be removed during measurement and
should only be applied when blowing fuses.
• The blowing capacitor, CBLOW
, must be replaced in the final
application with the load capacitance, CL , for proper operation.
• The power supply used for programming must be capable of
delivering at least 26 V and 300 mA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• The following programming order is recommended:
1. fPWM
2. Sens
3. D(Q)
4. Lock the device (only after all other parameters have been
programmed and validated, because this prevents any further
programming of the device)
Programming Modes
Try Mode Try mode allows multiple programmable parameters
to be tested simultaneously without permanently setting any
values. In this mode, each VP(HIGH) pulse will indefinitely loop
the programming logic through the mode, register, and bit field
selection states. There must be no interruptions in the VCC supply.
After powering the VCC supply, select mode key 2, followed
by the parameter register, and then address its bit field. When
addressing the bit field, each VP(MID) pulse increases the value
of the parameter register by one, up to the maximum possible
code (see Programming Logic section). The addressed parameter
value is stored in the device even after the programming drive
voltage is removed from the VCC pin, allowing its value to be
measured. To test an additional programmable parameter in
Figure 9. Example of Blow Mode programming pulses applied to the VCC pin. In this example, D(Q)
(Parameter Key 2) is addressed to code 4 (i.e bit 2) and its value is permanently blown.
V+
0
Mode
Selection
Parameter
Selection
(Key 1)
V
P(HIGH)
V
P(MID)
V
P(LOW)
(Key 2) (Code 4)
Addressing
Bitfield 2
t
BLOW
Code 4
Blow
t
Low
Cycle VCC
supply
Cycle VCC
supply
1121234
Figure 8. Example of code 5 broken into its binary components, which are
code 4 and code 1.
(Decimal Equivalent)
Code 5
Bit Field Selection
Address Code Format
Code in Binary
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
(Binary)
1 0 1
Bit 2 Bit 0
Code 4 Code 1
(Decimal Equivalents)
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conjunction with the original, enter an additional VP(HIGH) pulse
on the VCC pin to reenter the parameter selection field. Select a
different parameter register, and address its bit field, without any
supply interruptions. Both parameter values will be stored and
can be measured after removing the programming drive voltage.
Multiple programming combinations can be tested to achieve
optimal application accuracy. See figure 10 for an example of the
Try mode pulse train.
Registers can be addressed and re-addressed an indefinite number
of times in any order. After the required code is found for each
register, cycle the supply and blow the bit field using Blow mode.
Blow Mode After the required value of the programmable
parameter is found using Try mode, the corresponding code
should be blown to make the value permanent. To do this, first
select Blow mode as key 1, then the required parameter register,
and address and blow each required bit separately (as described
in the Fuse Blowing section). The supply must be cycled between
blowing each bit of a given code. After a bit is blown, cycling the
supply will not reset its value.
Single parameters can be still addressed in the Blow mode before
fuse blowing. Simultaneous addressing of multiple parameters,
as in Try mode, is not possible. After powering the VCC supply,
select the desired parameter register and address its bit field.
When addressing the bit field, each VP(MID) pulse increases
the value of the parameter register by one, up to the maximum
possible code (see Programming Logic table). The addressed
parameter value is stored in the device even after the program-
ming drive voltage is removed from the VCC pin, allowing its
value to be measured. It is not possible to decrease the value of
the register without resetting the parameter bit field. To reset the
bit field, and thus the value of the programmable parameter, cycle
the supply, VCC, voltage.
It is possible to switch between Try and Blow modes in that, after
individual programmable parameters have been blown in Blow
mode, other parameters can be still tested in Try mode.
Lock Mode To lock the device, first select Lock mode, then
address the Lock bit and apply a blow pulse with CBLOW in place.
After locking the device, no future programming of any param-
eter is possible.
V+
0
Mode
Selection
Parameter
Selection
(Key 2, Try Mode)
V
P(HIGH)
V
P(MID)
V
P(LOW)
(Key 1) (Code 3)
Addressing Parameter
Selection
(Key 2) (Code 2)
Addressing
12 1 12 12 123
Figure 10. Example of Try mode programming pulses applied to the VCC pin. In this example,
Sensitivity (parameter key 1) is addressed to code 3, and D(Q) (parameter key 2) is addressed
to code 2. The values set in the Sensitivity and D(Q) registers will be held in the device until the
supply is cycled. Permanent fuse blowing cannot be accomplished in Try mode.
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Programming State Machine
VP(HIGH) VP(HIGH)
VP(HIGH)
VP(HIGH)
VP(HIGH)
VP(HIGH)
2 x VP(HIGH)
VP(MID)
VP(MID)
VP(MID)
VP(MID) VP(MID) VP(MID)
VP(MID) 1
(Sens
Range1/
Range2)
2
(D(Q))
Select Mode
3
(fPWM/
Calibration
Test Mode)
6
(Lock All)
VP(MID) VP(MID) VP(MID)
VP(MID) VP(MID) VP(MID)
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Programming Logic Table
Mode or Parameter
Name
(Register Key)
Bit Field Address Description
Binary Format
[MSB → LSB] Decimal Equivalent Code
Programmable Mode
Lock, Blow
(1) 01 1 Entry to Lock or Blow mode
Try
(2) 10 2 Entry to Try mode
Programmable Parameter
Sens
(Range1/Range2)
(1)
0 0000 0000 0 Minimum Sens value in SensRange1, Sens =
SensPRE
0 1111 1111 255 Maximum Sens value in SensRange1
1 0000 0000 256 Minimum Sens value in SensRange2
1 1111 1111 511 Maximum Sens value in SensRange2
D(Q)
(2)
0 0000 0000 0 Initial value, D(Q) = D(Q)PRE
0 1111 1111 255 Maximum quiescent current duty cycle in range
1 0000 0000 256 Switch from programming increasing D(Q) to
programming decreasing D(Q)
1 1111 1111 511 Minimum quiescent current duty cycle in range
fPWM
/
Calibration Test Mode
(3)
0 0000 0000 0 Initial value; fPWM = fPWMPRE
0 0000 1111 15 Minimum PWM frequency in range
0 0001 0000 16 Enable 50% Duty Cycle Calibration Test Mode
Lock All
(6) 10 0000 0000 512 Enable blowing Lock fuse to lock device
Sens
(%/gauss)
D(Q)
(%)
Quiescent Current
Duty Cycle Range
D(Q)(max)
D(Q)(min)
D(Q)PRE
fPWM
(Hz)
fPWMPRE
fPWM(max)
fPWM(min)
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The calibration mode is provided so that the user can compensate
for differences in the ground potential between the A1357 and
any interface circuitry used to measure the pulse width of the
A1357 current. The test mode is optional and must be enabled
by blowing programming bits. After the bit for the test mode has
been blown, the device enters 50% Duty Cycle Calibration Test
mode every time the device is powered-up. The bit enabling test
mode is key 3, bit 4.
In customer applications, the PWM interface circuitry (shown
as the system controller in figure 11) and the A1357 may be
powered via different power and ground circuits. As a result, the
ground reference for the A1357 may differ from the ground refer-
ence of the system controller. In some customer applications, this
ground difference can be as large as ±0.5 V.
Differences in the ground reference for the A1357 and the system
controller can result in variations in the threshold voltage used
to measure the duty cycle of the A1357. If the PWM conversion
threshold voltage varies, then the duty cycle will vary because
there is a finite rise time, tr , and fall time, tf , in the PWM wave-
form. This problem is shown in figure 12.
50% Duty Cycle Calibration Test Mode
PWM period
Duty Cycle
shorter than
expected
Duty Cycle at
expected duration
Duty Cycle longer
than expected
Vth (high)
∆tr∆tf
Vth (centered)
Vth (low)
2.5
3.5
1.5
Threshold Voltage,
Vth (V)
Time
Figure 12. When the threshold voltage, Vth , is correctly centered between Vth (high) and Vth (low) , the current duty cycle
accurately coincides with the applied magnetic field. If the threshold voltage is raised, the current duty cycle appears shorter
than expected. Conversely, if the threshold voltage is lowered, the current duty cycle is longer than expected.
GND1 GND2
System
Controller
GND
A1357
VCC
1
2
VSUPPLY
RSENSE
CBYPASS
0.1 μF
Figure 11. In many applications the A1357 may be powered using a different ground reference
than the system controller. This may cause the ground reference for the A1357 (GND1) to differ
from the ground reference of the system controller (GND2) by as much as to ± 0.5 V.
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The 50% Duty Cycle Calibration Test mode allows end users to
compensate for any threshold errors that result from a difference
in system ground potentials. When calibration mode has been
enabled, at power-up the device operates initially in calibration
mode for tCAL , 50 ms, during which the device current waveform
has a fixed 50% duty cycle (the programmed quiescent duty
cycle, D(Q) , value) regardless of the applied external magnetic
field (see figure 13). This allows the system controller to com-
pare the measured quiescent duty cycle with an ideal 50% duty
cycle. After tCAL has elapsed, the duty cycle will correspond to
an applied magnetic field as expected. The calibration test time
(tCAL) corresponds with a target PWM frequency of 1 kHz. If the
PWM frequency is programmed away from its target of 1 kHz,
the duration of the calibration test time will scale inversely with
the change in PWM frequency.
Figure 13. With calibration mode in effect, after powering-on the A1357 outputs a 50%
duty cycle for the first 50 ms, tCAL , regardless of the applied magnetic field. After tCAL has
elapsed, the output responds to a magnetic field as expected. The example in this figure
assumes that a large +B field is applied to the device after tCAL has elapsed.
Calibration sequence PWM proportional to
magnetic field
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Package KB, 3-Pin SIP
1.90 NOM
2.16
MAX
45°
45°
0.84 REF
231
A
Gate and tie bar burr area
A
B
B
C
D
E
E
Dambar removal protrusion (6X)
Mold Ejector
Pin Indent
Branded
Face
Standard Branding Reference View
N = Device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
YYWW
NNNN
1
5.21 +0.08
–0.05
0.38 +0.06
–0.03
3.43 +0.08
–0.05
0.51 +0.07
–0.05
14.73 ±0.51
1.55 ±0.05
For Reference Only; not for tooling use (reference DWG-9009)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Branding scale and appearance at supplier discretion
D
D
D
1.33
2.60
C
Hall element (not to scale)
Active Area Depth 0.43 mm REF
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Allegro MicroSystems, LLC
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1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
