1
TM HUF76131SK8
10A, 30V, 0.013 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76131.
Features
• Logic Level Gate Drive
• 10A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.013Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC MS-012AA
Ordering Information
PART NUMBER PACKAGE BRAND
HUF76131SK8 MS-012AA 76131SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76131SK8T.
®
SOURCE(2)
DRAIN(8)
SOURCE(1)
DRAIN(7)
DRAIN(6)
DRAIN(5)
SOURCE(3)
GATE(4)
BRANDING DASH
1234
5
Data Sheet June 2000 File Number 4396.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 |Copyright © Intersil Corporation 2000.
2
Absolute Maximum Ratings TA= 25oC, Unless Otherwise Specified HUF76131SK8 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 30 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 30 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±16 V
Drain Current
Continuous (Figure 2) (Notes 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 10
Figure 5 A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5
0.02 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 30 - - V
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 1 - - V
Zero Gate Voltage Drain Current IDSS VDS = 25V, VGS = 0V - - 1 µA
VDS = 25V, VGS = 0V, TA = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
Drain to Source On Resistance rDS(ON) ID = 10A, VGS = 4.5V (Figures 9,14) - 0.017 0.018 Ω
ID = 10A, VGS = 5V - 0.015 0.017 Ω
ID = 10A, VGS = 10V - 0.011 0.013 Ω
Turn-On Time tON VDD = 15V, ID≅ 10A, RL = 1.5Ω, VGS =5V,
RGS = 6.8Ω
(Figure 15)
- - 115 ns
Turn-On Delay Time td(ON) -15-ns
Rise Time tr-61-ns
Turn-Off Delay Time td(OFF) -33-ns
Fall Time tf-36-ns
Turn-Off Time tOFF - - 105 ns
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 15V, ID≅ 10A,
RL= 1.5Ω, Ig(REF) = 1.0mA
(Figure 13)
-3947nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 22 26 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 1.53 1.85 nC
Gate to Source Gate Charge Qgs - 4.00 - nC
Gate to Drain “Miller” Charge Qgd - 9.50 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12) - 1605 - pF
Output Capacitance COSS - 685 - pF
Reverse Transfer Capacitance CRSS - 115 - pF
Thermal Resistance Junction to Ambient RθJA Pad Area = 0.76 in2 (Note 2) - - 50 oC/W
Pad Area = 0.054 in2 (See TB377) - - 143.4 oC/W
Pad Area = 0.0115 in2 (See TB377) - - 177.3 oC/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 10A - - 1.25 V
ISD = 2.3A - - 1.1 V
Reverse Recovery Time trr ISD = 2.3A, dISD/dt = 100A/µs--57ns
Reverse Recovered Charge QRR ISD = 2.3A, dISD/dt = 100A/µs--81nC
NOTES:
2. 50oC/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds.
3. 177.3oC/W measured using FR-4 board with 0.0115 in2 footprint at 1000 seconds.
HUF76131SK8
3
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
8
4
025 50 75 100 125 150
6
10
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
12
2
t, RECTANGULAR PULSE DURATION (s)
10-5 10-1 100
10
0.01
1
10-2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
0.001 10-4 10-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
PDM
t1t2
101
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
0.1
102103
TJ = MAX RATED
TA = 25oC
100µs
10ms
1ms
VDSS(MAX) = 30V
10 1001 VDS, DRAIN TO SOURCE VOLTAGE (V)
1
100
500
10
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
IDM, PEAK CURRENT (A)
1000
1
10-5 10-4 10-3 10-2 10-1 100101
t, PULSE WIDTH (s)
TA = 25oC
I = I25 150 - TA
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
10
HUF76131SK8
4
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
1 10 100
100
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
0.1
10
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
10
20
30
00.5 1.0 1.5 2.0 2.5
40
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
TA = 25oC
50
VGS = 5V
VGS = 10V
VGS = 4.5V
VGS = 4V
VGS = 3.5V
VGS = 3V
DUTY CYCLE = 0.5% MAX
0 2.5 3.0 3.5 4.02.0
0
10
20
30
40
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
150oC
-55oC
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
50
0.5 1.0 1.5 0.75
1.0
1.25
1.5
1.75
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs
VGS = 10V, ID = 10A
DUTY CYCLE = 0.5% MAX
-80 -40 0 40 80 120 160
0.4
0.6
0.8
1.0
1.2
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA1.2
1.1
1.0
0.9
0.8
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
HUF76131SK8
5
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes 7254 and 7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 14. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
2500
1500
00 5 10 15 20 25
C, CAPACITANCE (pF)
2000
VDS, DRAIN TO SOURCE VOLTAGE (V)
1000
CISS
COSS
CRSS
30
500
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
10
8
6
4
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 15V
2
30 40 50
0Qg, GATE CHARGE (nC)
10 20
ID = 20A
ID = 10A
ID = 5A
ID= 2.5A
WAVEFORMS IN
DESCENDING ORDER:
20
40
60
80
04
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), ON-STATE RESISTANCE (mΩ)
061082
ID = 20A
ID = 10A
ID = 5A
ID = 2.5A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
100
20 30 40 500
200
150
50
010
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VDD = 15V, ID = 10A, RL= 1.5Ω
td(OFF)
tf
td(ON)
tr
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF76131SK8
6
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
Ig(REF)
0
0
HUF76131SK8
7
Thermal Resistance vs Mounting P ad Area
The maximum rated junction temperature TJMAX constrains
the maximum allowable device power dissipation PDmax in
an application. The application ambient temperature TA(oC)
and thermal impedance ZθJA (oC/W) must be reviewed to
ensure that TJMAX (oC) is never exceeded. Equation 1
mathematically represents the relationship.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Precise determination of
PDMAX is complex and influenced by many factors:
1. PC heat sink area and location (top and bottom), copper
leads and mounting pad area.
2. Air Flow, board orientation and type.
3. Power pulse width and duty factor.
Figure 22 addresses these points by depicting RθJA values
vs. top copper (component side) heat sink area. The
measurements were performed in still air using a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power.
Figure 22 also displays the two RθJA values listed in the
Electrical Specifications table. The two points were chosen
to graphically depict the compromise between copper board
area, thermal resistance and ultimately power dissipation.
Thermal resistance values corresponding to other
component side copper areas can be obtained from Figure
22 or by calculation using Equation 2. Area in Equation 2 is
the top copper area including the gate and source pads.
Figure 22 provides the necessary information for steady
state junction temperature or power dissipation calculations.
Transient pulse applications are best studied using the
Intersil device SPICE thermal model.
(EQ. 1)
PDMAX TJMAX TA
–()
ZθJA
----------------------------------------=
(EQ. 2)
RθJA 79.3 21.8 Area()ln×–=
RθJA (oC/W)
50
100
150
200
AREA, TOP COPPER AREA (in2)
0.01 0.1 1.0
RθJA = 79.3 - 21.8*ln(AREA)
143.4oC/W - 0.054in2
177.3oC/W - 0.0115in2
IGURE 22. THERMAL RESISTANCE vs MOUNTING PAD AREA
0.001
250
HUF76131SK8
8
PSPICE Electrical Model
SUBCKT HUF76131 2 1 3 ; rev 12/31/97
CA 12 8 2.22-9
CB 15 14 2.13e-9
CIN 6 8 1.52e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 37.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 1.29e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.94e-3
RGATE 9 20 2.20
RLDRAIN 2 5 10
RLGATE 1 9 10.4
RLSOURCE 3 7 1.29
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 8.75e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),3))}
.MODEL DBODYMOD D (IS = 2.25e-12 RS = 6.05e-3 IKF=16.00 TRS1 = 1.14e-4 TRS2 = 1.23e-6 CJO = 2.35e-9 TT = 2.71e-8 M = 0.44)
.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 1.01e-4 TRS2 = 1.11e-7)
.MODEL DPLCAPMOD D (CJO = 1.08e-9 IS = 1e-30 N = 10 M = 0.69)
.MODEL MMEDMOD NMOS (VTO = 1.89 KP = 5.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.20)
.MODEL MSTROMOD NMOS (VTO = 2.22 KP = 125.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.54e-4 TC2 = 1.07e-7)
.MODEL RDRAINMOD RES (TC1 = 1.61e-2 TC2 = 5.17e-5)
.MODEL RSLCMOD RES (TC1 = 1.03e-5 TC2 = 7.67e-7)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -2.81e-3 TC2 = -8.75e-6)
.MODEL RVTEMPMOD RES (TC1 = -6.68e-4 TC2 = 8.80e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.80 VOFF= -1.50)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.50 VOFF= -5.80)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= -0.00)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76131SK8
9
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
SPICE Thermal Model
REV 20 Feb 98
HUF76131
CTHERM1 7 6 3.75e-4
CTHERM2 6 5 3.05e-3
CTHERM3 5 4 3.70e-2
CTHERM4 4 3 2.52e-2
CTHERM5 3 2 8.50e-2
CTHERM6 2 1 7.95e-1
RTHERM1 7 6 3.95e-2
RTHERM2 6 5 2.50e-1
RTHERM3 5 4 4.00e-1
RTHERM4 4 3 6.35
RTHERM5 3 2 2.02e1
RTHERM6 2 1 4.80e1
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
1
2
3
4
5
6
7JUNCTION
CASE
HUF76131SK8
10
HUF76131SK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
MS-012AA
12mm TAPE AND REEL
AA1
E
E1
e
b
D
L
h x 45o
2
0o-8o
c
0.004 IN
0.10 mm
56
0.155
4.0
0.275
7.0
0.050
1.27
0.024
0.6
0.060
1.52
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A10.004 0.0098 0.10 0.25 -
b 0.013 0.020 0.33 0.51 -
c 0.0075 0.0098 0.19 0.25 -
D 0.189 0.1968 4.80 5.00 2
E 0.2284 0.244 5.80 6.20 -
E10.1497 0.1574 3.80 4.00 3
e 0.050 BSC 1.27 BSC -
H 0.0099 0.0196 0.25 0.50 -
L 0.016 0.050 0.40 1.27 4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. Thechamferonthebodyisoptional.Ifitisnotpresent,avisualindex
feature m ust be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
USER DIRECTION OF FEED
L
C
2.0mm
4.0mm
1.75mm
1.5mm
DIA. HOLE
8.0mm
12mm
COVER TAPE
330mm 50mm
13mm
18.4mm
12.4mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
ACCESS HOLE
40mm MIN.
