UPD5713TK-E2-A - NEC - Datasheet.Live

LF412

January 28, 2010

Low Offset, Low Drift Dual JFET Input Operational

Amplifier

General Description

These devices are low cost, high speed, JFET input opera-

tional amplifiers with very low input offset voltage and guar-

anteed input offset voltage drift. They require low supply

current yet maintain a large gain bandwidth product and fast

slew rate. In addition, well matched high voltage JFET input

devices provide very low input bias and offset currents. The

LF412 dual is pin compatible with the LM1558, allowing de-

signers to immediately upgrade the overall performance of

existing designs.

These amplifiers may be used in applications such as high

speed integrators, fast D/A converters, sample and hold cir-

cuits and many other circuits requiring low input offset voltage

and drift, low input bias current, high input impedance, high

slew rate and wide bandwidth.

Features

■Internally trimmed offset voltage: 1 mV (max)

■Input offset voltage drift: 10 μV/°C (max)

■Low input bias current: 50 pA

■Low input noise current:

■Wide gain bandwidth: 3 MHz (min)

■High slew rate: 10V/μs (min)

■Low supply current: 1.8 mA/Amplifier

■High input impedance: 1012Ω

■Low total harmonic distortion ≤0.02%

■Low 1/f noise corner: 50 Hz

■Fast settling time to 0.01%: 2 μs

Typical Connection

565641

Ordering Information

LF412XYZ

Xindicates electrical grade

Yindicates temperature range

“M” for military

“C” for commercial

Zindicates package type

“H” or “N”

Connection Diagrams

Metal Can Package

565642

Order Number LF412MH, LF412CH

See NS Package Number H08A

or LF412MH/883 (Note 1)

See NS Package Number H08C

Dual-In-Line Package

565644

Order Number LF412ACN, LF412CN

or LF412MJ/883 (Note 1)

See NS Package Number J08A or N08E

BI-FET II™ is a trademark of National Semiconductor Corporation.

LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier

Simplified Schematic

1/2 Dual

565643

Note 1: Available per JM38510/11905

Detailed Schematic

565632

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LF412

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

(Note 11)

LF412A LF412

Supply Voltage ±22V ±18V

Differential Input Voltage ±38V ±30V

Input voltage Range

(Note 3)±19V ±15V

Output Short Circuit

Duration (Note 4) Continuous Continuous

H Package N Package

Power Dissipation

(Note 12)(Note 5) 670 mW

Tj max 150°C 115°C

θjA (Typical) 152°C/W 115°C/W

Operating Temp. Range (Note 6) (Note 6)

Storage Temp. −65°C≤TA≤150°

−65°C≤TA≤150°

Range

Lead Temp.

(Soldering, 10 sec.) 260°C 260°C

ESD Tolerance

(Note 13)1700V 1700V

DC Electrical Characteristics

(Note 7)

Symbol Parameter Conditions LF412A LF412 Units

Min Typ Max Min Typ Max

VOS Input Offset Voltage RS=10 kΩ, TA=25°C 0.5 1.0 1.0 3.0 mV

ΔVOS/ΔTAverage TC of Input RS=10 kΩ (Note 8) 7 10 7 20 μV/°C

Offset Voltage

IOS Input Offset Current VS=±15V Tj=25°C 25 100 25 100 pA

(Note 7, Note 9)Tj=70°C 2 2 nA

Tj=125°C 25 25 nA

IBInput Bias Current VS=±15V Tj=25°C 50 200 50 200 pA

(Note 7, Note 9)Tj=70°C 4 4 nA

Tj=125°C 50 50 nA

RIN Input Resistance Tj=25°C 1012 1012 Ω

AVOL Large Signal Voltage VS=±15V, VO=±10V, 50 200 25 200 V/mV

Gain RL=2k, TA=25°C

Over Temperature 25 200 15 200 V/mV

VOOutput Voltage Swing VS=±15V, RL=10k ±12 ±13.5 ±12 ±13.5 V

VCM Input Common-Mode ±16 +19.5 ±11 +14.5 V

Voltage Range −16.5 −11.5 V

CMRR Common-Mode RS≤10k 80 100 70 100 dB

Rejection Ratio

PSRR Supply Voltage (Note 10) 80 100 70 100 dB

Rejection Ratio

ISSupply Current VO = 0V, RL = ∞ 3.6 5.6 3.6 6.5 mA

Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device

is functional, but do not guarantee specific performance limits.

AC Electrical Characteristics

(Note 7)

Symbol Parameter Conditions LF412A LF412 Units

Min Typ Max Min Typ Max

Amplifier to Amplifier TA=25°C, f=1 Hz-20 kHz −120 −120 dB

Coupling (Input Referred)

SR Slew Rate VS=±15V, TA=25°C 10 15 8 15 V/μs

GBW Gain-Bandwidth Product VS=±15V, TA=25°C 3 4 2.7 4 MHz

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LF412

Symbol Parameter Conditions LF412A LF412 Units

Min Typ Max Min Typ Max

THD Total Harmonic Dist AV=+10, RL=10k,

VO=20 Vp-p,

BW=20 Hz-20 kHz

≤0.02 ≤0.02 %

enEquivalent Input Noise TA=25°C, RS=100Ω, 25 25

Voltage f=1 kHz

inEquivalent Input Noise TA=25°C, f=1 kHz 0.01 0.01

Current

Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 4: Any of the amplifier outputs can be shorted to ground indefintely, however, more than one should not be simultaneously shorted as the maximum junction

temperature will be exceeded.

Note 5: For operating at elevated temperature, these devices must be derated based on a thermal resistance of θjA.

Note 6: These devices are available in both the commercial temperature range 0°C≤TA≤70°C and the military temperature range −55°C≤TA≤125°C. The

temperature range is designated by the position just before the package type in the device number. A “C” indicates the commercial temperature range and an

“M” indicates the military temperature range. The military temperature range is available in “H” package only. In all cases the maximum operating temperature is

limited by internal junction temperature Tj max.

Note 7: Unless otherwise specified, the specifications apply over the full temperature range and for VS=±20V for the LF412A and for VS=±15V for the LF412.

VOS, IB, and IOS are measured at VCM=0.

Note 8: The LF412A is 100% tested to this specification. The LF412 is sample tested on a per amplifier basis to insure at least 85% of the amplifiers meet this

specification.

Note 9: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature, Tj. Due to limited

production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient

temperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is

recommended if input bias current is to be kept to a minimum.

Note 10: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice.

VS = ±6V to ±15V.

Note 11: Refer to RETS412X for LF412MH and LF412MJ military specifications.

Note 12: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate

outside guaranteed limits.

Note 13: Human body model, 1.5 kΩ in series with 100 pF.

Typical Performance Characteristics

Input Bias Current

565610

Input Bias Current

565611

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LF412

Supply Current

565612

Positive Common-Mode

Input Voltage Limit

565613

Negative Common-Mode

Input Voltage Limit

565614

Positive Current Limit

565615

Negative Current Limit

565616

Output Voltage Swing

565617

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LF412

Output Voltage Swing

565618

Gain Bandwidth

565619

Bode Plot

565620

Slew Rate

565621

Distortion vs Frequency

565622

Undistorted Output Voltage

Swing

565623

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LF412

Open Loop Frequency

Response

565624

Common-Mode Rejection

Ratio

565625

Power Supply Rejection

Ratio

565626

Equivalent Input Noise

Voltage

565627

Open Loop Voltage Gain

565628

Output Impedance

565629

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LF412

Inverter Settling Time

565630

Pulse Response

RL=2 kΩ, CL=10 pF

Small Signal Inverting

565636

Small Signal Non-Inverting

565637

Large Signal Inverting

565638

Large Signal Non-Inverting

565639

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LF412

Current Limit (RL=100Ω)

565640

Application Hints

The LF412 series of JFET input dual op amps are internally

trimmed (BI-FET II™) providing very low input offset voltages

and guaranteed input offset voltage drift. These JFETs have

large reverse breakdown voltages from gate to source and

drain eliminating the need for clamps across the inputs.

Therefore, large differential input voltages can easily be ac-

commodated without a large increase in input current. The

maximum differential input voltage is independent of the sup-

ply voltages. However, neither of the input voltages should be

allowed to exceed the negative supply as this will cause large

currents to flow which can result in a destroyed unit.

Exceeding the negative common-mode limit on either input

will cause a reversal of the phase to the output and force the

amplifier output to the corresponding high or low state.

Exceeding the negative common-mode limit on both inputs

will force the amplifier output to a high state. In neither case

does a latch occur since raising the input back within the

common-mode range again puts the input stage and thus the

amplifier in a normal operating mode.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output, however, if both inputs

exceed the limit, the output of the amplifier may be forced to

a high state.

The amplifiers will operate with a common-mode input voltage

equal to the positive supply; however, the gain bandwidth and

slew rate may be decreased in this condition. When the neg-

ative common-mode voltage swings to within 3V of the neg-

ative supply, an increase in input offset voltage may occur.

Each amplifier is individually biased by a zener reference

which allows normal circuit operation on ±6.0V power sup-

plies. Supply voltages less than these may result in lower gain

bandwidth and slew rate.

The amplifiers will drive a 2 kΩ load resistance to ±10V over

the full temperature range. If the amplifier is forced to drive

heavier load currents, however, an increase in input offset

voltage may occur on the negative voltage swing and finally

reach an active current limit on both positive and negative

swings.

Precautions should be taken to ensure that the power supply

for the integrated circuit never becomes reversed in polarity

or that the unit is not inadvertently installed backwards in a

socket as an unlimited current surge through the resulting

forward diode within the IC could cause fusing of the internal

conductors and result in a destroyed unit.

As with most amplifiers, care should be taken with lead dress,

component placement and supply decoupling in order to en-

sure stability. For example, resistors from the output to an

input should be placed with the body close to the input to

minimize “pick-up” and maximize the frequency of the feed-

back pole by minimizing the capacitance from the input to

ground.

A feedback pole is created when the feedback around any

amplifier is resistive. The parallel resistance and capacitance

from the input of the device (usually the inverting input) to AC

ground set the frequency of the pole. In many instances the

frequency of this pole is much greater than the expected

3 dB frequency of the closed loop gain and consequently

there is negligible effect on stability margin. However, if the

feedback pole is less than approximately 6 times the expected

3 dB frequency a lead capacitor should be placed from the

output to the input of the op amp. The value of the added

capacitor should be such that the RC time constant of this

capacitor and the resistance it parallels is greater than or

equal to the original feedback pole time constant.

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LF412

Typical Application

Single Supply Sample and Hold

565631

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LF412

Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)

Order Number LF412MH or LF412CH

NS Package Number H08A

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LF412

Metal Can Package (H)

Order Number LF412MH/833

NS Package Number H08C

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LF412

Dual-In-Line Package (J)

Order Number LF412MJ/883

NS Package Number J08A

Dual-In-Line Package (N)

Order Number LF412ACN or LF412CN

NS Package Number N08E

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LF412

Notes

LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier

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