07-2001
ARA2004
Reverse Amplifier with Step Attenuator
PRELIMINARY DATA SHEET - Rev 1.0
FEATURES
·Low cost integrated amplifier with step
attenuator
·Attenuation Range: 0-58 dB, adjustable in
1dB increments via a 3 wire serial control
·Meets DOCSIS distortion requirements at
+60dBmV output signal level
·Low distortion and low noise
·Frequency range: 5-100MHz
·5 Volt operation
·-40 to +85 0C temperature range
APPLICATIONS
·MCNS/DOCSIS Compliant Cable Modems
·CATV Interactive Set-Top Box
·Telephony over Cable Systems
·OpenCable Set-Top Box
·Residential Gateway
The ARA2004 is designed to provide the reverse path
amplification and output level control functions in a
CATV Set-Top Box or Cable Modem. It incorporates
a digitally controlled precision step attenuator that is
preceded by an ultra low noise amplifier stage, and
followed by an ultra-linear output driver amplifier. This
device uses a balanced circuit design that exceeds
the MCNS/DOCSIS requirement for harmonic
performance at a +60dBmV output level while only
requiring a single polarity +5V supply. Both the input
and output are matched to 75 ohms with an
appropriate transformer. The precision attenuator
provides up to 58 dB of attenuation in 1 dB increments
via a three-wire serial interface. With external passive
components, this device meets IEC 1000-4-12 and
ANSI/IEEE C62.41-1991 100KHz ringwave tests, as
well as IEC1000-4-5 1.2/50mS surge tests. The
ARA2004 is offered in a 28-pin SSOP package
featuring an exposed paddle on the bottom of the
package.
PRODUCT DESCRIPTION
Figure 1: Cable Modem or Set Top Box Application Diagram
S23 Package
28 Pin SSOP
with Exposed Paddle
Diplexer
ARA2004
SAW
Filter
Double-
Conversion
Tuner
MAC
Upstream
QPSK/16QAM
Modulator
QAM Receiver
with FE C
Balun Low Pass
Filter
Transmit Enable/Disable
Enable
Data
Clock
Microcontroller
with Ethernet
MAC
RAM ROM
10Base-T
Transceiver
RJ45
Connector
Clock
Clock
Data
Data
54-860 MHz
44 MHz
5-42 MHz
2PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
Figure 2: Functional Block Diagram
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
EFET
EFET
GaAs IC
ATT
IN
(+)
A1
OUT
(+)
A1
IN
(+)
I
SET1
Vg1
A1
OUT
(-)
A1
IN
(-)
ATT
IN
(-) ATT
OUT
(-)
A2
IN
(-)
A2
OUT
(-)
Vg2
I
SET2
A2
OUT
(+)
A2
IN
(+)
ATT
OUT
(+)
16 dB 1 dB2 dB4 dB8 dB32 dB
CMOS IC (Serial to Parallel Interface)
8-Bit Shi ft
Register/
Address
Buffer
Control Latch
P5 P4 P3 P2 P1 P0
8
Clock
Data
Enable
Figure 3: Pin Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND GND
I
SET1
A1
OUT
(-)
Vg1
ATT
IN
(-)
V
CMOS
A1
IN
(+)
A1
OUT
(+)
CLK
ATT
IN
(+)
DAT
V
ATTN
En
A1
IN
(-) A2
OUT
(-)
I
SET2
A2
IN
(-)
Vg2
ATT
OUT
(-)
A2
OUT
(+)
GND
CMOS
A2
IN
(+)
N/C
ATT
OUT
(+)
N/C
N/C
N/C
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
3
ARA2004
Table 1: Pin Description
NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED
1DNGdnuorG51C/NnoitcennoCoN
)1(
2V
NTTA
rotaunettArofylppuS61C/NnoitcennoCoN
)1(
3TTA
NI
)+(tupnI)+(rotaunettA
)2(
71C/NnoitcennocoN
)1(
41A
TUO
)+(tuptuO)+(1AreifilpmA81DNG
SOMC
latigiDrofdnuorG
tiucriCSOMC
51A
NI
)+(tupnI)+(1AreifilpmA
)2(
91TTA
TUO
)-(tuptuO)-(rotaunettA
)2(
61gVlortnoC)-/+(1AreifilpmA022A
NI
)-(tupnI)-(2AreifilpmA
)2(
7I
1TES
tnerruC)-/+(1AreifilpmA
tsujdA 122A
TUO
)-(tuptuO)-(2AreifilpmA
81A
NI
)-(tupnI)-(1AreifilpmA
)2(
22I
2TES
)-/+(2AreifilpmA
tsujdAtnerruC
91A
TUO
)-(tuptuO)-(1AreifilpmA322gVlortnoC)-/+(2AreifilpmA
01TTA
NI
)-(tupnI)-(rotaunettA
)2(
422A
TUO
)+(tuptuO)+(2AreifilpmA
11V
SOMC
latigiDroFylppuS
tiucriCSOMC 522A
NI
)+(tupnI)+(2AreifilpmA
)2(
21KLCkcolC62TTA
TUO
)+(tuptuO)+(rotaunettA
)2(
31TADataD72C/NnoitcennoCoN
)1(
41nEelbanE82DNGdnuorG
Notes:
(1) All N/C pins should be grounded.
(2) Pins should be AC-coupled. No external DC bias should be applied.
4PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
ELECTRICAL CHARACTERISTICS
RETEMARAP NIM XAM TINU
)42,12,9,4,2snip(ylppuSgolanA09CDV
V:ylppuSlatigiD CMOS )11nip(06CDV
)32,6snip(2gV,1gVslortnoCreifilpmA5-2V
FR
stupnItarewoP
snip(
8,5
)
-06+VmBd
)41,31,21snip(ecafretnIlatigiD5.0-V
CMOS 5.0+V
erutarepmeTegarotS55-002+
0
C
erutarepmeTgniredloS-062
0
C
emiTgniredloS-5ceS
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
RETEMARAP NIM PYT XAM TINU
V:ylppuSreifilpmA DD )42,12,9,4snip(5.457 CDV
V:ylppuSrotaunettA ATTN )2nip(VDD 5.0-57 CDV
V:ylppuSlatigiD CMOS )11nip(0.3-5.5CDV
ecafretnIlatigiD0-VCMOS V
)32,6snip(2gV,1gVslortnoCreifilpmA5-12V
erutarepmeTesaC04-5258
0
C
Stresses in excess of the absolute ratings may cause permanent damage. Functional
operation is not implied under these conditions. Exposure to absolute ratings for
extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
Notes:
1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be
applied.
2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC
bias should be applied.
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
5
ARA2004
RETEMARAP NIM PYT XAM TINU STNEMMOC
)9,4snip(tnerruC1AreifilpmA -
-
84
4.2
08
6Am delbanexT
delbasidxT
)42,12snip(tnerruC2AreifilpmA -
-
77
7.3
021
9Am delbanexT
delbasidxT
)2nip(tnerruCrotaunettA-951Am
noitpmusnoCrewoPlatoT -
-
76.0
57
80.1
051
W
Wm
delbanexT
delbasidxT
Note: As measured in ANADIGICS test fixture
Table 4: DC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
RETEMARAP NIM PYT XAM TINU STNEMMOC
)zHM01(niaG5.723.925.03BdgnittesnoitaunettaBd0
ssentalFniaG -
-
57.0
5.1
-
-Bd zHM24ot5
zHM56ot5
erutarepmeTrevonoitairaVniaG-600.0--C°/Bd
Bd1spetSnoitaunettA
Bd2
Bd4
Bd8
Bd61
Bd23
56.0
6.1
6.3
5.7
0.51
2.03
38.0
07.1
57.3
57.7
04.51
57.03
00.1
50.2
0.4
0.8
8.51
3.13
BdcinotonoM
noitaunettAmumixaM6.853.06-Bd
2
dn
leveLnoitrotsiDcinomraH
)zHM01( -57-35-cBdsmhO57otniVmBd06+
3
dr
leveLnoitrotsiDcinomraH
)zHM01( -06-35-cBdsmhO57otniVmBd06+
3
dr
tpecretnItuptuOredrO87-- VmBd
tnioPnoisserpmoCniaGBd1-5.86- VmBd
erugiFesioN-0.30.4BdssolnulabtupnisedulcnI
Table 5: AC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
6PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
RETEMARAP NIM PYT XAM TINU STNEMMOC
rewoPesioNtuptuO
.teS.nettA.niM/langiSoN/evitcA
.teS.nettA.xaM/langiSoN/evitcA
-
-
-
-
5.83-
8.35-
VmBdhtdiwdnabzHk061ynA
zHM24ot5morf
edomelbasidxTni)zHM54(noitalosI-56-Bd
tuptuoniecnereffiD
xTneewteblangis
elbasidxTdnaelbane
ecnadepmItupnIlaitnereffiD-003- smhO 8dna5snipneewteb
)delbanexT(
ecnadepmItupnI-57- smhO remrofsnarthtiw
)delbanexT(
ssoLnruteRtupnI
)ecnadepmicitsiretcarahcmhO57(
-
-
02-
5-
21-
-Bd delbanexT
delbasidxT
ecnadepmItuptuOlaitnereffiD-003- smhO42dna12snipneewteb
ecnadepmItuptuO-57- smhOremrofsnarthtiw
ssoLnruteRtuptuO
)ecnadepmicitsiretcarahcmhO57(
-
-
71-
51-
21-
01- Bd delbanexT
delbasidxT
tneisnarTegatloVtuptuO
elbasidxT/elbanexT
-
-
-
4
001
7p-pVm gnittesrotaunettaBd0
gnittesrotaunettaBd42
Note: As measured in ANADIGICS test fixture
continued: AC Electrical Specifications
TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
7
ARA2004
Figure 4: Test Circuit
227
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
GND
I
SET1
Vg1
A1
IN
(+)
A1
OUT
(+)
ATT
IN
(+)
V
ATTN
V
CMOS
CLK
DAT
En N/C
A2
OUT
(-)
I
SET2
A2
IN
(-)
Vg2
ATT
OUT
(-)
GND
CMOS
A2
IN
(+)
A2
OUT
(+)
N/C
N/C
N/C
GND
A1
IN
(-)
A1
OUT
(-)
ATT
IN
(-)
ATT
OUT
(+)
(75 Ohms)
470pF
470pF
1K Ohms
470pF
2K Ohms
Turns
Ratio
2:1 1500pF RF Output
(75 Ohms)
0 / +3 V
Control A2 +5 V
1uF
0.1uF
3.9 Ohms
Clock
Enable
Data
+5 V
1000pF
1000pF
1.2K Ohms
RF Input
0 / +3 V
Control A1 +5 V
1.2K Ohms 1000pF
1000pF
1uF
0.1uF
1K Ohms
470pF
2K Ohms
ARA2004
10uH
10uH
1uF
0.1uF
+5 V
1uF
0.1uF
Note:
Tx Enable: Control A1 and Control A2 = +3V
Tx Disable: Control A1 and Control A2 = 0V
Toko Balun
616PT-1030
2K Ohms
2K Ohms
Turns
Ratio
1:2
8PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
PERFORMANCE DATA
Figure 5: Attenuation Level vs Control Word
Figure 6: Gain & Noise Figure vs Frequency
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
0 4 8 1216202428323640444852566064
Control Word
Attenuation (dB)
Figure 7: Gain & Noise Figure vs VDD
5
10
15
20
25
30
35
10 30 50 70 90
Frequency (M Hz)
Gain (dB)
2
3
4
5
6
7
8
NF (dB)
Gain Noise Figure
20
23
26
29
32
35
34567
VDD ( Volts )
GAIN (dB)
1
2
3
4
5
6
NF (dB)
Gain Noise Figure
Measured @ 30 MHz
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
9
ARA2004
Figure 8: Gain & Noise Figure vs Temperature
Figure 9: Harmonic Distortion vs VDD
POUT = 58dBmV
Figure 10: Harmonic Distortion vs VDD
POUT = 58dBmV
-80
-70
-60
-50
-40
-30
-20
34567
VDD ( Volts )
Harmonic Level (dBc)
2nd Harm onic 3rd Harmonic
Measured @ 5 MHz
-80
-70
-60
-50
-40
-30
-20
34567
VDD ( Volts )
Harmonic Level (dB c)
2nd Harmonic 3rd Harmonic
Measured @ 12 MHz
20
23
26
29
32
35
-40 -25 -10 5 20 35 50 65 80
Temperature (Co)
GAIN (dB)
1
2
3
4
5
6
NF (dB)
Gain Noise Figure
Measured @ 30 MHz
10 PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
Figure 11: Harmonic Distortion vs Temperature
POUT = 58dBmV
Figure 12: Harmonic Distortion vs Power Out
-80
-75
-70
-65
-60
-55
-50
-45
-40
-40 -25 -10 5 20 35 50 65 80
Temperature (Co)
Harmonic level (dBc)
2nd Harmonic 3rd Ha rm on ic
Meas ured @ 5 MHz
Figure 13: Transients vs Attenuation
POUT = 55dBmV at 0dB attenuation
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
49 51 53 55 57 59 61 63 65 67
Pout (dBmV)
Harmonics (dBc)
2nd 3rd
0
10
20
30
40
50
60
70
80
90
100
0 102030405060
Power Attenuati o n (dB )
Transient (mV)
DOCSIS 1.1 Spec. ARA2001
ARA2004
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
11
ARA2004
Figure 14: Harmonic Performance over
Frequency POUT = +62dBmV
Figure 15: IIP2 & IIP3 vs Frequency
Figure 16: IIP2 & IIP3 vs VDD
20
24
28
32
36
40
5 152535455565758595
Frequency (MHz)
IIP
2
(dBm)
4
6
8
10
12
14
IIP
3
(dBm)
IIP2 IIP3
Measured @ VDD = 5 Volts
Pin = -20 dBm per tone
20
24
28
32
36
40
34567
VDD (Volts)
IIP
2
(dBm)
-5
-1
3
7
11
15
IIP
3
(dBm)
IIP2 IIP3
Measured @ 65 MHz
Two tones @ 29.5 MHz
-72
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
0 5 10 15 20 25 30 35 40
Frequency (MHz)
Harmonic Level (dBc)
2nd Harmonic 3rd Harmonic
12 PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
DATA
CLOCK
ENABLE
ENABLE
OR
D
7
: MSB D
6
D
4
D
3
D
1
D
0
: LSB
Table 6: Programming Word
TIBATAD D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
eulaV 7P6P5P4P3P2P1P0P
LOGIC PROGRAMMING
Table 7: Data Description
Figure 17: Serial Data Input Timing
EULAV NOITCNUF
)ssapyb=0,no=1(
7PA/N
6PA/N
5PtiBrotaunettABd23
4PtiBrotaunettABd61
3PtiBrotaunettABd8
2PtiBrotaunettABd4
1PtiBrotaunettABd2
0PtiBrotaunettABd1
Programming Instructions
The programming word is set through an 8 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the
data entry, then set high to latch the shift register.
The rising edge of the clock pulse shifts each data
value into the register.
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
13
ARA2004
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2004 includes two amplification stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 6 and 23, respectively.) By
applying a slightly positive bias of typically +1.0 Volts,
the amplifier is enabled. In order to disable the
amplifier, the control pin needs to be pulled to
ground.
A practical way to implement the necessary control
is to use bias resistor networks similar to those
shown in the test circuit schematic (Figure 4.) Each
network includes a resistor shunted to ground that
serves as a pull-down to disable the amplifier when
no control voltage is applied. When a positive voltage
is applied, the network acts as a voltage divider that
presents the required +1.0 Volts to enable the
amplifier. By selecting different resistor values for
the voltage divider, the network can accommodate
different control voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplifier Bias Current
The ISET pins (7 and 22) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Thermal Layout Considerations
The device package for the ARA2004 features an
exposed paddle on the bottom of the package body.
Use of the paddle is an integral part of the device
design. Soldering this paddle to the ground plane of
the PC board will ensure the lowest possible thermal
resistance for the device, and will result in the longest
MTF (mean time to failure.)
A PC board layout that optimizes the benefits of the
paddle is shown in Figure 18. The via holes located
under the body of the device must be plated through
to a ground plane layer of metal, in order to provide a
sufficient heat sink. The recommended solder mask
outline is shown in Figure 19.
Figure 18: PC Board Layout
14 PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
Figure 19: Solder Mask Outline
Output Transformer
Matching the output of the ARA2004 to a 75 Ohm
load is accomplished using a 2:1 turns ratio
transformer. In addition to providing an impedance
transformation, this transformer provides the bias to
the output amplifier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the amplifiers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF
and DC power requirements without saturating the
core, and it must have adequate isolation and good
phase and amplitude balance. It also must operate
over the desired frequency and temperature range
for the intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Although the
ARA2004 has some built-in ESD protection, proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
15
ARA2004
NOTE
1. PACKAGE BODY SIZ ES EXCLUDE MOLD FLASH AND
GATE BURRS
2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED
3. CONTROLLING DIMENSION ARE INCHES.
4. REF. - MO-137
A1
y
θ
D
e
L
E
H
b
C
A2
SYMBOLS
A0.0040.000
0.025
0.150
0°
−−−
0.016
0.228
0.386
0.007
0.008
0.004
8°
0.394
0.050
0.157
0.244
0.012
0.010
DIMEN SIONS IN INCHES
0.057
MIN MAX
0.061
θ
S
T0.096
0.190
−−−
−−−
0.100.00
.64
3.81
0°
−−−
0.40
5.80
9.80
0.18
0.20
0.10
8°
10.00
1.27
4.00
6.20
0.30
0.25
DIM EN SION S IN MILLIMETERS
1.45
MIN MAX
1.55
2.43
4.82
−−−
−−−
0.057 1.45
Figure 20: S23 Package Outline - 28 Pin SSOP with Exposed Paddle
PACKAGE OUTLINE
16 PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
COMPONENT PACKAGING
Figure 22: Tape Dimensions
Volume quantities of the ARA2004 are supplied on
tape and reel. Each reel holds 3,500 pieces. Smaller
quantities are available in plastic tubes of 50 pieces.
Figure 21: Reel Dimensions
DIRECTION OF FEED
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
17
ARA2004
NOTES
18 PRELIMINARY DATA SHEET - Rev 1.0
07-2001
ARA2004
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
19
ARA2004
NOTES
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
PRELIMINARY DATA SHEET - Rev 1.0
07-2001
20
ARA2004
REBMUNREDRO ERUTAREPMET
EGNAR
EGAKCAP
NOITPIRCSED GNIGAKCAPTNENOPMOC
1P32S4002ARA58ot04-
0
ChtiwPOSSniP82
elddaPdesopxE leerdnaepateceip005,3
0P32S4002ARA58ot04-
0
ChtiwPOSSniP82
elddaPdesopxE )ebutrepseceip05(sebutcitsalP
ORDERING INFORMATION
