intel. 809XBH/839XBH/879XBH ADVANCED 16-BIT MICROCONTROLLER WITH 8- OR 16-BIT EXTERNAL BUS Automotive gw Extended Automotive Temperature mw High-Speed i/O Subsystem Range ( 40C to + 125C Case) = Full Duplex Serial Port = High Performance NMOS Process u Dedicated Baud Rate Generator m 8 Kbytes On-Chip ROM/EPROM m 6.25 1s 16 x 16 Multiply mw 232 Byte Register RAM m 6.25 ps 32/16 Divide uw Register-to-Register Architecture m 16-Bit Watchdog Timer @ 10-Bit A/D Converter with S/H w Four 16-Bit Software Timers m Five 6-Bit 1/0 Ports = Two 16-Bit Counters/Timers @ 20 Interrupt Sources @ Available in 68-Pin PLCC, PFP and CFP: m 8-Bit Pulse-Width Modulated Output 48-Pin PDIP Package gw Run-Time Programmable EPROM (See Packaging Specifications, Order # 231369) w Full Duplex Serial Port The 8X9XBH family of 16-bit microcontrollers consists of many members, all of which are designed for high- speed control functions. The 8X9XBH family members produced for the automotive environment, using Intels HMOS-ii! process, with 8 Kbytes of ROM (or ROMless) and 232 total bytes of on-chip RAM, 256 bytes of register RAM are described in this datasheet. The CPU supports bit, byte, and word operations. Thirty-two-bit double words are supported for a subset of the instruction set. With a 12 MHz input frequency the 8X9XBH can do a 16-bit addition in 1.0 ws and a 16 x 16-bit multiply or 32/16 divide in 6.25 ys. Instruction execution times average 1 us to 2 ps in typical applications. Four high-speed capture inputs are provided to record the times at which external events occur stored in an eight-level FIFO. Rising, falling, rising and falling, or every eight rising edges can be recorded every 2.25 us using 12 MHz clock. Interrupts can be programmed for every FIFO entry, or every 6th FIFO entry. Up to 6 high-speed pulse generator outputs are provided to trigger external events at preset times. The high- speed output unit can simultaneously perform software timer functions, start A/D conversions, or pulse one or more outputs. Up to four 16-bit software timers can be in operation at once. The on-chip A/D converter includes a Sample and Hold (S/H), and converts up to 8 multiplexed analog input channels to a 10-bit digital result. With a 12 MHz input frequency, each conversion takes as little as 22 ws. A/D conversions can be performed at preprogrammed times, or asynchronously. Also provided on-chip are: a full duplex, double buffered receive serial port with 3 asynchronous and 1 synchronous modes; a 16-bit watchdog timer, and a 256 state pulse-width modulated output signal. NOTICE: This datasheet contains information on products in full production. Specifications within this datasheet are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. January 1995 6-2 Order Number: 27036 1-006AUTOMOTIVE 809XBH/839XBH/879XBH POWER FREQUENCY Veer ANGND DOWN REFERENCE pf ee be ee ee eee ww be ween enn anewes @ KBYTE \ ON~CHIP 1 clock i a ' CEN ; ROM/EPROM ' " t A/D - 7 t t ' 1 | CONVERTER rb mewabunnnnnfenns oN 1 ,! . 1 yy cpu v a CONTROL 1 } 1 CONTROLLER ' ' 232 ' plourue SIGNALS 1 ys/H ' BYTE REGISTER | ! 7 1 WATCHDOG | REGISTER ALU | a LTIMERS t ' ee FILE E | TIMERZ 16 t PORT 3 tp ux Thaw ne fine Foes 1 y vy i6, ADDR 1 a war DATA \ v Yy BUS I PULSE BAUD t t i WIDTH SERIAL bat RATE 1 PORT 4 ' oD PORT GEN HIGH ' i : . SPEED i 1 \/0 ' t 1 ' 1 t t t ' a ' baawae om os) meme nwaee eA PORTO PORT 1 PORT 2 HSI HSO ALT FUNCTIONS 270361-1 Figure 1. MCS 96 Microcontroller Block Diagram PRODUCT/PACKAGING OPTIONS The 8X9XBH is available in 48 and 68-pin packages, with and without on-chip ROM or EPROM. The 8X9XBH nomenclature is shown in Figure 2. Figures 3, 4 and 6 show the pinouts for all available 68-piri packages: Plastic Leaded Chip Carrier (PLCC), Plas- tic Flatpack (PFP) and Ceramic Flatpack (CFP). Fig- ure 5 shows the pinout for the 48-pin Plastic Dip Package (PDIP). The 8X9XBH is also available in three temperature range options: Commercial (0C to + 70C), Extend- ed ( 40C to + 85C) and Automotive ( 40C to +125C). Intel's extended and automotive temper- ature range products are designed to meet the needs of those applications whose operating re- quirements exceed commercial standards. The automotive, extended, and commercial temper- ature versions of the 8X9XBH product families are available with or without burn-in options as listed in Table 1. As shown in Figure 2, temperature, burn-in and package options are indentified by a one- or two-let- ter prefix to the part number. it also illustrates the 8X9XBH family nomenclature for ROM/EPROM/ ROMless, with/without A/D, and process. 6-3a AUTOMOTIVE 809XBH/839XBH/879XBH intel A N 83 97 BH L. PROCESS HMOS Ill PIN COUNT: 5 = 48-PIN 7 = 68~-PIN PROGRAM MEMORY OPTION: 0 =ROMLESS 3 = ROM 7 = EPROM PACKAGE TYPE OPTION: SEE TABLE 2, COLUMN S Q= HERMETIC, QUAD FLATPACK N= PLASTIC, LEADED CHIP CARRIER (PLCC) P= PLASTIC, FLATPACK - 68-PIN P= PLASTIC, DIP - 48-PIN TEMPERATURE, BURN - IN OPTION: SEE TABLE 1 270961-13 Figure 2. The 8X9XBH Family Nomenclature Table 1. Temperature Burn-in Option Temperature Temperature Operating Burn-in Classification Designation Temperature 128C (Hr) Commercial Null 0C to + 70C Ambient 6 Extended T 40C to + 85C Ambient 6 Automotive A 40C to + 125C Case 6 H 40C to + 125C Case 6 NOTES: 1. Burn-in is dynamic at + 125C, Vocg = 7.3V 0.25V, for 6 hours. 2. Other burn-in durations are also available, but not standard. Table 2. The 8X9XBH Family Packages ROMIess 68-Pin N8097BH-PLCCG 68-Pin P8097BH-PFP 48-Pin P8095B8H-P-DIP ROM 68-Pin N8397BH-PLCC (8 Kbytes) 68-Pin P8397BH-PFP 48-Pin P8395BH-P-DIP EPROM 68-Pin Q8797BH-CFP (8 Kbytes) 48-Pin C8795BH-DIPintel. AUTOMOTIVE 809XBH/839XBH/879XBH PFP/cFR ORD Otro Description | PFP/CFP FTP SYP Description 1 41 9 ACH7/P0.7 35 16 43 READY 2 40 8 ACH6/P0.6 36 _ 42 T2RST/P2.4 3 _ 7 ACH2/P0.2 37 15 41 BHE/WRH 4 6 ACHO/P0.0 38 14 40 WR/WRL 5 - 5 ACH1/P0.4 39 13 39 PWM/P2.5 6 4 ACH3/P0.3 40 _ 38 P2.7/T2CAPTURE 7 3 NMI 41 12 37 Vpp 8 39 2 EA 42 1 36 Vss 9 38 1 Voc 43 10 35 HSO.3 10 37 68 Vss 44 9 34 HSO.2 11 36 67 XTAL1 45 _ 33 P2.6 12 35 66 XTAL2 46 _ 32 P17 13 65 CLKOUT 47 31 P1.6 14 64 BUSWIDTH 48 30 P15 15 63 INST 49 8 29 HSO.1 16 34 62 ALE/ADV 50 7 28 HSO.0 17 33 61 RD 51 6 27 HSO.5/HSI.3 18 32 60 ADO/P3.0 52 5 26 HSO.4/HSI.2 19 31 59 AD1/P3.1 53 4 25 HSI.4 20 30 58 AD2/P3.2 54 3 24 HSI.0 21 29 57 AD3/P3.3 55 _ 23 P1.4 22 28 56 AD4/P3.4 56 22 P1.3 23 27 55 ADS/P3.5 57 _ 21 P1.2 24 26 54 AD6/P3.6 58 _ 20 P14 25 25 53 AD7/P3.7 59 _ 19 P1.0 26 24 52 AD8/P4.0 60 2 18 TXD/P2.0 27 23 54 AD9/P4.1 61 1 17 RXD/P2.1 28 22 50 AD10/P4.2 62 48 16 RESET 29 21 49 AD11/P4.3 63 47 15 EXTINT/P2.2 30 20 48 AD12/P4.4 64 46 14 Vpp 31 19 47 AD13/P4.5 65 45 13 VREF 32 18 46 AD14/P4.6 66 44 12 ANGNO 33 17 45 AD15/P4.7 67 43 11 ACH4/P0.4 34 44 T2CLK/P2.3 68 42 10 ACH5/P0.5 Figure 3, PFP/CFP, P-DIP and PLCC Functlonal PinoutsAUTOMOTIVE 809XBH/839XBH/879XBH neaneorn ggeceee -& [3 MS SS OR ORS -~ Dz a SiS fe2s, enti 8's 22L2e2e27218 OK eka wz 212 HOODOO Oo oo oo 987 6 5 4 3 2 1 68 67 66 65 64 63 62 61 acHS/Po.5 [10 a 60[-) abo/P3.0 ACH4/PO.4 [11 59 Doves ANGND (J 12 581) aD2/P3.2 VREF 4 13 571 aD3/P3.3 Ypp Cy 14 S61} AD4/P3.4 EXTINT/P2.2 EJ 15 68-PIN 5510) aps /P3.5 RESET CJ 16 PLCC 5410 aD6/P3.6 RxO/P2.1 C917 8395 aD7/P3.7 TXD/P2.0 [J 18 52 (7) aps /P4.o P1LOf} 139 TOP VIEW S115 Abg/P4.1 P1.1 920 LOOKING DOWN ON 500] Ab10/P4.2 P1.2(}21 COMPONENT SIDE 4915 a11/P4.3 P1.3 1] 22 4810) a012/P4.4 e140) 23 OF PC BOARD 47D a013/P4.5 HsI0 J 24 4607) AD14/P4.6 Hsii CJ 25 4590 ad15/P4.7 Hsiz /HS04 [J 26 440 F2cLK/P2.3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 coo ygogeg geo = > * . . wm . * gERes SEPP "seeds " zEje uo g zr & 270361-2 Figure 4. 68-Pin PLCC Package Pins Facing Down Rxo/P2.1 C91 480 RESET 1xp/P2.0 C2 4710 EXTINT/P2.2 HsIo [93 461 Vp Hsis C4 45 Veer HsI2/HSO4 [5 4415 ANGND HSi3/HSO5 [6 4390 acna/P0.4 Hsoo [7 4290) acHs/P0.5 Hso1 C13 41950 acu? /P0.7 Hso2 Cio 4077 acn6/P0.6 Hso3 Ch 10 39 EA VssC 11 yes 95 38 Yeo Vpp (912 48-PIN) 37D 55 pww/e2.s 13) OP sea xract Wal /wh C14 35 xtac2 wRA/BHE C15 34907 ALE/ADV READY CJ 16 3301 RD ab15/P4.7 C17 32 aba /P3.0 ania /P4.6 C18 B13 ADI /P3.4 ap13/P4.5 Cf i9 30 Doan Ad12/P4.4 C9 20 291 ad3/P3.3 api1/pP4.3 (J 21 28D aps/P3.4 AD10/P4.2 [22 2710 aD5/P3.5 aps/P4.1 Cy 23 261 AD6/P3.6 A08/P4.0 C4 24 2590) a7 /P3.7 270361-3 Figure 5. 48-Pin P-DIP Packagetel AUTOMOTIVE 809XBH/839XBH/879XBH ny @ oOo oOo a a ~ MN mn rx oo << ACH2 /PO.2 ACHO / P0.0 ACH1 /PO.1 ACH3 /PO.3 BUSWIDTH INST ALE / ADV NM EA Voc Vs XTAL1 XTAL2 CLKOUT RD 15 16 17 ACHS /PO.5 ADO / P3.0 ACH4 /PO.4 ADI /P3.1 ANGND AD2 /P3.2 Vrer AD3 /P3.3 Vpp AD4 /P3.4 EXTINT / P2.2 ADS /P3.5 68-PIN RESET ADG /P3.6 RXD /P2.1 FLAT PACK AD? /P3.7 TXD /P2.0 (TOP VIEW) ADB / P4.0 P1.0 59 COMPONENT SIDE 27 ADO /P4.1 Pia OF PC BOARD ADIO /P4.2 P12 ADI1 /P4.3 P13 ADI2 /P4.4 P1.4 ADI3 /P4.5 HSIO ADI4/P4.6 HSIt ADIS /P4.7 HSI2 /HS04 T2CLK / P2.3 42 41 40 39 38 37 36 35 SZgeternesgs senseerta BESTT NRSY> AHS Ss XQ Sjz > e& = |= lz 5 a = & = & 270361-5 Figure 6. 68-Pin Package (Fiat PackTop View) 6-7a AUTOMOTIVE 809XBH/839XBH/879XBH intel PIN DESCRIPTIONS Symbol Name and Function Voc Main supply voltage (5V). Vss Digital circuit ground (OV). There are two Vgsg pins, both of which must be connected. Vep RAM standby supply voltage (5V). This voltage must be present during normal operation. In a Power Down condition (i.e. Voc drops to zero), if RESET is activated before Vcc drops below spec and Vpp continues to be held within spec., the top 16 bytes in the Register File will retain their contents. RESET must be held low during the Power Down and should not be brought high until Vcc is within spec and the oscillator has stabilized. VREF Reference voltage for the A/D converter (5V). Vref is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as Vgs. Vpp Programming voltage for the EPROM parts. It should be + 12.75V for programming. This pin is Vpp on 8X9X-90 parts. Systems that have this pin connected to ANGND through a capacitance (required on 8X9X-90 parts) do not need to change. Otherwise, tie to Vcc. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is 4 the oscillator frequency. lt has a 33% duty cycle. RESET Reset input to the chip. Input low for at least 2 state times to reset the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state- time sequence in which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is executed. Input high for normal operation. RESET has an internal pullup. BUSWIDTH Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is high, a 16-bit bus cycle occurs. If BUSWIDTH is low, an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. This pinis the TEST pin on 8X9X-90 parts. Systems with TEST tied to Voc do not need to change. If this pin is left unconnected, it will rise to Voc. NMI A positive transition causes a vector to external memory location OOOOH. External memory from OOH through OF FH is reserved for Intel development systems. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses. Input for memory select (External Access). EA equal to a TTL-high causes memory __ accesses to jocations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory. EA = + 12.5V causes execution to begin in the Programming Mode. EA has an internal pulldown, so it goes low unless driven otherwise. EA is latched at reset. 6-8intel. AUTOMOTIVE 809XBH/839XBH/879XBH PIN DESCRIPTIONS (Continued) Symbol Name and Function ALE/ADV Address Latch Enabie or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for external memory. ALE/ADV is activated only during external memory accesses. Read signal output to external memory. RD is activated only during external memory reads. Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. Bus High Enable or Write High output to external memory, as selected by the CCR. BHE low selects the bank of memory that is connected to the high byte of the data bus. AO low selects the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 low, BHE high), to the high byte only (AO high, BHE low), or both bytes (AO low, BHE low). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is activated only during external memory writes. READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next positive transition in CLKOUT occurs with READY high. The bus cycle can be lengthened by up to 1 ws. When the external memory is not being used, READY has no effect. Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR. READY has a weak internal pullup, so it goes high unless externally pulled low. HS! Inputs to High Speed Input Unit. Four HSI pins are available: HS!.0, HSI.1, HSI.2 and HSI1.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HS! pins are also used as inputs by EPROM parts in Programming Mode. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also a mode input to EPROM parts in the Programming Mode. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. Six of its pins are shared with other functions, the remaining 2 are quasi-bidirectional. These pins are also used to input and output control signals on EPROM parts in Programming Mode. Ports 3 and 4 8-bit bidirectional |/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are also used as a command, address and data path by EPROM parts operating in the Programming Mode.AUTOMOTIVE 809XBH/839XBH/879XBH Memory Map OFFH 255 POWER-DOWN RAM OFOH 240 OFFH INTERNAL 239 REGISTER FILE (RAM) 1AH 26 FFFFH 19H TY stack POINTER STACK POINTER 28 18H 24 EXTERNAL MEMORY OR 1/0 17H PWM_CONTROL 23 16H | 10s1 ioc 22 4000H 15H | oso loco 21 INTERNAL PROGRAM 14H 20 STORAGE ROM/EPROM 13H | RESERVED RESERVED 9 EXTERNAL MEMORY 2080H 12H 18 RESERVED 2030H 207FH 11H | SP_STAT SP_CON 17 SECURITY KEY 2020H ~ 202FH 10H } 10 PORT 2 10 PORT 2 16 OFH | 10 PORT 1 10 PORT 1 15 201CH= 201FH SELF JUMP OPCOOE (27H FEH) 201AH 2018H OEH | 10 PORTO BAUD_RATE 14 RESERVED 2019H OOH | TIMER2 (HI 13 ERZ (HI) CHIP CONFIGURATION BYTE 2018H OCH | TIMER2 (LO) RESERVED 12 RESERVED 2012H = 2017H OBH | TIMER! (Hi) W1 t 1 OAH | TIMER? (0) WATCHDOG 10 INTERRUPT VECTORS OSH ] INT_PENDING INT_PENDING 9 08H | INT_MASK INT_MASK 8 2000H 07H | SBUF (RX) SBUF (TX) 7 PORT 4 1FFH 06H | HSI_STATUS HSO_COMMAND 6 PORT 3 1 FFEH OSH | HSI_TIME (HI) HSO_TIME (HI) 5 EXTERNAL MEMORY 4H | HSI_TIME (LO) HSO_TIME (LO) 4 OR 1/0 91008 03H | AD_RESULT (HI) HSI_MODE 3 INTERNAL RAM OOFFH 02H | AD_RESULT (LO) AD_COMMAND 2 REGISTER FILE STACK POINTER O1H Ff RO (HI) RO (HI) 1 SPECIAL FUNCTION REGISTERS oon | Ro (Lo) RO (10) 0 (WHEN ACCESSED AS DATA MEMORY) o000H (WHEN READ) (WHEN WRITTEN) 270361-17intel. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS** Case Temperature Under Bias... ~- 40C to + 125C Storage Temperature 60C to + 150C Voltage from Vpp to Vsg or ANGND 0.3V to + 13.0V Voltage from Any Other Pin to Vgs or ANGND ~0.3V to +7.0V** **NOTE: This includes Vpp on ROM and CPU devices. OPERATING CONDITIONS AUTOMOTIVE 809XBH/839XBH/879XBH NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Symbol Parameter Min Max Units To Case Temperature Under Bias 40 +125 C Voc Digital Supply Voltage 4.50 5.50 Vv VREF Analog Supply Voltage 4.50 5.50 Vv Fosc Oscillator Frequency 6.0 12.0 MHz Vep Power Down Supply Voltage 4.50 5.50 Vv NOTE: ANGND and Vss should be nominally at the same potential. DC CHARACTERISTICS Test Conditions: Voc, Vrer. Vp, Vpp. Vgg = 5.0V 0.5V; Fosc = 6.0 MHz to 12.0 MHz; Tc = 40C to + 125C; Vgs, ANGND = OV Symbol Parameter Min Max |Units/ Test Conditions loc Voc Supply Current ( 40C < + 125C Case) 240 mA |All Outputs icc: [Voc Supply Current (To = + 125C) 155 | ma [Disconnected Ipp Vpp Supply Current 1 mA |Normal Operation and Power Down IREF Vrer Supply Current 10 mA Vie Input Low Voltage (Except RESET) -0.3] +08 V Vid Input Low Voltage, RESET -0.3] +08 V Vin input High Voltage (Except RESET, NMI, XTAL1) 2.0 |Vcc + 0.5] V Vind Input High Voltage, RESET Rising 24 IVoo + 0.5] V Ving [input High Voltage, RESET Falling Hysteresis 21 |Voco + 0.5] V Ving Input High Voltage, NMI, XTAL1 2.3 |Voc + 0.5] V tol Input Leakage Current, All HSI, P3, P4 and P2.1. +10 BA |Vin = 0 to Voc Ihit DC Input Leakage Current, All PO +3 BA |Vin = Oto Voc lin input High Current to EA 100 BA |Vin = 2.4V fic Input Low Current, All P1, P2.6 and P2.7. ~150 pA {Vit = 0.45V hict Input Low Current to RESET -0.25} -2 MA IVi_ = 0.45V lite Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH 50 pA |Vi_ = 0.45V VoL Output Low Voltage, 0.45 Ve ilot = 0.8mA All Quasi-Bidirectional |/O, P3, P4 (Note 1) 6-11a AUTOMOTIVE 809XBH/839XBH/879XBH intel , DC CHARACTERISTICS Test Conditions: Vcc, Vrer. Vep. Vpp. Vss = 5.0V +0.5V; Fosc = 6.0 MHz to 12.0 MHz: Tc = 40C to + 125C; Vsg, ANGND = OV (Continued) Symbol Parameter Min Max | Units Test Conditions Voi Output Low Voltage, 0.75 v lo. = 2.0mA All Quasi-Bidirectional |/O, P3, P4 (Notes 1, 2, 3) VoL2 Output Low Voltage on Standard !/O 0.45 Vv lo. = 2.0mA Bus, Control Pins (Notes 2, 3) VoH Output High Voltage on 2.4 Vv lon = 20 pA Quasi-Bidirectional 1/O (Note 1) Vout Output High Voltage on Standard |/O 2.4 Vv lou = 200 pA Bus, Control Pins (Note 1) lona Output High Current on RESET ~50 pA Vou = 2.4V (Note 4) Cs Pin Capacitance (Any Pin to Vss) 10 pF Frest = 1.0 MHz (Note 4) NOTES: 1. Quasi-bidirectional pins include those on P1, P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only), PWM, and HSO pins. Bus/Controt pins include CLKOUT, ALE, BHE, AD, WR, INST and ADO-15. 2. Maximum current per pin must be externally limited to the following values if Vo, is held above 0.45V. lo, on quasi-bidirectional pins: 4.0 mA lo on standard output pins and RESET: 8.0 mA lo. on Bus/Control pins: 2.0 mA lo: on HSO.0, HSO.4, HSO.5 = 1.6 mA: @ Vo. =0.5V 3. During normal (non-transient) operation the following limits apply: Total lo, on Port 1 must not exceed 4.0 mA. Total Iq, on P2.0, P2.6, RESET and all HSO pins must not exceed 17.0 mA. Total Io, on P2.5, P2.? must not exceed 4.0 mA. 4. These values are not tested in production, and are based on theoretical estimates and/or laboratory tests. AC CHARACTERISTICS Voc: Vpp = 5.0V +0.5V; To = 40C to + 125C; Fogo = 6.0 MHz to 12.0 MHz Test Conditions: Load Capacitance on Output Pins = 80 pF Oscillator Frequency = 12 MHz TIMING REQUIREMENTS (Other system components must meet these specifications) Symbol Parameter Min Max Units Toryx READY Hold after CLKOUT Edge 0 ns TiLyy End of ALE/ADV to READY Valid 2Tosc 70 ns TLLYH End of ALE/ADV to READY High 2Tosc + 40 4Tosc 80 ns TYLYH Non-Ready Time 1000 ns Tayoyl) Address Valid to Input Data Valid 5 Tosc 120 ns TRLov RD Active to Input Data Valid 3 Tosc 100 ns Trupx Data Hold after RD Inactive 0 ns TrRHpz RD Inactive to input Data Float 0 Tosc ~ 25 ns Taygv) Address Valid to BUSWIDTH Valid 2Tosc 125 ns TLLGX BUSWIDTH Hold after ALE/ADV Low Tosc + 40 ns TLLev ALE/ADV Low to BUSWIDTH Valid Tose 95 ns NOTE: 1. The term Address Valid applies to ADO-AD15, BHE and INST. 6-12 |AUTOMOTIVE 809XBH/839XBH/879XBH intel. AC CHARACTERISTICS (Continued) TIMING RESPONSES (MCS 96 parts meet these specifications) Symbol Parameter Min Max Units FxTac Oscillator Frequency 6.0 12.0 MHz Tosc Oscillator Period 83 166 ns TOHCH XTAL1 Rising Edge to Clockout Rising Edge 0 120 ns TCHCH CLKOUT Period(1) 3 Toso) 3 Tosco?) ns TCHCL CLKOUT High Time Tosc 35 Tosc + 10 ns Tou CLKOUT Low to ALE High 30 15 ns TLUCH ALE/ADV Low to CLKOUT High Tosc 25 Tosc + 45 ns TLHLL ALE/ADV High Time Tosc 30 Tosc + 35(2) ns TaviL@) | Address Setup to End of ALE/ADV Tosc 50 ns Trtaz(4) | RD or WR Low to Address Float 4005) ns TLERL End of ALE/ADV to RD or WR Active Tosc 40 ns TLLAX Address Hold after End of ALE/ADV Tosc 40 ns TWLWH WR Pulse Width 3 Tosc 35 ns Tovwu Output Data Valid to End of WR/WRL/WAH 3 Tosc 60 ns TwHox Output Data Hold after WR/WAL/WRH Tosc 50 ns TWHLH End of WR/WAL/WBH to ALE/ADV High Tosc 75 ns TRLRH RD Pulse Width 3 Tosc 30 ns TRHLH End of RD to ALE/ADV High Tosc 45 ns Tou CLOCKOUT Low to ALE/ADV Low Tosc 400) | Togo + 350) ns TRHBX RD High to INST, BHE, ADO-15 Inactive Tosc 25 Tosc + 30 ns TwHex WR High to INST, BHE, ADO-15 Inactive Tosc 50 Tosc + 100 ns 6 | THLHH WRL, WRH Low to WAL, WAH High 2Tosc 35 2Tosc + 40 ns TLL ALE/ADV Low to WAL, WRH Low 2Tosc 30 2Tosc + 55 ns TavHL Output Data Valid to WRL, WRH Low Tosc 60 ns NOTES: 1. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3 Tosc + 10 ns if Tosc is constant and the rise and fall times on XTAL1 are less than 10 ns. __ 2. Max spec applies only to ALE. Min spec applies to both ALE and ADV. 3. The term Address in this definition applies to ADO-15, BHE and INST. 4. The term Address in this definition applies to ADO-? for 8-bit cycles, and ADO-15 for 16-bit cycles. 5. Typical values. 6-13a AUTOMOTIVE 809XBH/839XBH/879XBH intel WAVEFORM Toncn-+l ke be-Tosc-| + Toc CLOCKOUT S beToHeL--} Top Touyx READY YALL! (3) Totty pray TYLYH eS T ALE, ADV LLYH TLHLL TL URL Te LRH RD \ T a re ee be Tavir | LLAX el Tai ay RLDV 7 .. AD ADDR OUT DATA IN f Sih TRUAZ | + spresetcceee AVDV. WHLH _ abt =f THU WR, WRL, WRH PTAveL (2), 7 a rTLLRL > TwHax AD ADDR OUT DATA OUT . em menmene T TLiax Tovw | Tenax, BHE, INST VALID eww ewww ew enwes Tau! |} wiws +lTynes| 1 AD8-15 ih VALID 270361-7 NOTES: 1. 8-bit bus only. 2. When write strobe mode selected. 3. When ADV selected. WAVEFORMBUSWIDTH PIN CLKOUT / \ / \ / \ Tavev BUSWIDTH VALID ALE / ADV Titex TAVEL ADDRESS / DATA ADDR OUT DATA IN 270361 -8 6-14 |a intel AUTOMOTIVE 809XBH/839XBH/879XBH AC CHARACTERISTICSSERIAL PORTSHIFT REGISTER MODE SERIAL PORT TIMINGSHIFT REGISTER MODE Test Conditions: Tc = 40C to + 125C; Voc = 5V +10%; Vsg = OV; Load Capacitance = 80 pF Symbol Parameter Min Max Units TXLXL Serial Port Clock Period 8 Tosc ns TXLXH Serial Port Clock Falling Edge to Rising Edge 4Tosc 50 4Tosc + 50 ns TavxH Output Data Setup to Clock Rising Edge 3 Tosc ns TxHax Output Data Hold After Clock Rising Edge 2 Tosc 70 ns TxXHOV Next Output Data Valid After Clock Rising Edge 2 Tosc + 50 ns TpvxH Input Data Setup to Clock Rising Edge 2 Tosc + 200 ns TxHDx Input Data Hold After Clock Rising Edge 0 ns TxHaz Last Clock Rising to Output Float 5 Tosc ns WAVEFORMSERIAL PORTSHIFT REGISTER MODE SERIAL PORT WAVEFORMSHIFT REGISTER MODE fe Tux >| Le Tovxu | | | Tun! Ie Trav > | b* Txnox Tyna2 > - ous XDD EKKO Tovxn >| fe >| [+ Txnox (IN) a DALI Xvarionk vari XvanioyX XvauioX XvaioX vaio Xvauio) 6 i 6-15AUTOMOTIVE 809XBH/839XBH/879XBH EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TotoL Oscillator Frequency 6 12 MHz ToHOX High Time 30 ns ToLox Low Time 30 ns TOLOH Rise Time 15 ns TOHOL Fall Time 16 ns EXTERNAL CLOCK DRIVE WAVEFORMS Tonox 2.5 25 270361-10 AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS 2.4 2.0 2.0 x te TEST POINTS <~ os x 270361-11 AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for a Logic 0". Timing measurements are made at 2.0V for a Logic 41 and 0.8V for a Logic O". 0.45 Vv, +0.20V Voy 0.20 LOAD POINTS VLoap ~9-20 Voy +0.20 270361-12 For timing purposes a port pin is no tonger floating when a 200 mV change from load voltage occurs, and begins to float when a 200 mV change from the loaded VoH/Vo, level occurs lo./lon 2 +8 mA. 6-16= intel AUTOMOTIVE 809XBH/839XBH/879XBH Power Supply Rise Time = 1 to 5 milliseconds 5.5Vp Start Time fram Power Supply Rise to External Output Low cux__ GCC PORTS 10 STATE TIMES PORT 3 & 4 ADDRESS HDATAH ADDRESS | WITH PULLUPS 2018H ccB 2080H _ L FIRST BUS FETCH CYCLE PROGRAM Tripy = 10XTAL CYCLES START External RESET Low to Port Valid Time RESET FUNCTION REGISTERS | TOTAL 8X9XBH RESET TIME 270361-31 Minimum Hardware Configuration Circuits Vpp Yep Yeo Yep asveap | YREF wm (S8.LEAD REF awonn DEVICES EA Anon DEVICES a a) Voc Veg! Voc 47 uF Yss2 47 uF Vs? at 0.01 pF uF 0.01 pF uF 12MHz = 270961 -32 = 270361 -33 6-17a AUTOMOTIVE 809XBH/839XBH/879XBH intel . A/D CONVERTER SPECIFICATIONS OPERATING CONDITIONS The absolute conversion accuracy is dependent on Voc. Vep: VREE + +e eee eee eee renee 5.0V +0.25V the accuracy of Vrer. The specifications given be- = gg, ANGND .......-.... 0-00. cce cence eee 0.0V low assume adherence to the Operating Conditions T ~40C to + 125C section of this datasheet. Testing is done at Vaer = Correerssr eee rce eters eacecnes 0 5.120V. La 0 Oe 6.0 to 12.0 MHz Test Conditions: =) = 5.120V NOC cece eee teen een ret eee ees 5.0V Parameter Typical*(1) Minimum Maximum Units** Notes Resolution 1024 1024 Levels 10 10 Bits Absolute Error 0 +4 LSBs Full Scale Error -0.5 +0.5 LSBs Zero Offset Error +05 LSBs Non-Linearity +4 LSBs Differential Non-Linearity 0 +2 LSBs Channel-to-Channel Matching 0 +1 LSBs Repeatability 0.25 0 LSBs 1 Temperature Coefficients: Offset 0.009 LSB/C 1 Full Scate 0.009 LSB/C 1 Differential Non-Linearity 0.009 LSB/C 1 Off Isolation 60 dB 1,2,4 Feedthrough 60 dB 1,2 Voc Power Supply Rejection 60 dB 1,2 Input Resistance 1K 5K 2 1 DC Input Leakage 0 3.0 pA Sample Delay 3 Tosc 50 3 Tosc + 50 ns 1,3 Sample Time 12 Tosc 50 12 Tosc + 50 ns 1 Sample Capacitance 2 pF NOTES: * These values are expected for most parts at 25C. ** An LSB, as used here, is defined in the glossary which follows and has a value ot approximately 5 mV. 1. These values are not tested in production and are based on theoretical estimates and laboratory tests. 2. DC to 100 KHz. 3. For starting the A/D with an HSO Command. 4, Multiplexer Break-Before-Make Guaranteed. 6-18 ia intel e AUTOMOTIVE 809XBH/839XBH/879XBH EPROM SPECIFICATIONS AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions: Load Capacitance = 150 pF, Tc = 25C, +5C, Vcc, Vpp, Vaer = 5.0V +0.5V, Vgs, ANGND = OV, Vpp = 12.75V +0.25V, EA = 11V +2.0V, Fosc = 6.0 MHz Symbol Parameter Min Max Units TALL ADDRESS/COMMAND Valid to PALE Low 0 Tosc TLLAX ADDRESS/COMMAND Hold After PALE Low 80 Tose TDvpL Output Data Setup Before PROG Low 0 Tosc TPLDX Data Hold After PROG Falling 80 Tosc TLL PALE Pulse Width 180 Tosc TPLPH PROG Pulse Width 250Tosc | 100 ps + 144 Tosc TLHPL PALE High to PROG Low 250 Tosc TPHLL PROG High to Next PALE Low 600 Tosc TPHDX Data Hold After PROG High 30 Tosc Tey PROG High to PVER/PDO Valid 500 Tosc TLUVH PALE Low to PVER/PDO High 100 Tosc TPLDV PROG Low to VERIFICATION/DUMP Data Valid 100 Tosc TSHLL RESET High to First PALE Low (not shown) 2000 Tosc NOTE: Run-time programming is done with Fogc = 6.0 MHz to 12.0 MHz, Voc, Vep, VaeF = 5V 0.5V, To = 25C +5C and Vpp = 12.75V + 0.25V. For run-time programming over a full operating range, contact the factory. DC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max Units lpp Vpp Supply Current (Whenever Programming) 100 mA NOTE: Vpp must be within 1V of Vcc while Voc < 4.5V. Vpp must not have a low impedance path to ground or Vsg while Voc > 4.5V. i 6-19AUTOMOTIVE 809XBH/839XBH/879XBH WAVEFORMEPROM PROGRAMMING TaVLL PORTS 3,4 / COMMAND TLL PALE PROG TAVLE TuLax PORTS 3,4 TLLvH PYER VALID Tove TUHPL TeLov Tecox TeLPH TeHpx 270361-14 Reserved location warning: Intel Reserved ad- dresses can not be used by applications which use 8X9XBH internal ROM/EPROM. The data read from a reserved location is not guaranteed, and a write to any reserved location could cause unpredictable re- sults. When attempting to program Intel Reserved addresses, the data must be OFFFFH to ensure a harmless result. A memory map indicating reserved locations on the 8X9XBH is shown in Figure 2. Intel Reserved locations, when mapped to external memory, must be filled with OFFFFH to ensure com- patibility with future devices. POWER SUPPLY SEQUENCE WHILE PROGRAMMING For any 879XBH that is in any programming mode, high voltages must be applied to the device. To avoid damaging the devices, the following rules must not be violated. RULE #1Vpp must not have a low impedance path to ground when Vcc is above 4.5V. RULE #2Vocc must be above 4.5V before Vpp can be higher than 5.0V. RULE #3 Vpp must be within 1V of Voc while Voc is below 4.5V. RULE #4 All voltages must be within tolerance and the oscillator stable before RESET rises. RULE #5EA must be brought high to place the devices in programming mode before Vpp is brought high. To adhere to these rules, the following power up and power down sequences can be followed. 6-20 POWER UP RESET = 0; CLOCK ON; if using an external clock ; instead of an oscillator Vcc = Vep = Vea = 5V; PALE = PROG = PORT 34 = Vin;* SID AND PMODE VALID; EA = 12.75V; Vpp = 12.75V; WAIT; wait for supplies and clock to ; settle RESET = 5V; WAIT Tshll; See datasheet BEGIN; POWER DOWN RESET = 0; Vpp = 5V; EA = Sv; PALE = PROG = SID = PMODE = PORT34 = Ov; Voc = Vpp = Vea = OV; CLOCK OFF; NOTE: "Vin, = Logical 1, 2.4V Minimum One final note on power up, power down. The maxi- mum limit on Vpp must never be violated, even for an instant. Therefore, an RC rise to the desired Vpp is recommended. Vpp is also sensitive to instanta- neous voltage steps. This also can be avoided by using an RC ramp on Vpp.a intel AUTOMOTIVE 809XBH/839XBH/879XBH ADDITIONAL INFORMATION MCS-96 Thermal Characteristics AN 9c Package ec/wy | ec/W) 68-Lead Plastic Leaded Chip Carrier 36 13.4 68-Lead Plastic Flatpack 36 13.4 NOTES: 65a = Thermai resistance between junction and the surrounding environment (ambient). Measurements are taken 1 ft. away from case in air flow environment. @jc = Thermal resistance between junction and package surface (case). All values of 0j4 and 6 jc may fluctuate depending on the environment (with or without airflow, and how much air flow) and device power dissipation at temperature of operation. Typical variations are + 2C/W. The graph below shows a typical 6Ja vs. Air Fiow rate for a PLCC package (with and without a heat speader). Surface Mounted Oi, (ec/w) Without Heat speader With Heat speader 0 0.2 0.4 0.6 0.8 1.0 AIR FLOW RATE (LFM) (thousands) 270361-15 Figure 7. 044 vs Linear Air Flow Figure 8 is an loc vs. temperature plot for the BX9XBH products. Test conditions are stated and actuals may vary depending on speed, package, Vcc and temperature, but will not exceed maximum limit specified at any case temperature between specified temperature limits. (Voge =5.5V / f= 12MHz) 250 230 210 190 loc 159 (mA) 130 110 90 70 50 40 -40 0 25 70 110 125 TEMPERATURE (C CASE) SPEC MAX MIN 270361-16 Figure 8. 8X9XBH Icc vs TEMP i 6-21AUTOMOTIVE 809XBH/839XBH/879XBH FUNCTIONAL DEVIATIONS The following is a list of all known functional devia- tions for 8X9XBH devices. CPU Section 1. Indexed, 3 Operand Multiply (Note C, D, E) in a three word multiply (MUL, MULB, MULU, MULUB) using indexed addressing mode, the dis- placement portion may not be in the range of 200H through 17FFH, inclusive. If the displace- ments in this range are necessary, the use of a two operand indexed multiply can be used with a move. 2. JBS and JBC Directly with Port Pins (Note C) The JBS and JBC instructions when used directly with Port 2.1 or all pins of Port 0 cannot be used. lf testing of these port pins is necessary, shadow the entire port data in a RAM register and test the bit in that RAM register. 3. BUSWIDTH and 8-Bit Bus (Note C) lf the BUSWIDTH pin is pulled high externally, or lefi to float, the internal pullup will pull this pin high. A high condition on this input equates to a 16-bit bus mode externally. During the CHIP CON- FIGURATION BYTE fetch cycle, the port circuitry changes the CCB address about 25 ns after RD goes low. If the CCB being read is trying to config- ure an 86-bit bus, the upper address lines (AD8-AD15) will NOT be latched during the CCB read. Therefore, if the read from the CCR (2018H) is in a x8 address space, the BUSWIDTH pin MUST be held low for this fetch, or the address lines ADB-AD15 must be latched (via a latched external EPROM or TTL latch). 4. FIFO/HS! Status Cleared (Note C, D) It is possible to have a time value in the FIFO with no status bits set in the HSI_STATUS register. When events are logged, the first event is loaded into the Hoiding Register, the next is loaded into slot #1 of the FIFO, the next in slot #2, etc. If the Holding Register is read after the #2 slot is load- ed, the #1 slot will be moved into the Holding Register to be read next. If another event is logged, it will be placed in slot #3, not #1 (the one just vacated). There are 7 slots in the FIFO. If the FIFO is allowed to roll over, that is a 9th event stored in the #1 slot again, before a cleared FIFO nappens, the Sth event will have a valid time with a cleared status bits in the HSI__ STATUS register (Bits 0, 2, 4 and 6 = 0). 6-22 intel. If the HSI_STATUS register status bits are cleared, there is no way of matching this time with an HSI input pin. It is important to note that in order to avoid this problem both interrupt routines and polling procedures which allow seven entries in the FIFO MUST clear all events from the FIFO before the next event is logged. if this is not pos- sible, events will have cleared status bits and these routines should also handle that case. To ensure proper operation of the High Speed tn- put FIFO, it is imperative that no more than seven FIFO entries be placed into an empty FIFO. This includes conditions that enter and clear multiple events but leave one or more eniries in the FIFO (i.e., add three entries, read one out, add four more, read one out, is seven entries). All seven must be emptied before allowing further events to occur at the pins. The FIFO is empty even if there is an entry in the Holding Register. (An event is defined as a pin transition. An entry is defined as one or more pin events loaded into a single FIFO array location.) Ailowing more than seven FIFO entries to occur between cleared conditions will result in incorrect status information for either the eighth or ninth entry. This effectively limits the total number of entries to seven. There is one exception that will allow the FIFO to correctly record eight entries. If the first two en- tries of a cleared FIFO and Holding Register are separated by greater than 16 state times, the ninth entry (rather than the eighth entry) will be recorded with incorrect status information. This is true even if the events following the first two en- tries were only separated by eight states. . RESET (Note C) If the XTAL inputs are driven BEFORE Vcc is sta- ble (between 4.5 Voc5.5 Voc), the state ma- chine locks the device into a condition which floats the node in control of the pulidown gate on the RESET pin. The pulldown node will remain on until the floating node loses the stored charge and releases the pulidown. All subsequent RESETs after the Power-on-Reset will operate correctly. Make sure that Vcc is stable before XTAL is driven. Since RESET is asynchronous, it is possible to apply RESET during writes to quasi-bidirectional port pins. If this occurs, the QBD port pins may not RESET immediately to a logical one. Instead of the low impedance pullup being turned on, only the high impedance device is on, causing the sig- nals on the QBD pins to rise more slowly than usual.intel. 6. Using T2CLK as source for Timer2 (Note C, D) TIMER2 has two selectable clock sources, the T2CLK or HSI.1 pins, selectable by bit |OC0.3. When using T2CLK as the clock for TIMER2, writ- ing to {OCO may cause TIMER2 to increment. The user should only write to 1OCO once during initiali- zation, and then immediately clear TIMER2 using the HSO command OEH. Effectively, the custom- er cannot reset TIMER2 with bit {OC0.1, and can only use the external reset sources or the HSO command when using T2CLK as the clock source. If the HSI.1 pin is the source for TIMER2, only the first write to |OCO may cause TIMER2 to increment, further writes will not increment TIM- ER2. . HSI Resolution (Note E) The HSI resolution has changed from 8 state times on the BH D-step to 9 state times on the BH E-step. This decreases the maximum HSI input speed from once every 8 state times to once ev- ery 9 state times. . Serial Port Flags (Note E) Reading SP__STAT may not clear the TI or RI flag if that flag was set within two state times prior to the read. In addition, the parity error bit (RPE/ RB8) may not be correct if it is read within two state times after Ri is set. . Checksum on Reserved Locations (Note E) This is a design consideration, not an errata. A test register was added to location 201Ch on the 8X9XBH E-step that controls the readability and writability of certain SFRs during testing. The ad- dition of these bits affects the readability and writ- ability of this reserved location when it is read. lf this location is included in a checksum (which it should not), a checksum difference could occur between the E-step and previous steppings. The User Guide states that reserved locations should not be read or written, this statement includes checksum reads also. AUTOMOTIVE 809XBH/839XBH/879XBH Note: C = present on C-step devices D = present on D-step devices E = present on E-step devices E-step and iater devices can be identified by a spe- cial mark following the eight digit FPO number on the top of the package. For E-step devices, this mark is an E. DATASHEET REVISION HISTORY The following are the key differences between this datasheet and the -005 version: 1. The preliminary status was dropped and re- placed with production status (no label). 2. Trademarks were updated. 6-23