74VHC32 — Quad 2-Input OR Gate
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0
February 2008
74VHC32
Quad 2-Input OR Gate
Features
High Speed: t
PD
=
3.8ns (typ.) at V
CC
=
5V
Low Power Dissipation: I
CC
=
2 µA (max.) at T
A
=
25°C
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
Power down protection is provided on all inputs
Low Noise: V
OLP
=
0.8V (max.)
Pin and Function Compatible with 74HC32
General Description
The VHC32 is an advanced high speed CMOS 2-Input
OR Gate fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The internal circuit is composed of 4 stages including
buffer output, which provide high noise immunity and
stable output. An input protection circuit ensures that 0V
to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface
5V to 3V systems and two supply systems such as bat-
tery back up. This circuit prevents device destruction due
to mismatched supply and input voltages.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74VHC32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
74VHC32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74VHC32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 2
74VHC32 — Quad 2-Input OR Gate
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Truth Table
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
ABO
HHH
LHH
HLH
LLL
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 3
74VHC32 — Quad 2-Input OR Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
V
IN
DC Input Voltage –0.5V to +7.0V
V
OUT
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
IK
Input Diode Current –20mA
I
OK
Output Diode Current ±20mA
I
OUT
DC Output Current ±25mA
I
CC
DC V
CC
/ GND Current ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
L
Lead Temperature (Soldering, 10 seconds) 260°C
Symbol Parameter Rating
V
CC
Supply Voltage 2.0V to +5.5V
V
IN
Input Voltage 0V to +5.5V
V
OUT
Output Voltage 0V to V
CC
T
OPR
Operating Temperature –40°C to +85°C
t
r
, t
f
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
0ns/V
100ns/V
0ns/V
20ns/V
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 4
74VHC32 — Quad 2-Input OR Gate
DC Electrical Characteristics
Noise Characteristics
Note:
2. Parameter guaranteed by design.
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
T
A
=
–40°C to
+85°C
UnitsMin. Typ. Max. Min. Max.
V
IH
HIGH Level Input
Voltage
2.0 1.50 1.50 V
3.0–5.5 0.7 x V
CC
0.7 x V
CC
V
IL
LOW Level Input
Voltage
2.0 0.50 0.50 V
3.0–5.5 0.3 x V
CC
0.3 x V
CC
V
OH
HIGH Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OH
=
–50µA 1.9 2.0 1.9 V
3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 I
OH
=
–4mA 2.58 2.48
4.5 I
OH
=
–8mA 3.94 3.80
V
OL
LOW Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OL
=
50µA 0.0 0.1 0.1 V
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 I
OL
=
4mA 0.36 0.44
4.5 I
OL
=
8mA 0.36 0.44
I
IN
Input Leakage
Current
0–5.5 V
IN
=
5.5V or GND ±0.1 ±1.0 µA
I
CC
Quiescent
Supply Current
5.5 V
IN
=
V
CC
or GND 2.0 20.0 µA
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
UnitsTyp. Limits
V
OLP(2)
Quiet Output Maximum
Dynamic V
OL
5.0 C
L
=
50pF 0.3 0.8 V
V
OLV(2)
Quiet Output Minimum
Dynamic V
OL
5.0 C
L
=
50pF –0.3 –0.8 V
V
IHD(2)
Minimum HIGH Level
Dynamic Input Voltage
5.0 C
L
=
50pF 3.5 V
V
ILD(2)
Maximum LOW Level
Dynamic Input Voltage
5.0 C
L
=
50pF 1.5 V
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 5
74VHC32 — Quad 2-Input OR Gate
AC Electrical Characteristics
Note:
3. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per gate).
Symbol Parameter V
CC (V) Conditions
TA = 25°C
TA = –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
tPHL, tPLH Propagation Delay 3.3 ± 0.3 CL = 15pF 5.5 7.9 1.0 9.5 ns
CL = 50pF 8.0 11.4 1.0 13.0
5.0 ± 0.5 CL = 15pF 3.8 5.5 1.0 6.5 ns
CL = 50pF 5.3 7.5 1.0 8.5
CIN Input Capacitance VCC = Open 4 10 10 pF
CPD Power Dissipation
Capacitance
(3) 14 pF
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 6
74VHC32 — Quad 2-Input OR Gate
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25 0.25
0.10 0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 7
74VHC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 8
74VHC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 9
74VHC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC32 Rev. 1.3.0 10
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ative or In Design This datasheet contains the design specifications for product
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Rev. I32
74VHC32 — Quad 2-Input OR Gate