Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
1
Low Skew, Low Additive Jitter, 10 output LVPECL/LVDS/HCSL
Fanout Buffer with one LVCMOS output
Features
• 3 to 1 input Multiplexer: Two inputs accept any
differential (LVPECL, HCSL, LVDS, SSTL, CML,
LVCMOS) or a single ended signal and the third
input accepts a crystal or a single ended signal
• Ten differential LVPECL/LVDS/HCSL outputs
• One LVCMOS output
• Ultra-low additive jitter: 24fs (integration band:
12kHz to 20MHz at 625MHz clock frequency)
• Supports clock frequencies from 0 to 1.6GHz
• Supports 2.5V or 3.3V power supplies on LVPECL,
LVDS or HCSL outputs
• Supports 1.5V, 1.8V, 2.5V or 3.3V on LVCMOS
outputs
• Embedded Low Drop Out (LDO) Voltage regulator
provides superior Power Supply Noise Rejection
• Maximum output to output skew of 40ps
• Device controlled via control pins
Figure 1. Functional Block Diagram
Ordering Information
ZL40231LDG1 48 Pin QFN Trays
ZL40231LDF1 48 pin QFN Tape and Reel
Package size: 7 x 7 mm
-40C to +85C
-40C to +85C
Bank B
Bank A
XOUT
XIN
OUT10
LVCMOS_OE
OUTA_TYPE_SEL0
OUTA_TYPE_SEL1
IN_SEL0
IN_SEL1
OUTB_TYPE_SEL0
OUTB_TYPE_SEL1
ZL40231
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
OUT4_p
OUT4_n
OUT5_p
OUT5_n
OUT6_p
OUT6_n
OUT7_p
OUT7_n
OUT8_p
OUT8_n
OUT9_p
OUT9_n
IN0_p
IN0_n
IN1_p
IN1_n
Synchronous
OE
OUT_A_TYPE_SEL[1:0] BANK A OUTPUT
LVECL
LVDS
HCSL
HIGH-Z
00
01
10
11
OUT_B_TYPE_SEL[1:0] BANK B OUTPUT
LVECL
LVDS
HCSL
HIGH-Z
00
01
10
11
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
2
Table of Contents
Features ..................................................................................................................................... 1
Applications................................................................................................................................ 1
Table of Contents ...................................................................................................................... 2
Pin Diagram ............................................................................................................................... 5
Pin Descriptions ......................................................................................................................... 6
Functional Description ............................................................................................................... 9
Clock Inputs ............................................................................................................................... 9
Clock Outputs .......................................................................................................................... 12
Crystal Oscillator Input ............................................................................................................. 13
Termination of unused inputs and outputs .............................................................................. 13
Power Consumption ................................................................................................................ 13
Power Supply Filtering ............................................................................................................. 14
Power Supplies and Power-up Sequence ............................................................................... 14
Host Interface .......................................................................................................................... 15
Typical device performance ..................................................................................................... 16
AC and DC Electrical Characteristics ...................................................................................... 20
Absolute Maximum Ratings ..................................................................................................... 20
Recommended Operating Conditions ..................................................................................... 20
Change History ........................................................................................................................ 34
Package Outline ...................................................................................................................... 35
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
3
List of Figures
Figure 1. Functional Block Diagram ........................................................................................................................................... 1
Figure 2. Pin Diagram ................................................................................................................................................................ 5
Figure 3. Input driven by a single ended output ........................................................................................................................ 9
Figure 4. Input driven by DC coupled LVPECL output ................................................................................................................. 9
Figure 5. Input driven by DC coupled LVPECL output (alternative termination) ...................................................................... 10
Figure 6. Input driven by AC coupled LVPECL output ............................................................................................................... 10
Figure 7. Input driven by HCSL output ..................................................................................................................................... 10
Figure 8. Input driven by LVDS output ..................................................................................................................................... 11
Figure 9. Input driven by AC coupled LVDS .............................................................................................................................. 11
Figure 10. Input driven by an SSTL output ................................................................................................................................. 11
Figure 11. Termination for LVCMOS output .............................................................................................................................. 12
Figure 12. Driving a load via transformer .................................................................................................................................. 12
Figure 13. Crystal Oscillator Circuit............................................................................................................................................ 13
Figure 14. Power Supply Filtering .............................................................................................................................................. 14
Figure 15. 156.25MHz LVPECL ................................................................................................................................................... 16
Figure 16. 1.5GHz LVPECL .......................................................................................................................................................... 16
Figure 17. 156.25MHz LVDS ...................................................................................................................................................... 16
Figure 18. 1.5GHz LVDS ............................................................................................................................................................. 16
Figure 19. 100MHz HCSL............................................................................................................................................................ 16
Figure 20. 250MHz HCSL............................................................................................................................................................ 16
Figure 21. I/O delay vs temperature .......................................................................................................................................... 17
Figure 22. PSNR vs noise frequency ........................................................................................................................................... 17
Figure 23. 100MHz LVPECL Phase Noise ................................................................................................................................... 17
Figure 24. 100MHz LVDS Phase Noise ....................................................................................................................................... 17
Figure 25. 25MHz LVDS Phase Noise in Xtal mode .................................................................................................................... 17
Figure 26. 100MHz HCSL Phase Noise ....................................................................................................................................... 17
Figure 27. 156.25MHz LVPECL Phase Noise ............................................................................................................................... 18
Figure 28. 625MHz LVPECL Phase Noise .................................................................................................................................... 18
Figure 29. 156.25MHz LVDS Phase Noise .................................................................................................................................. 18
Figure 30. 625MHz LVDS Phase Noise ....................................................................................................................................... 18
Figure 31. Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19
Figure 32. Output clock noise floor vs input clock slew-rate ..................................................................................................... 19
Figure 33. Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19
Figure 34. Output clock noise floor vs input clock slew-rate ..................................................................................................... 19
Figure 35. Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 19
Figure 36. Output clock noise floor vs input clock slew-rate ..................................................................................................... 19
Figure 37. Differential Input Voltage Levels .............................................................................................................................. 21
Figure 38. Differential Output Voltage Levels ........................................................................................................................... 25
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
4
List of Tables
Table 1 Pin Descriptions ................................................................................................................................................................................. 6
Table 2 Input clock selection ........................................................................................................................................................................ 15
Table 3 Output Type Selection ...................................................................................................................................................................... 15
Table 4 Absolute Maximum Ratings* ........................................................................................................................................................... 20
Table 5 Recommended Operating Conditions* ............................................................................................................................................ 20
Table 6 Current consumption ....................................................................................................................................................................... 20
Table 7 Input Characteristics* ...................................................................................................................................................................... 21
Table 8 Crystal Oscillator Characteristics* ................................................................................................................................................... 22
Table 9 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* .................................................................................................................. 22
Table 10 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* ................................................................................................................ 23
Table 11 LVCMOS Output Characteristics for VDDO = 3.3V* ....................................................................................................................... 23
Table 12 LVCMOS Output Characteristics for VDDO = 2.5V* ....................................................................................................................... 24
Table 13 LVPECL Output Characteristics for VDDO = 3.3V* ......................................................................................................................... 25
Table 14 LVPECL Output Characteristics for VDDO = 2.5V* ......................................................................................................................... 26
Table 15 LVDS Outputs for VDDO = 3.3V* .................................................................................................................................................... 27
Table 16 LVDS Outputs for VDDO = 2.5V* .................................................................................................................................................... 28
Table 17 HCSL Outputs for VDDO = 3.3V* .................................................................................................................................................... 29
Table 18 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 30
Table 19 LVCMOS Output Phase Noise with 25 MHz XTAL*......................................................................................................................... 31
Table 20 LVPECL Output Phase Noise with 25 MHz XTAL* ........................................................................................................................... 31
Table 21 LVDS Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 32
Table 22 HCSL Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 32
Table 23 7x7mm QFN Package Thermal Properties ..................................................................................................................................... 33
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
5
Pin Diagram
The device is packaged in a 7x7mm 48-pin QFN.
Figure 2. Pin Diagram
OUT0_p
OUT0_n
OUT1_p
OUT1_n
VDDO_A
OUT2_p
OUT2_n
VDDO_A
GND
OUTA_TYPE_SEL1
NC1
VDD_LVCMOS
OUT_LVCMOS
GND
VDD
IN1_p
OUT5_p
OUT5_n
OUT6_p
OUT6_n
VDDO_B
OUT7_p
OUT7_n
VDDO_B
GND
OUTA_TYPE_SEL0
VDD
XIN
XOUT
GND
IN_SEL0
IN0_p
4142434445464748
29
30
31
34
35
36
8
7
6
5
4
3
2
1
2019181716151413
32
33
OUT3_p
OUT3_n
OUT4_p
OUT4_n 12
11
10
9OUT8_p
OUT8_n
OUT9_p
OUT9_n
25
26
27
28
IN0_n
IN_SEL1
OUTB_TYPE_SEL0
GND
24232221
IN1_n
OUTB_TYPE_SEL1
LVCMOS_OE
GND
37383940
Exposed GND Pad 5.1 x 5.1 mm
Pin#1
Corner
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
6
Pin Descriptions
All device inputs and outputs are LVPECL unless described otherwise. The I/O column uses the following symbols: I
– input, IPU – input with 300k internal pull-up resistor, IPD – input with 300k internal pull-down resistor, IAPU – input
with 31k internal pull-up resistor, IAPD – input with 30k internal pull-down resistor, IAPU/APD – input biased to VDD/2
with 60k internal pull-up and pull-down resistors (30 k equivalent), O – output, I/O – Input/Output pin, NC-No
connect pin, P – power supply pin.
Table 1 Pin Descriptions
#
Name
I/O
Description
Input Reference
20
21
41
40
IN0_p
IN0_n
IN1_p
IN1_n
IAPD
IAPU/APD
IAPD
IAPU/APD
Input Differential or Single Ended References 0 and 1
Input frequency range 0Hz to 1.6GHz.
Non inverting inputs (_p) are pulled down with internal 30k pull-down resistors.
Inverting inputs (_n) are pulled up and pulled down with 60k internal resistors
(30k equivalent) to keep inverting input voltages at VDD/2 when inverting inputs
are left floating (device fed with a single ended reference).
Output Clocks
1
2
3
4
6
7
9
10
11
12
36
35
34
33
31
30
28
27
26
25
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
OUT4_p
OUT4_n
OUT5_p
OUT5_n
OUT6_p
OUT6_n
OUT7_p
OUT7_n
OUT8_p
OUT8_n
OUT9_p
OUT9_n
O
Ultra Low Additive Jitter Differential LVPECL/HCSL/LVDS Outputs 0 to 9
Output frequency range 0 to 1.6GHz
Type (LVPECL/HCSL/LVDS/High-Z) of each output bank is controlled via
OUTA/B_TYPE_SEL0/1 pins.
44
OUT_LVCMOS
O
Ultra Low Additive Jitter LVCMOS Output 0 to 9
Output frequency range 0 to 250MHz
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
7
Control
19
22
IN_SEL0
IN_SEL1
IPD
Input select pins. Logic level on these pins selects which input will be passed to
the output.
IN_SEL1
IN_SEL0
OUTN
0
0
Input 0 (IN0)
0
1
Input 1 (IN1)
1
X
Crystal Oscillator
14
47
OUTA_TYPE_SEL0
OUTA_TYPE_SEL1
IPD
Output Signal for Bank A: Selects Type of the output for Bank A (Outputs 0 to 4)
OUTA_TYPE_SEL1
OUTA_TYPE_SEL0
Output 0 to 4
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
High-Z (Disabled)
23
39
OUTB_TYPE_SEL0
OUTB_TYPE_SEL1
I/O
Output Signal for Bank B: Selects Type of the output for Bank B (Outputs 5 to 9)
OUTB_TYPE_SEL1
OUTB_TYPE_SEL0
Output 5 to 9
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
High-Z (Disabled)
46
LVCMOS_OE
I
Output enable for LVCMOS outputs: When high LVCMOS output is enabled.
When low LVCMOS output is High-Z
Crystal Oscillator
16
XIN
I
Crystal Oscillator Input or crystal bypass mode or crystal overdrive mode
If crystal oscillator circuit is not used pull down this pin or connect it to ground.
17
XOUT
O
Crystal Oscillator Output
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
8
No Connect
38
NC1
NC
No Connects (not connected to the die) Leave unconnected or connect to GND
for mechanical support
Power and Ground
15
42
VDD
P
Positive Supply Voltage. Connect to 3.3V or 2.5V supply.
5
8
VDDO_A
P
Positive Supply Voltage for Differential Outputs Bank A Connect 3.3V or 2.5V
power supply. VDDO_A does not have to be connected to the same voltage level as
VDD or VDDO_B.
These pins power up differential outputs OUT[0:4]_p/n.
29
32
VDDO_B
Positive Supply Voltage for Differential Outputs Bank B Connect 3.3V or 2.5V
power supply. VDDO_B does not have to be connected to the same voltage level as
VDD or VDDO_A.
These pins power up differential outputs OUT[5:9]_p/n.
45
VDD_LVCMOS
P
Power Supply Voltage for LVCMOS Output Connect to 3.3V, 2.5V, 1.8V or 1.5V
power supply
13
18
24
43
37
48
GND
P
Ground Connect to ground
E-Pad
GND
P
Ground. Connect to ground
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
9
Functional Description
The ZL40231 is a low additive jitter, low power 3 x 10 LVPECL/HCSL/LVDS fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML ) or single ended (LVPECL or
LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by
connecting an external crystal resonator between its XIN and XOUT pins.
The ZL40231 has ten LVPECL/HCSL/LVDS outputs which can be powered from 3.3V or 2.5V supply. Each output
bank (A and B) can be independently set to be LVPECL, LVDS, HCSL or Hi-Z via control OUTA/B_TYPE_SEL0/1
pins.
The control inputs: OUTA/B_TYPE_SEL0/1 and IN_SEL0/1 have low input threshold voltage so they can be driven
from a device with low I/O voltage (down to 1.2V).
The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature
range -40°C to +85°C.
Clock Inputs
The following blocks diagram shows how to terminate different signals fed to the ZL40231 inputs.
Figure 3 shows how to terminate a single ended output such as LVCMOS. Ideally, resistors R1 and R2 should be
100 each and Ro + Rs should be 50 so that the transmission line is terminated at both ends with characteristic
impedance. If the driving strength of the output driver is not sufficient to drive low impedance, the value of series
resistor RS should be increased. This will reduce the voltage swing at the input but this should be fine as long as the
input voltage swing requirement is not violated (Table 7). The source resistors of Rs = 270 could be used for
standard LVCMOS driver. This will provide 516mV of voltage swing for 3.3V LVCMOS driver with load current of
(3.3V/2) *(1/(270 + 50)) = 5.16mA.
For optimum performance both differential input pins (_p and _n) need to be DC biased to the same voltage. Hence,
the ratio R1/R2 should be equal to the ratio R3/R4.
Figure 3. Input driven by a single ended output
Figure 4. Input driven by DC coupled LVPECL output
R1
R2
Z0
= 50 Ω
MSCC Device
Vdd
Rs
Vdd
0.1 µF
Ro
Ro + Rs = Z0
Vdd
R3
R4
R1/R2 = R3/R4
Example:
R1 = R2 = 100Ω
R3 = R4 = 1kΩ
Rs = 270Ω for s tandard LVCMOS output
Vdd
0.1 µF
Optional AC coup ling
capacitor
Z0
= 50 Ω
Z0
= 50 Ω
LVPECL
MSCC Device
VDD
VDD VDD
VDD
RUP RDWN
VDD
3.3V
2.5V
127 Ω 82 Ω
250 Ω 62.5 Ω
RUP RUP
RDWN RDWN
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
10
Figure 5. Input driven by DC coupled LVPECL output (alternative termination)
Figure 6. Input driven by AC coupled LVPECL output
Figure 7. Input driven by HCSL output
100 Ω 100 Ω
100 Ω 100 Ω
Z0
= 50 Ω
Z0
= 50 Ω
LVPECL
MSCC Device
VDD
200 Ω
10 nF
10 nF
200 Ω
VDD
VDD
VDD
Z0
= 50 Ω
Z0
= 50 Ω
LVPECL LVPECL
50 Ω 50 Ω
VDD
VDD
MSCC Device
RDWN
VDD
3.3V
2.5V
50 Ω
22 Ω
RDWN
Z0
= 50 Ω
Z0
= 50 Ω
HCSL
MSCC Device
50 Ω 50 Ω
VDD
33 Ω
33 Ω
VDD 1 kΩ 1 kΩ
1 kΩ 1 kΩ
1µF
1µF
VDD VDD
50Ω resistors can be alternatively
connected at the source after 33Ω
series resistors.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
11
Figure 8. Input driven by LVDS output
Figure 9. Input driven by AC coupled LVDS
Figure 10. Input driven by an SSTL output
MSCC Device
100 Ω
Z0
= 50 Ω
Z0
= 50 Ω
LVDS
VDD
VDD
120 Ω 120 Ω
120 Ω 120 Ω
Z0
= 60 Ω
Z0
= 60 Ω
SSTL
MSCC Device
VDD VDD
VDD
Inpu t driven by SSTL driver
VDD
MSCC Device
100 Ω
Z0
= 50 Ω
Z0
= 50 Ω
LVDS
10 kΩ 10 kΩ
10 kΩ 10 kΩ
10 nF
10 nF
VDD
VDD VDD VDD
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
12
Clock Outputs
LVCMOS output OUT10 require only series termination resistor whose value is depending on LVCMOS output
voltage as shown in Figure 11.
Figure 11. Termination for LVCMOS output
Differential outputs LVPECL and LVDS should have same termination as corresponding outputs described in
previous section. HCSL outputs should be terminated with 33Ω series resistors at the source and 50Ω shunt resistors
at the source or at the end on the transmission line. AC coupling and re-biasing is not required at the outputs when
driving native HCSL receivers.
The device is designed to drive differential input of semiconductor devices. In applications that use a transformer to
convert from the differential to the single ended output (for example driving an oscilloscope 50 input), a resistor
larger than 10 should be added at the center tap of the primary winding to achieve optimum jitter performance as
shown in Figure 12. This is to provide a nominal common mode impedance of 10 or higher which is typical for
differential terminations.
Figure 12. Driving a load via transformer
Z0
= 50 Ω
MSCC Device
LVCMOS
VDDO
VDD = VDDO
Rs
Rs
VDDO
3.3V
2.5V
1.8V
1.5V
35Ω
30Ω
20Ω
10Ω
Z0
= 50 Ω
Z0
= 50 Ω
LVPECL
200 Ω
10 nF
10 nF
200 Ω
VDD
24.9 Ω
50 Ω
Add resistor to the ground or leave open
2 : 1Z0
= 50 Ω
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
13
SDDSIVP =
Crystal Oscillator Input
The crystal oscillator circuit can work with crystal resonators from 8MHz to 60MHz. Load capacitors C1, C2 and
series resistor Rs shall be selected as per crystal vendor recommendation. Shunt resistor is implemented inside the
device.
Figure 13. Crystal Oscillator Circuit
Termination of unused inputs and outputs
Unused inputs can be left unconnected or alternatively IN_0/1 can be pulled-down by 1kΩ resistor. Unused outputs
should be left unconnected.
Power Consumption
The device total power consumption can be calculated as:
Where:
The core power when XTAL is not used. The current is
specified in Table 6. If XTAL is running this power should
be set to zero.
The core power when XTAL is used. The current is
provided in Table 6. If XTAL is not used this power should
be set to zero.
Common output power shared among all ten outputs. The
current IDD_CM is specified Table 6.
Output power where output current (IDD_LVDS) is specified in
Table 6. For LVPECL or HCSL just replace IDD_LVDS with
IDD_LVPECL or IDD_HCSL.
N is the number of enabled differential outputs and it can be
either: 0, 5 or 10.
Dynamic LVCMOS output power. IDD is specified in Table 6.
If LVCMOS output is disabled this term is equal to zero.
MSCC Device
XIN
XOU T
Crystal
C1
C2
Load capacitors C1 and C2
should be as per crystal
specification
Rs
XTALDDDDXTAL IVP _
=
NIVP LVDSDDDDODIFO = __
CMDDDDOC IVP _
=
LVCMOSODIFOCXTALST PPPPPP __ ++++=
)
100/(
_
__
fCV
MHzfIVP
LOADLVCMOSDD
DDLVCMOSDDLVCMOSO
+
=
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
14
Power dissipated inside the device can be calculated by subtracting power dissipated in termination/biasing resistors
from the power consumption.
Where N1, N2 and N3 are the number of enabled LVPECL, LVDS and HSCL outputs respectively. When both banks
are enabled N1 + N2 + N3 = 10 and one or two of N1, N2 and N3 will equal to 0.
VOH and VOL are the output high and low voltages
respectively for LVPECL output
VB is LVPECL bias voltage equal to VDD – 2V
VSW is voltage swing of LVDS output.
VSW is voltage swing of HCSL output. 50Ω is
termination resistance and 33Ω is series resistance
of the HCSL output.
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with 0.1µF capacitor with minimum equivalent series
resistance (ESR) and minimum series inductance (ESL). For example, 0402 X5R Ceramic Capacitors with 6.3V
minimum rating could be used. These capacitors should be placed as close as possible to the power pins. To reduce
the power noise from adjacent digital components on the board each power supply could be further insulated with low
resistance ferrite bead with two capacitors. The ferrite bead will also insulate adjacent component from the noise
generated from the device. Following figure shows recommended decoupling for each power pin.
Figure 14. Power Supply Filtering
Power Supplies and Power-up Sequence
The device has four different power supplies: VDD, VDDO_A, VDDO_B and VDD_LVCMOS which are mutually
independent. Voltages supported by each of these power supplies are specified in Table 1.
The device is not sensitive to the power-up sequence. For example, commonly used sequence where higher voltage
comes up before or at the same time as the lower voltages can be used (or any other sequence).
HCSLLVDSLVPECLTD PNPNPNPP −−−= 321
= 100/
2
SWLVDS VP
10uF 1uF 0.1uF
Ferrite Bead
Board Supply VDD or VDDO
( ) ( )
( ) ( )
−+−+
−+−=
50/50/
50/50/ 22
BBOLBBOH
BOLBOHLVPECL VVVVVV
VVVVP
( ) ( )
+= 503350/2
SWHCSL VP
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
15
Host Interface
ZL40231 is controlled via Input Select (IN_SEL0/1) pins which select which one of three inputs is fed to the output
and show in Table 2 and OUTA/B_TYPE_SEL0/1 pins which select signal level (LVPECL, LVDS, HCSL or Hi-Z) for
each of two (A and B) output banks as shown in Table 3.
All input control pins have low input threshold voltage so they can be driven from the device with low output voltage
(FPGA/CPLD). Supported voltages are between 1.2V and VDD (2.5V or 3.3V).
Table 2 Input clock selection
IN_SEL1
IN_SEL0
Selected Input
0
0
IN0_p, IN0_n
0
1
IN1_p, IN1_n
1
X
XIN
Table 3 Output Type Selection
OUTA/B_TYPE_SEL1
OUTA/B_TYPE_SEL0
Output
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
High-Z (Output Disabled)
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
16
Typical device performance
The following plots show typical device performances
Figure 15. 156.25MHz LVPECL
Figure 16. 1.5GHz LVPECL
Figure 17. 156.25MHz LVDS
Figure 18. 1.5GHz LVDS
Figure 19. 100MHz HCSL
Figure 20. 250MHz HCSL
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
17
Figure 21. I/O delay vs temperature
Figure 22. PSNR vs noise frequency
Figure 23. 100MHz LVPECL Phase Noise
Figure 24. 100MHz LVDS Phase Noise
Figure 25. 25MHz LVDS Phase Noise in Xtal
mode
Figure 26. 100MHz HCSL Phase Noise
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
18
Figure 27. 156.25MHz LVPECL Phase Noise
Figure 28. 625MHz LVPECL Phase Noise
Figure 29. 156.25MHz LVDS Phase Noise
Figure 30. 625MHz LVDS Phase Noise
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
19
Figure 31. Output RMS jitter (12kHz to
20MHz) vs input clock slew-rate
Figure 32. Output clock noise floor vs input
clock slew-rate
Figure 33. Output RMS jitter (12kHz to
20MHz) vs input clock slew-rate
Figure 34. Output clock noise floor vs input
clock slew-rate
Figure 35. Output RMS jitter (12kHz to
20MHz) vs input clock slew-rate
Figure 36. Output clock noise floor vs input
clock slew-rate
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
20
AC and DC Electrical Characteristics
Absolute Maximum Ratings Table 4 Absolute Maximum Ratings*
Parameter
Sym.
Min.
Typ.
Max.
Units
Notes
1
Supply voltage (3.3V)
VDD /VDDO
-0.5
4.6
V
2
Supply voltage (2.5V)
VDD /VDDO
-0.5
3.5
V
3
Storage temperature
TST
-55
125
°C
* Exceeding these values may cause permanent damage
* Functional operation under these conditions is not implied
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions
Table 5 Recommended Operating Conditions*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Supply voltage 3.3V
VDD /VDDO/VDD_LVCMOS
3.135
3.30
3.465
V
2
Supply voltage 2.5V
VDD /VDDO/VDD_LVCMOS
2.375
2.50
2.625
V
3
Supply voltage 1.8V
VDD_LVCMOS
1.6
1.8V
2
V
4
Supply voltage 1.5V
VDD_LVCMOS
1.35
1.5
1.65
V
5
Operating temperature
TA
-40
25
85
°C
6
Input voltage
VDD-IN
- 0.3
VDD + 0.3
V
* Voltages are with respect to ground (GND) unless otherwise stated
* The device core supports two power supply modes (3.3V and 2.5V)
Table 6 Current consumption
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Core device current (all outputs and XTAL disabled)
Is_3.3V
163
197
mA
VDD= 3.3V+5%
Is_2.5V
153
187
mA
VDD = 2.5V+5%
2
Core device current (all outputs disabled) XTAL circuit
enabled with 25MHz Crystal connected between XIN and
XOUT
IDD_XTAL_3.3V
128
154
mA
VDD= 3.3V+5%
IDD_XTAL_2.5V
124
150
mA
VDD= 2.5V+5%
3
Common output current
IDD_CM_3.3V
13.44
15.05
mA
VDDO= 3.3V+5%
IDD_CM_2.5V
12.18
13.65
mA
VDDO= 2.5V+5%
4
Dynamic LVCMOS output current (f = 100MHz)
Needs to be scaled for different frequencies by f/100MHz
IDD_3.3V
2.38
2.68
mA
VDDO= 3.3V+5%
IDD_2.5V
1.74
1.96
mA
VDDO= 2.5V+5%
5
Current dissipation per LVEPCL output
IDD_LVPECL_3.3V
19.36
23.26
mA
VDDO= 3.3V+5%
IDD_LVPECL_2.5V
19.38
22.17
mA
VDDO= 2.5V+5%
6
Current dissipation per LVDS output
IDD_LVDSL_3.3V
6.73
8.00
mA
VDDO= 3.3V+5%
IDD_LVDS_2.5V
6.87
7.83
mA
VDDO= 2.5V+5%
7
Current dissipation per HCSL output
IDD_HCSL_3.3V
16.43
19.87
mA
VDDO= 3.3V+5%
IDD_HCSL_2.5V
17.14
19.18
mA
VDDO= 2.5V+5%
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
21
Table 7 Input Characteristics*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
CMOS high-level input voltage for control inputs
VCIH
1.05
V
2
CMOS low-level input voltage for control inputs
VCIL
0.45
V
3
CMOS input leakage current for control inputs (includes current due to pull
down resistors)
IIL
-25
50
µA
VI = VDD or 0 V
4
Differential input common mode voltage for IN0_p/n and IN1_p/n
VCM
1
2
V
5
Differential input voltage difference for IN0_p/n and IN1_p/n
f ≤ 1GHz **
VID
0.15
1.3
V
6
Differential input voltage difference for IN0_p/n and IN1_p/n for
1GHz < f ≤ 1.6GHz **
VID
0.35
1.3
V
7
Differential input leakage current for IN0_p/n and IN1_p/n (includes
current due to pull-up and pull-down resistors)
IIL
-150
150
µA
VI = 2V or 0V
8
Single ended input voltage for IN0_p and IN1_p
VSI
-0.3
2.7
V
VDD = 3.3V or
2.5V
9
Single ended input common mode voltage (IN0_p/n and IN1_p/n)
VSIC
1
2
V
VDD = 3.3V or
2.5V
10
Single ended input voltage swing for IN0_p and IN1_p
VSID
0.3
1.3
V
VDD = 3.3V or
2.5V
11
Input frequency (differential)
fIN
0
1600
MHz
12
Input frequency (LVCMOS)
fIN_CMOS
0
250
MHz
13
Input duty cycle
dc
35%
65%
14
Input slew rate
slew
2
V/ns
15
Input pull-up/ pull-down resistance
RPU/RPD
60kΩ
16
Input pull-down resistance for INx_p
RPD
30kΩ
17
Input multiplexer isolation IN0_p/n to IN1_p/n and vice versa
Power on both inputs 0dBm, fOFFSET > 50kHz
Iso
-84
dBc
fIN = 100 MHz
-82
fIN = 200 MHz
-71
fIN = 400 MHz
-67
fIN = 800 MHz
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
* Input mux isolation is measured as amplitude of fOFFSET spur in dBc on the output clock phase noise plot
**Input differential voltage is calculated as VID = VIH-VIL where VIH and VIL are input voltage high and low respectively. It should not be confused with VID = 2 * (VIH-
VIL) used in some datasheets. Please refer to Figure 37.
Figure 37. Differential Input Voltage Levels
2 * VID
0
VCM
0
VIH
VIL
VIH - VIL
VIL - VIH
V
ID
= V
IH
- V
IL
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
22
Table 8 Crystal Oscillator Characteristics*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Mode of oscillation
mode
Fundamental
2
Frequency
f
8
60
MHz
3
On chip load capacitance
1
pF
4
On chip series resistor
0
Ω
5
On chip shunt resistor
R
500
kΩ
6
Frequency in overdrive mode(1)
fOV
0.1
250
MHz
Functional but
may not meet
AC
parameters
Minimum
depends on
AC coupling
Capacitor
(0.1uF
assumed)
7
Frequency in bypass mode(2)
fBP
0
250
MHz
Functional but
may not meet
AC
parameters
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1) Maximum input level is 2V
(2) Maximum output level is VDD
Table 9 Power Supply Rejection Ratio for VDD = VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
PSRR for LVPECL output
PSRRLVPECL
-71.75
dBc
fIN = 156.25 MHz
-84.45
fIN = 312.5 MHz
-82.11
fIN = 625 MHz
2
PSRR for LVDS output
PSRRLVDS
-95.16
dBc
fIN = 156.25 MHz
-97.77
fIN = 312.5 MHz
-79.23
fIN = 625 MHz
3
PSRR for HCSL output
PSRRHCSL
-77.15
dBc
fIN = 100 MHz
-76.75
fIN = 156.25 MHz
-80.44
fIN = 312.5 MHz
* Values are over Recommended Operating Conditions
* Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
23
Table 10 Power Supply Rejection Ratio for VDD = VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
PSRR for LVPECL output
PSRRLVPECL
-73.68
dBc
fIN = 156.25 MHz
-78.88
fIN = 312.5 MHz
-71.82
fIN = 625 MHz
2
PSRR for LVDS output
PSRRLVDS
-90.04
dBc
fIN = 156.25 MHz
-79.99
fIN = 312.5 MHz
-73.45
fIN = 625 MHz
3
PSRR for HCSL output
PSRRHCSL
-92.16
dBc
fIN = 100 MHz
-74.08
fIN = 156.25 MHz
-91.88
fIN = 312.5 MHz
* Values are over Recommended Operating Conditions
* Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
Table 11 LVCMOS Output Characteristics for VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage (1mA load)
VOH
VDDO-0.1
V
DC
Measurement
2
Output low voltage (1mA load)
VOL
0.1
V
DC
Measurement
3
Output High Current (Load adjusted to Vout = VDDO/2)
IOH
30
mA
DC
Measurement
4
Output Low Current (Load adjusted to Vout = VDDO/2)
IOL
34
mA
DC
Measurement
5
Output impedance
RO
15
Ω
DC
Measurement
6
Rise time (20% to 80%)
tr
220
310
ps
7
Fall time (20% to 80%)
tf
320
365
ps
8
Output frequency
FO
0
250
MHz
9
Input to output delay
tIOD
1.07
1.28
2.07
ns
10
Output enable time
tEN
3
cycles
11
Output disable time
TDIS
3
cycles
12
Additive RMS jitter in 1MHz to 5MHz band
Tj_1M_5M
46
80
fs
Input Clock
25MHz
13
Additive RMS jitter in 12kHz to 5MHz band
Tj_12K_5M
56
90
fs
Input Clock
25MHz
14
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
60
79
fs
Input Clock
125MHz
15
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
65
86
fs
Input Clock
125MHz
16
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
61
94
fs
Input Clock
156.25MHz
17
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
66
100
fs
Input Clock
156.25MHz
18
Noise floor
NF
-165
-162
dBc/Hz
Input clock:
25 MHz
19
-160
-156
dBc/Hz
Input clock:
125 MHz
20
-158
-153
dBc/Hz
Input clock:
156.25 MHz
* Values are over Recommended Operating Conditions
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
24
Table 12 LVCMOS Output Characteristics for VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage (1mA load)
VOH
VDDO-0.1
V
DC
Measurement
2
Output low voltage (1mA load)
VOL
0.1
V
DC
Measurement
3
Output High Current (Load adjusted to Vout = VDDO/2)
IOH
21
mA
DC
Measurement
4
Output Low Current (Load adjusted to Vout = VDDO/2)
IOL
25
mA
DC
Measurement
5
Output impedance
RO
15
Ω
DC
Measurement
6
Rise time (20% to 80%)
tr
225
310
ps
7
Fall time (20% to 80%)
tf
320
365
ps
8
Output frequency
FO
0
250
MHz
9
Input to output delay
tIOD
1.10
1.41
2.30
ns
10
Output enable time
tEN
3
cycles
11
Output disable time
TDIS
3
cycles
12
Additive RMS jitter in 1MHz to 5MHz band
Tj_1M_5M
51
104
fs
Input Clock
25MHz
13
Additive RMS jitter in 12kHz to 5MHz band
Tj_12k_5M
62
111
fs
Input Clock
25MHz
14
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
64
81
fs
Input Clock
125MHz
15
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
70
88
fs
Input Clock
125MHz
16
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
62
94
fs
Input Clock
156.25MHz
17
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
68
100
fs
Input Clock
156.25MHz
18
Noise floor
NF
-164
-161
dBc/Hz
Input clock:
25 MHz
19
-159
-155
dBc/Hz
Input clock:
125 MHz
20
-158
-153
dBc/Hz
Input clock:
156.25 MHz
* Values are over Recommended Operating Conditions
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
25
Table 13 LVPECL Output Characteristics for VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VLVPECL_OH
1.9
2.08
2.4
V
DC Measurement
2
Output low voltage
VLVPECL_OL
1.2
1.36
1.7
V
DC Measurement
3
Output differential swing**
VLVPECL_SW
0.6
0.72
0.9
V
DC Measurement
4
Variation of VLVPECL_SW for complementary output states
∆VLVPECL_SW
0
0.02
0.07
V
5
Common mode output
VCM
1.6
1.72
2.1
V
7
Output frequency when VLVPECL_SW ≥ 0.6V
FMAX_0.6VSW
800
MHz
8
Output frequency when VLVPECL_SW ≥ 0.4V
FMAX_0.4VSW
1600
MHz
9
Rise or fall time (20% to 80%)
tr, tf
110
170
ps
10
Output frequency
FO
0
1600
MHz
11
Output to output skew
tOOSK
40
ps
12
Device to device output skew
tDOOSK
120
ps
13
Input to output delay
tIOD
0.73
0.87
1.1
ns
14
Output enable time
tEN
3
cycles
15
Output disable time
tDIS
3
cycles
16
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
68
96
fs
Input clock: 100 MHz
50
64
fs
Input clock: 156.25MHz
20
32
fs
Input clock: 625 MHz
17
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
71
101
fs
Input clock: 100 MHz
55
70
fs
Input clock: 156.25MHz
25
39
fs
Input clock: 625 MHz
18
Noise floor
NF
-161
-159
dBc/Hz
Input clock: 100 MHz
-160
-155
dBc/Hz
Input clock: 156.25 MHz
-155
-151
dBc/Hz
Input clock: 625 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Figure 38. Differential Output Voltage Levels
VOH
2 * V
SW
0
VCM
0
VOL
VOH - VOL
VOL - VOH
VSW = VOH - VOL
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
26
Table 14 LVPECL Output Characteristics for VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VLVPECL_OH
1.1
1.28
1.7
V
DC Measurement
2
Output low voltage
VLVPECL_OL
0.4
0.57
0.9
V
DC Measurement
3
Output differential swing**
VLVPECL_SW
0.6
0.71
0.9
V
DC Measurement
4
Variation of VLVPECL_SW for complementary output states
∆VLVPECL_SW
0
0.02
0.05
V
5
Common mode output
VCM
0.8
0.92
1.2
V
7
Output frequency when VLVPECL_SW ≥ 0.6V
FMAX_0.6VSW
800
MHz
8
Output frequency when VLVPECL_SW ≥ 0.4V
FMAX_0.4VSW
1600
MHz
9
Rise or fall time (20% to 80%)
tr, tf
120
170
ps
10
Output frequency
FO
0
1600
MHz
11
Output to output skew
tOOSK
40
ps
12
Device to device output skew
tDOOSK
120
ps
13
Input to output delay
tIOD
0.75
0.87
1.1
ns
14
Output enable time
tEN
3
cycles
15
Output disable time
tDIS
3
cycles
16
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
65
91
fs
Input clock: 100 MHz
50
64
fs
Input clock: 156.25MHz
20
30
fs
Input clock: 625 MHz
17
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
69
99
fs
Input clock: 100 MHz
54
75
fs
Input clock: 156.25MHz
26
41
fs
Input clock: 625 MHz
18
Noise floor
NF
-161
-159
dBc/Hz
Input clock: 100 MHz
-160
-156
dBc/Hz
Input clock: 156.25 MHz
-155
-151
dBc/Hz
Input clock: 625 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
27
Table 15 LVDS Outputs for VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VLVDS_OH
1.3
1.39
1.47
V
DC Measurement
2
Output low voltage
VLVDS_OL
1.0
1.07
1.15
V
DC Measurement
3
Output differential swing**
VLVDS_SW
0.25
0.32
0.39
V
DC Measurement
4
Variation of VLVDS_SW for complementary output states
∆VLVDS_SW
0
0.002
0.01
V
5
Common mode output
VCM
1.15
1.23
1.3
V
6
Variation of VCM for complementary output states
∆VCM
0
0.001
0.01
V
7
Output frequency when VLVDS_SW ≥ 250mV
FMAX_0.25VSW
800
MHz
8
Output frequency when VLVDS_SW ≥ 200mV
FMAX_0.2VSW
1600
MHz
9
Rise or fall time (20% to 80%)
tr, tf
110
170
ps
10
Output frequency
FO
0
1600
MHz
11
Output to output skew
tOOSK
20
ps
12
Device to device output skew
tDOOSK
130
ps
13
Input to output delay
tIOD
0.76
0.86
1.1
ns
14
Output Short Circuit Current Single Ended
IS
-24
24
mA
Single ended outputs
shorted to GND
15
Output Short Circuit Current Differential
ISD
-24
24
mA
Complementary outputs
shorted
16
Output enable time
tEN
3
cycles
17
Output disable time
tDIS
3
cycles
18
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
110
144
fs
Input clock: 100 MHz
63
81
fs
Input clock: 156.25MHz
21
33
fs
Input clock: 625 MHz
19
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
115
150
fs
Input clock: 100 MHz
73
102
fs
Input clock: 156.25MHz
26
40
fs
Input clock: 625 MHz
20
Noise floor
NF
-158
-156
dBc/Hz
Input clock: 100 MHz
-158
-155
dBc/Hz
Input clock: 156.25 MHz
-154
-151
dBc/Hz
Input clock: 625 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
28
Table 16 LVDS Outputs for VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VLVDS_OH
1.3
1.4
1.5
V
DC Measurement
2
Output low voltage
VLVDS_OL
0.97
1.05
1.13
V
DC Measurement
3
Output differential swing**
VLVDS_SW
0.25
0.35
0.44
V
DC Measurement
4
Variation of VLVDS_SW for complementary output states
∆VLVDS_SW
0
0.001
0.01
V
5
Common mode output
VCM
1.15
1.23
1.3
V
6
Variation of VCM for complementary output states
∆VCM
0
0.001
0.01
V
7
Output frequency when VLVDS_SW ≥ 250mV
FMAX_0.25VSW
800
MHz
8
Output frequency when VLVDS_SW ≥ 200mV
FMAX_0.2VSW
1600
MHz
9
Rise or fall time (20% to 80%)
tr, tf
110
170
ps
10
Output frequency
FO
0
1600
MHz
11
Output to output skew
tOOSK
20
ps
12
Device to device output skew
tDOOSK
130
ps
13
Input to output delay
tIOD
0.78
0.86
1.12
ns
14
Output Short Circuit Current Single Ended
IS
-24
24
mA
Single ended outputs
shorted to GND
15
Output Short Circuit Current Differential
ISD
-24
24
mA
Complementary outputs
shorted
16
Output enable time
tEN
3
cycles
17
Output disable time
tDIS
3
cycles
18
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
107
140
fs
Input clock: 100 MHz
62
77
fs
Input clock: 156.25MHz
20
31
fs
Input clock: 625 MHz
19
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
111
146
fs
Input clock: 100 MHz
66
83
fs
Input clock: 156.25MHz
24
36
fs
Input clock: 625 MHz
20
Noise floor
NF
-158
-156
dBc/Hz
Input clock: 100 MHz
-159
-155
dBc/Hz
Input clock: 156.25 MHz
-155
-151
dBc/Hz
Input clock: 625 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
29
Table 17 HCSL Outputs for VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VHCSL_OH
0.6
0.85
1.1
V
DC Measurement
2
Output low voltage
VHCSL_OL
-0.05
0
0.05
V
DC Measurement
3
Output differential swing**
VHCSL_SW
0.6
0.85
1.1
V
DC Measurement
4
Variation of VHCSL_SW for complementary output states
∆VHCSL_SW
0
0.003
0.05
V
5
Common mode output
VCM
0.28
0.43
0.55
V
6
Variation of VCM for complementary output states
∆VCM
0
0.002
0.05
V
7
Absolute Crossing Voltage
VCROSS
0.320
0.384
0.447
V
8
Total Variation of VCROSS
∆VCROSS
0.127
V
9
Output frequency
FMAX
0
400
MHz
10
Rise or fall time (20% to 80%)
tr, tf
143
309
ps
11
Output to output skew
tOOSK
21
ps
12
Device to device output skew
tDOOSK
129
ps
13
Input to output delay
tIOD
0.73
0.90
1.08
ns
14
Output enable time
tEN
3
cycles
15
Output disable time
tDIS
3
cycles
16
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
TjPCIe_3.0
20
40
fs
Input clock: 100MHz
17
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
73
104
fs
Input clock: 100 MHz
53
69
fs
Input clock: 156.25MHz
18
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
77
112
fs
Input clock: 100 MHz
64
100
fs
Input clock: 156.25MHz
19
Noise floor
NF
-161
-159
dBc/Hz
Input clock: 100 MHz
-159
-155
dBc/Hz
Input clock: 156.25 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
30
Table 18 HCSL Outputs for VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Output high voltage
VHCSL_OH
0.6
0.83
1.1
V
DC Measurement
2
Output low voltage
VHCSL_OL
-0.05
0
0.05
V
DC Measurement
3
Output differential swing**
VHCSL_SW
0.5
0.83
1.1
V
DC Measurement
4
Variation of VHCSL_SW for complementary output states
∆VHCSL_SW
0
0.003
0.05
V
5
Common mode output
VCM
0.28
0.42
0.55
V
6
Variation of VCM for complementary output states
∆VCM
0
0.002
0.05
V
7
Absolute Crossing Voltage
VCROSS
0.260
0.316
0.372
V
8
Total Variation of VCROSS
∆VCROSS
0.108
V
9
Output frequency
FMAX
0
400
MHz
10
Rise or fall time (20% to 80%)
tr, tf
125
162
ps
11
Output to output skew
tOOSK
21
ps
12
Device to device output skew
tDOOSK
129
ps
13
Input to output delay
tIOD
0.76
0.92
1.10
ns
14
Output enable time
tEN
3
cycles
15
Output disable time
tDIS
3
cycles
16
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
TjPCIe_3.0
20
40
fs
Input clock: 100MHz
17
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
68
95
fs
Input clock: 100 MHz
52
66
fs
Input clock: 156.25MHz
18
Additive RMS jitter in 12kHz to 20MHz band
Tj_12k_20M
72
102
fs
Input clock: 100 MHz
56
71
fs
Input clock: 156.25MHz
19
Noise floor
NF
-161
-158
dBc/Hz
Input clock: 100 MHz
-160
-153
dBc/Hz
Input clock: 156.25 MHz
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 38.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
31
Table 19 LVCMOS Output Phase Noise with 25 MHz XTAL*
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Jitter RMS in 12kHz to 5MHz band
103
fs
VDD = 3.3V, VDDO = 3.3V
117
fs
VDD = 2.5V; VDDO = 2.5V
2
Noise floor
-75
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
-107
dBc/Hz
@100Hz, VDD = 3.3V, VDDO = 3.3V
-132
dBc/Hz
@1kHz, VDD = 3.3V, VDDO = 3.3V
-150
dBc/Hz
@10kHz, VDD = 3.3V, VDDO = 3.3V
-162
dBc/Hz
@100kHz, VDD = 3.3V, VDDO = 3.3V
-166
dBc/Hz
@1MHz, VDD = 3.3V, VDDO = 3.3V
-166
dBc/Hz
@5MHz, VDD = 3.3V, VDDO = 3.3V
-70
dBc/Hz
@10Hz, VDD = 2.5V; VDDO = 2.5V
-102
dBc/Hz
@100Hz, VDD = 2.5V; VDDO = 2.5V
-130
dBc/Hz
@1kHz, VDD = 2.5V; VDDO = 2.5V
-149
dBc/Hz
@10kHz, VDD = 2.5V; VDDO = 2.5V
-161
dBc/Hz
@100kHz, VDD = 2.5V; VDDO = 2.5V
-165
dBc/Hz
@1MHz, VDD = 2.5V; VDDO = 2.5V
-165
dBc/Hz
@5MHz, VDD = 2.5V; VDDO = 2.5V
* Values are over Recommended Operating Conditions
Table 20 LVPECL Output Phase Noise with 25 MHz XTAL*
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Jitter RMS in 12kHz to 5MHz band
265
fs
VDD = 3.3V, VDDO = 3.3V
213
fs
VDD = 2.5V; VDDO = 2.5V
2
Noise floor
-75
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
-107
dBc/Hz
@100Hz, VDD = 3.3V, VDDO = 3.3V
-133
dBc/Hz
@1kHz, VDD = 3.3V, VDDO = 3.3V
-152
dBc/Hz
@10kHz, VDD = 3.3V, VDDO = 3.3V
-157
dBc/Hz
@100kHz, VDD = 3.3V, VDDO = 3.3V
-158
dBc/Hz
@1MHz, VDD = 3.3V, VDDO = 3.3V
-157
dBc/Hz
@5MHz, VDD = 3.3V, VDDO = 3.3V
-71
dBc/Hz
@10Hz, VDD = 2.5V; VDDO = 2.5V
-103
dBc/Hz
@100Hz, VDD = 2.5V; VDDO = 2.5V
-130
dBc/Hz
@1kHz, VDD = 2.5V; VDDO = 2.5V
-151
dBc/Hz
@10kHz, VDD = 2.5V; VDDO = 2.5V
-158
dBc/Hz
@100kHz, VDD = 2.5V; VDDO = 2.5V
-160
dBc/Hz
@1MHz, VDD = 2.5V; VDDO = 2.5V
-159
dBc/Hz
@5MHz, VDD = 2.5V; VDDO = 2.5V
* Values are over Recommended Operating Conditions
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
32
Table 21 LVDS Output Phase Noise with 25 MHz XTAL
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Jitter RMS in 12kHz to 5MHza band
178
fs
VDD = 3.3V, VDDO = 3.3V
190
fs
VDD = 2.5V; VDDO = 2.5V
2
Noise floor
-75
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
-107
dBc/Hz
@100Hz, VDD = 3.3V, VDDO = 3.3V
-133
dBc/Hz
@1kHz, VDD = 3.3V, VDDO = 3.3V
-154
dBc/Hz
@10kHz, VDD = 3.3V, VDDO = 3.3V
-161
dBc/Hz
@100kHz, VDD = 3.3V, VDDO = 3.3V
-161
dBc/Hz
@1MHz, VDD = 3.3V, VDDO = 3.3V
-160
dBc/Hz
@5MHz, VDD = 3.3V, VDDO = 3.3V
-68
dBc/Hz
@10Hz, VDD = 2.5V; VDDO = 2.5V
-103
dBc/Hz
@100Hz, VDD = 2.5V; VDDO = 2.5V
-130
dBc/Hz
@1kHz, VDD = 2.5V; VDDO = 2.5V
-152
dBc/Hz
@10kHz, VDD = 2.5V; VDDO = 2.5V
-161
dBc/Hz
@100kHz, VDD = 2.5V; VDDO = 2.5V
-160
dBc/Hz
@1MHz, VDD = 2.5V; VDDO = 2.5V
-159
dBc/Hz
@5MHz, VDD = 2.5V; VDDO = 2.5V
* Values are over Recommended Operating Conditions
Table 22 HCSL Output Phase Noise with 25 MHz XTAL
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Jitter RMS in 12kHz to 20MHz band
269
fs
VDD = 3.3V, VDDO = 3.3V
228
fs
VDD = 2.5V; VDDO = 2.5V
2
Noise floor
-76
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
-107
dBc/Hz
@100Hz, VDD = 3.3V, VDDO = 3.3V
-133
dBc/Hz
@1kHz, VDD = 3.3V, VDDO = 3.3V
-152
dBc/Hz
@10kHz, VDD = 3.3V, VDDO = 3.3V
-157
dBc/Hz
@100kHz, VDD = 3.3V, VDDO = 3.3V
-157
dBc/Hz
@1MHz, VDD = 3.3V, VDDO = 3.3V
-157
dBc/Hz
@5MHz, VDD = 3.3V, VDDO = 3.3V
-73
dBc/Hz
@10Hz, VDD = 2.5V; VDDO = 2.5V
-105
dBc/Hz
@100Hz, VDD = 2.5V; VDDO = 2.5V
-131
dBc/Hz
@1kHz, VDD = 2.5V; VDDO = 2.5V
-151
dBc/Hz
@10kHz, VDD = 2.5V; VDDO = 2.5V
-158
dBc/Hz
@100kHz, VDD = 2.5V; VDDO = 2.5V
-159
dBc/Hz
@1MHz, VDD = 2.5V; VDDO = 2.5V
-159
dBc/Hz
@5MHz, VDD = 2.5V; VDDO = 2.5V
* Values are over Recommended Operating Conditions
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
33
Table 23 7x7mm QFN Package Thermal Properties
Parameter
Symbol
Condition
Value
Units
Maximum Ambient Temperature
TA
85
C
Maximum Junction Temperature
TJMAX
125
C
Junction to Ambient Thermal Resistance(1) (Note 1)
JA
still air
21.1
C/W
1m/s airflow
16.9
2.5m/s airflow
15.0
Junction to Board Thermal Resistance
JB
6.9
C/W
Junction to Case Thermal Resistance
JC
12.8
C/W
Junction to Pad Thermal Resistance(2)
JP
Still air
3.9
C/W
Junction to Top-Center Thermal Characterization Parameter
JT
Still air
0.2
C/W
(1) Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on an 4-layer JEDEC standard test board and dissipating
maximum power
(2) Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package)
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
34
Change History
June 2017 was the first release of the document.
July 2017 release changes:
• Modified power calculation in the Power Consumption section.
August 2017 release changes:
• Modified “Input driven by HCSL output” figure.
• Modified additive jitter for 156.25MHz input clock.
• Added Figure 37 and Figure 38
October 2018 release changes:
• Added note in pinout to tie XIN pin when crystal circuit is not used
• Removed Figures 15 and 16 due to inaccuracy
• Fixed typo in Table 3
.
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
35
Package Outline
Data Sheet
ZL40231
ZL40231
October 2018
© 2018 Microsemi Corporation
36
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