Lattice Semiconductor LA-ispPAC-POWR1014/A Automotive Family Data Sheet
5-3
Pin Descriptions
Number Name Pin Type Voltage Range Description
44 IN1 Digital Input VCCINP
1, 2
PLD Logic Input 1 Registered by MCLK
46 IN2 Digital Input VCCINP
1, 3
PLD Logic Input 2 Registered by MCLK
47 IN3 Digital Input VCCINP
1, 3
PLD Logic Input 3 Registered by MCLK
48 IN4 Digital Input VCCINP
1, 3
PLD Logic Input 4 Registered by MCLK
25 VMON1 Analog Input -0.3V to 5.87V
4
Voltage Monitor 1 Input
26 VMON2 Analog Input -0.3V to 5.87V
4
Voltage Monitor 2 Input
27 VMON3 Analog Input -0.3V to 5.87V
4
Voltage Monitor 3 Input
28 VMON4 Analog Input -0.3V to 5.87V
4
Voltage Monitor 4 Input
32 VMON5 Analog Input -0.3V to 5.87V
4
Voltage Monitor 5 Input
33 VMON6 Analog Input -0.3V to 5.87V
4
Voltage Monitor 6 Input
34 VMON7 Analog Input -0.3V to 5.87V
4
Voltage Monitor 7 Input
35 VMON8 Analog Input -0.3V to 5.87V
4
Voltage Monitor 8 Input
36 VMON9 Analog Input -0.3V to 5.87V
4
Voltage Monitor 9 Input
37 VMON10 Analog Input -0.3V to 5.87V
4
Voltage Monitor 10 Input
7, 31 GNDD
5
Ground Ground Digital Ground
30 GNDA
5
Ground Ground Analog Ground
41, 23 VCCD
6
Power 2.8V to 3.96V Core VCC, Main Power Supply
29 VCCA
6
Power 2.8V to 3.96V Analog Power Supply
45 VCCINP Power 2.25V to 5.5V VCC for IN[1:4] Inputs
20 VCCJ Power 2.25V to 3.6V VCC for JTAG Logic Interface Pins
24 VCCPROG Power 3.0V to 3.6V VCC for E
2
Programming when the Device is Not
Powered by V
CCD
and V
CCA
15 HVOUT1
Open Drain Output
7
0V to 8V Open-Drain Output 1
Current Source/Sink 12.5µA to 100µA Source
100µA to 3000µA Sink High-voltage FET Gate Driver 1
14 HVOUT2
Open Drain Output
7
0V to 8V Open-Drain Output 2
Current Source/Sink 12.5µA to 100µA Source
100µA to 3000µA Sink High-voltage FET Gate Driver 2
13 SMBA_OUT3 Open Drain Output
7
0V to 5.5V Open-Drain Output 3, (SMBUS Alert Active Low,
LA-ispPAC-POWR1014A only).
12 OUT4 Open Drain Output
7
0V to 5.5V Open-Drain Output 4
11 OUT5 Open Drain Output
7
0V to 5.5V Open-Drain Output 5
10 OUT6 Open Drain Output
7
0V to 5.5V Open-Drain Output 6
9 OUT7 Open Drain Output
7
0V to 5.5V Open-Drain Output 7
8 OUT8 Open Drain Output
7
0V to 5.5V Open-Drain Output 8
6 OUT9 Open Drain Output
7
0V to 5.5V Open-Drain Output 9
5 OUT10 Open Drain Output
7
0V to 5.5V Open-Drain Output 10
4 OUT11 Open Drain Output
7
0V to 5.5V Open-Drain Output 11
3 OUT12 Open Drain Output
7
0V to 5.5V Open-Drain Output 12
2 OUT13 Open Drain Output
7
0V to 5.5V Open-Drain Output 13
1 OUT14 Open Drain Output
7
0V to 5.5V Open-Drain Output 14
40 RESETb
8
Digital I/O 0V to 3.96V Device Reset (Active Low) - Internal pull-up
42 PLDCLK Digital Output 0V to 3.96V 250kHz PLD Clock Output (Tristate), CMOS
Output - Internal pull-up