Programmable Delay Lines 100K ECL interfaced (3 BIT) 16 Pins DIP SERIES: PDU-53 Features: g 3-BIT Programmable @ Accurate Timing a Completely 100K ECL Interfaced Specifications: # Min. input pulse width: 3 ns or 15% of total delay whichever is greater. mg Min. PRR: 8 ns or 2 < pulse width whichever is greater. = Delay variation: Monotonic in one direction. = Programmed delay tolerance: 5% or 40 ps whichever is greater. = Inherent delay (Too): 2.2 ns. m Address to output prop. delay (Tsua): 2.9 ns max. u Power supply voltage: 5V + .7V. = Power supply current: 150 ma. = Temperature coefficient: 100 PPM/C. = Operating temp. range: 0C to + 85C. Storage temp. range: 65C to -- 150C. m DC parameters: See ECL-100K Logic Table on Page 6. Delay Total Increment Programmed Part No. (ps) Delay (ps) PDU-53-100 400+ 50 700 PDU-53-200 200+ 60 1,400 PDU-53-250 260+ 60 1,750 PDU-53-400 400+ 80 2,800 PDU-53-500 00 + 100 3,500 PDU-53-750 750 + 100 ,250 PDU-53-1000 1,000 + 200 7,000 PDU-53-1200 1,200 + 200 8,400 PDU-53-1500 1,500 + 200 10,500 PDU-53-2000 2,000 + 466 14,000 PDU-53-2500 2,500 + 400 17,500 PDU-53-3000 3,000 + 500 21,000 Test Conditions: @ Input pulse width: = Input pulse voltage: 10 ns BV p-p @ Input PRR: = Supply voltage (Vee): 100 ns 4.5V @ Input pulse rise-time: = Ambient temperature(T.): tons + 25C -580 .600 MAX, #.005 le.870 + 010 -280 MAX. .O15 TYP. 100 TYP.-| je pooneay 2 No pull-up resistors used internally on input & output. 3 Mt. Prospect Avenue, Clifton. New Jersey 07013 @ (201) 773-2299 m FAX (201) 773-9672 46