PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II). Features * Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge * Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK * Quad internal banks operation * Possible to assert random column address in every clock cycle * Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) * Automatic precharge and controlled precharge * Auto refresh (CBR refresh) and self refresh * x4, x8, x16 organization * Byte write control (x4, x8) by DM * Byte write control (x16) by LDM and UDM * 2.5 V 0.125 V Power supply for Vcc * 2.5 V 0.125 V Power supply for VccQ * Maximum clock frequency up to 133 MHz * SSTL_2 compatible with all signals * 4,096 refresh cycles/64 ms * 66-pin Plastic TSOP (II) (400 mil) * Burst termination by Precharge command and Burst stop command The information in this document is subject to change without notice. Document No. M13852EJ1V1DS00 (1st edition) Date Published December 1998 NS CP(K) Printed in Japan The mark * shows major revised points. (c) 1998 PD45D128442, 45D128842, 45D128164 Ordering Information Part Number Organization Clock frequency (word x bit x bank) CL = 2 Package MHz (MAX.) PD45D128442G5-C10-9LG 8M x 4 x 4 PD45D128442G5-C12-9LG PD45D128842G5-C10-9LG 4M x 8 x 4 PD45D128842G5-C12-9LG PD45D128164G5-C10-9LG PD45D128164G5-C12-9LG 2 100 66-pin Plastic TSOP (II) 83 (400 mil) 100 83 2M x 16 x 4 100 83 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 Part Number [x4, x8] PD45D128 842 G5 - C10 NEC Memory Synchrounous DRAM Data rate D: Double Capacity 128: 128M bits Organization 4: x4 8: x8 Number of Banks 4: 4Bank Interface 2: SSTL_2 Package G5: TSOP (II) VCC C: 2.5 V Minimum Cycle time 10: 10 ns (100MHz) 12: 12 ns (83MHz) [x16] 164 Organization 16: x16 Number of Banks and Interface 4: 4Bank, SSTL_2 Preliminary Data Sheet 3 PD45D128442, 45D128842, 45D128164 Pin Configuration [PD45D128442] 66-pin Plastic TSOP (II) (400mil) 8M word x 4 bit x 4 bank Vcc NC VccQ NC DQ0 VssQ NC NC VccQ NC DQ1 VssQ NC NC VccQ NC NC Vcc NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 Vcc 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 : Address inputs /CAS : Row address inputs /WE : Write enable DM : DQ write mask enable : Bank select VCC : Supply voltage DQ0 - DQ3 : Data inputs/outputs VSS : Ground DQS : Data strobe VCCQ : Supply voltage for DQ and DQS CLK, /CLK : System clock input VSSQ : Ground for DQ and DQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe A0 - A11 A0 - A11 A0 - A9, A11 : Column address inputs BA0, BA1 4 Vss NC VssQ NC DQ3 VccQ NC NC VssQ NC DQ2 VccQ NC NC VssQ DQS NC VREF Vss DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 Vss Preliminary Data Sheet : Column address strobe PD45D128442, 45D128842, 45D128164 [PD45D128842] 66-pin Plastic TSOP (II) (400mil) 4M word x 8 bit x 4 bank Vcc DQ0 VccQ NC DQ1 VssQ NC DQ2 VccQ NC DQ3 VssQ NC NC VccQ NC NC Vcc NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 Vcc 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Vss DQ7 VssQ NC DQ6 VccQ NC DQ5 VssQ NC DQ4 VccQ NC NC VssQ DQS NC VREF Vss DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs /CAS : Row address inputs /WE : Write enable : Column address inputs DM : DQ write mask enable : Bank select VCC : Supply voltage DQ0 - DQ7 : Data inputs/outputs VSS : Ground DQS : Data strobe VCCQ : Supply voltage for DQ and DQS CLK, /CLK : System clock input VSSQ : Ground for DQ and DQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe A0 - A11 A0 - A11 A0 - A9 BA0, BA1 Preliminary Data Sheet : Column address strobe 5 PD45D128442, 45D128842, 45D128164 [PD45D128164] 66-pin Plastic TSOP (II) (400mil) 2M word x 16bit x 4 bank Vcc DQ0 VccQ DQ1 DQ2 VssQ DQ3 DQ4 VccQ DQ5 DQ6 VssQ DQ7 NC VccQ LDQS NC Vcc NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 Vcc Vss DQ15 VssQ DQ14 DQ13 VccQ DQ12 DQ11 VssQ DQ10 DQ9 VccQ DQ8 NC VssQ UDQS NC VREF Vss UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 Vss : Address inputs /CAS : Row address inputs /WE : Write enable : Column address inputs LDM, UDM : DQ write mask enable : Bank select VCC : Supply voltage DQ0 - DQ15 : Data inputs/outputs VSS : Ground LDQS,UDQS : Data strobe VCCQ : Supply voltage for DQ, LDQS and UDQS CLK, /CLK : System clock input VSSQ : Ground for DQ, LDQS and UDQS CKE : Clock enable VREF : Input reference /CS : Chip select NC : No connection /RAS : Row address strobe A0 - A11 A0 - A11 A0 - A8 BA0, BA1 6 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Preliminary Data Sheet : Column address strobe PD45D128442, 45D128842, 45D128164 Clock Generator Block Diagram Bank D Bank C Bank B A0 - A11, BA0, BA1 Mode Register Row Address Buffer and Refresh Counter Row Decoder CLK /CLK CKE Memory Cell Array Bank A Control Logic /CS /RAS /CAS /WE Column Decoder Sense Amp. Column Decoder Column Address Buffer and Burst Counter Data Control Circuit Latch Circuit CLK, /CLK DLL Input & Output Buffer DQS DM DQ Preliminary Data Sheet 7 PD45D128442, 45D128842, 45D128164 CONTENTS 1. Input/Output Pin Function ..... 10 2. Commands ..... 11 3. Simplified State Diagram ..... 15 4. Truth Table ..... 16 4.1 Command Truth Table ..... 16 4.2 DM Truth Table ..... 16 4.3 CKE Truth Table ..... 16 4.4 Operative Command Table ..... 17 4.5 Command Truth Table for CKE ..... 20 5. Initialization ..... 21 6. Programming the Mode Register ..... 22 7. Mode Register ..... 23 7.1 Burst Length and Sequence ..... 24 8. Address Bits of Bank-Select and Precharge ..... 25 9. Precharge ..... 26 9.1 Read to Precharge Command Interval ..... 26 9.2 Write to Precharge Command Interval ..... 27 10. Auto Precharge ..... 28 10.1 Read with Auto Precharge ..... 28 10.2 Write with Auto Precharge ..... 29 11. Read/Write Command Interval ..... 30 11.1 Read to Read Command Interval ..... 30 11.2 Write to Write Command Interval ..... 31 11.3 Write to Read Command Interval ..... 32 11.4 Read to Write Command Interval ..... 33 8 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 12. Burst Termination ..... 34 12.1 Burst Stop Command in Read Cycle ..... 34 12.2 Precharge Termination in Read Cycle ..... 35 12.3 Precharge Termination in Write Cycle ..... 36 13. Electrical Specifications ..... 37 13.1 Absolute Maximum Ratings ..... 37 13.2 Recommended Operating Conditions ..... 37 13.3 Pin Capacitance (TA = 25 C, f = 1 MHz) ..... 37 13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) ..... 38 13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) ..... 38 13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted) ..... 39 13.6.1 Test Conditions ..... 39 13.6.2 Timing Diagram ..... 40 13.6.3 Synchronous Characteristics ..... 41 13.6.4 Synchronous Characteristics Example ..... 42 13.6.5 Asynchronous Characteristics ..... 42 14. Package Drawing ..... 74 15. Recommended Soldering Conditions ..... 75 Preliminary Data Sheet 9 PD45D128442, 45D128842, 45D128164 1. Input/Output Pin Function Pin name CLK, /CLK Input/Output Input Function CLK and /CLK are the master clock inputs. The timing reference point for the differential clock is when CLK and /CLK cross. All control and address inputs except for DQ, DM and CKE are latched by a rising edge of CLK. By both of rising and falling edges of CLK, output DQ and DQS are validated. CKE Input CKE controls power down mode. When the PD45D128xxx is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS Input /CS low starts a command input cycle. When /CS is high, commands are ignored but the current operations will be continued. /RAS, /CAS, /WE Input As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Refer to the command table. A0 - A11 Input Row address is determined by A0 - A11 at the rising edge of CLK in active command cycle. It does not depend on the bit organization. Column address is determined by A0 - A9, A11 at the rising edge of CLK in read or write command cycle. It depends on the bit organization : A0 - A9, A11 for x4 device, A0 - A9 for x8 device, A0 - A8 for x16 device. A10 defines precharge mode. When A10 is high in precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, precharge starts automatically after the burst access. BA0, BA1 Input BA0, BA1 are bank select signals. In command cycle, BA0 and BA1 low select Bank A, BA0 low and BA1 High select bank B, BA0 high and BA1 low select bank C and then BA0 and BA1 high select bank D. DQ0 - DQ15 Input/Output DQ pins have the same function as I/O pins on conventional DRAMs. DQS, LDQS, Input/Output Active on the both edges for data input and output. DM, LDM, UDM Input DM's are latched by both of rising and falling edges of the DQS. In write mode, DM's control byte mask. Unlike regular SDRAMs, DM's do not control read operation. VREF Input VREF is reference voltage for SSTL input buffers. VCC, VCCQ, VSS, VSSQ (Power Supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power supply pins for the output buffers. UDQS 10 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 2. Commands Extended mode register set command Fig.1 Extended mode register set command (/CS, /RAS, /CAS, /WE Low) CLK The PD45D128xxx has an extended mode register that defines enabling or disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data input CKE H /CS pins. After power on, the extended mode register set command must be executed to /RAS /CAS enabling or disabling DLL. The extended mode register can be set only when all banks are in idle state. /WE During 2 CLK (tRSC) following this command, the PD45D128xxx can not accept BA0 any other commands. BA1 A10 Add Mode register set command Fig.2 Mode register set command (/CS, /RAS, /CAS, /WE Low) CLK The PD45D128xxx has a mode register that defines how the device operates. In this command, A0 through A11, BA0 and BA1 are the data input pins. CKE After power on, the mode register set command must be executed to initialize the /RAS device. /CAS The mode register can be set only when all banks are in idle state. During 2 CLK (tRSC) following this command, the PD45D128xxx can not accept any other commands. H /CS /WE BA0,BA1 A10 Add Bank activate command Fig.3 Bank activate command (/CS, /RAS = Low, /CAS, /WE = High) CLK CKE The PD45D128xxx has four banks, each with 4,096 rows. This command activates the bank and the row address selected by BA0 and BA1, and by A0 through A11 respectively. H /CS /RAS /CAS This command corresponds to a conventional DRAM's /RAS falling. /WE BA0,BA1 Preliminary Data Sheet A10 Row Add Row 11 PD45D128442, 45D128842, 45D128164 Precharge command Fig.4 Precharge command (/CS, /RAS, /WE= Low, /CAS = High) CLK CKE This command begins precharge operation of the bank selected by BA0, BA1 and A10. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the PD45D128xxx can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command can terminate the current burst operation. This command corresponds to a conventional DRAM's /RAS rising. Read command H /CS /RAS /CAS /WE BA0, BA1 A10 (Precharge select) Add Fig.5 Read command (/CS, /CAS = Low, /RAS, /WE = High) CLK This command begins the burst read operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 CKE H /CS /RAS respectively. Read data is available after /CAS latency requirements which have been met. /CAS /WE And it is synchronized with DQS. BA0, BA1 A10 (Auto precharge select) Add Write command Col. Fig.6 Write command (/CS, /CAS, /WE = Low, /RAS = High) CLK CKE This command begins burst write operation. The bank and the burst start column address are selected by BA0 and BA1 and by A0 through A11 respectively. Write data must be input by DQ0 through DQ15. Byte mask data must be input by DM, LDM, and UDM. Both data must be synchronized with DQS that is inputted H /CS /RAS /CAS /WE after this command. BA0, BA1 A10 (Auto precharge select) Add 12 Preliminary Data Sheet Col. PD45D128442, 45D128842, 45D128164 CBR (auto) refresh command Fig.7 CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) CLK This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. CKE H /CS Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a bank activate command. /RAS /CAS /WE During tRC (refresh command to refresh or activate command period), the PD45D128xxx cannot accept any other command. BA0, BA1 A10 Add Self refresh entry command Fig.8 Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) CLK CKE After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the PD45D128xxx will exit the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. /CS /RAS /CAS /WE BA0, BA1 A10 Add Burst stop command Fig.9 Burst stop command (/CS, /WE = Low, /RAS, /CAS = High) CLK CKE This command can stop the current read burst operation. H /CS /RAS /CAS /WE BA0, BA1 A10 Add Preliminary Data Sheet 13 PD45D128442, 45D128842, 45D128164 No operation Fig.10 No operation (/CS = Low, /RAS, /CAS, /WE = High) CLK CKE This command is not an execution command. /CS This command doesn't begin or terminate any operation. /RAS /CAS /WE BA0, BA1 A10 Add 14 Preliminary Data Sheet H PD45D128442, 45D128842, 45D128164 3. Simplified State Diagram SREX Self Refresh Recovery Self Refresh SELF MRS Mode Register Set REF IDLE (tRSC) CBR (auto) Refresh (tRC) PW ACT DN PDE X Bank Activating Power Down DN PW EX PD BANK ACTIVE BS T RE ITA (B ur AD st A WR RE PRE/PALL L) P (tD AD en d) READ WRIT WRIT READ READ WRIT RE ITA WR AD A READA tio e ur st en d) rg Precharge (B (P re E( E PR ) n) ) tio n tio ina AL /t D m PL r te na ge mi ar ch ter re (tD PR (P ina rge E n) READA rm a ch PR Pre ch arg et ch erm a READA te Pre WRITA ina tio E( n) PR WRITA PRE/PALL POWER ON (tRP) Automatic sequence Manual input Preliminary Data Sheet 15 PD45D128442, 45D128842, 45D128164 4. Truth Table 4.1 Command Truth Table Function Symbol CKE /CS n-1 n /RAS /CAS /WE Address BA0 BA1 A10 A0-7,A11 Device deselect DESL H x H x x x x x x No operation NOP H x L H H H x x x Burst stop Read Read with auto precharge BST H x L H H L x x x READ H x L H L H V L V READA Write WRIT Write with auto precharge H H x L H L L V L WRITA Bank active ACT H x L L H H Prechrage select bank PRE H x L L H L Precharge all banks PALL Mode register set MRS Extended mode register set V H H x L L L V L EMRS V L x x H x L L L V H L L V 4.2 DM Truth Table Function Symbol CKE DM n-1 n U L Data write enable ENB H x L Data mask MASK H x H Upper byte write enable ENBU H x L x Lower byte write enable ENBL H x x L Upper byte write inhibit MASKU H x H x Lower byte write inhibit MASKL H x x H 4.3 CKE Truth Table Current State Function Idle CBR (auto) refresh command Symbol CKE n-1 n REF H H /CS /RAS /CAS /WE Address L L L H x Idle Self refresh entry SELF H L Self refresh Self refresh exit SREX L H x x x x x Idle Power down entry PWDN H L x x x x x Power down Power down exit PDEX L H x x x x x Remark H = High level, L = Low level, V = Valid, x = High or Low level (Don't care) 16 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 4.4 Operative Command Table Note1 (1/3) Current state Idle Row active Read /CS /RAS /CAS /WE Address Command Action Notes H x x x x DESL Nop or Power down L H H H x NOP Nop or Power down L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT Bank activating L L H L BA, A10 PRE/PALL Nop 3 L L L H x REF/SELF CBR (auto) refresh or Self refresh 4 L L L L Op-Code MRS Mode register set 4 L L L L Op-Code EMRS Extended mode register set 4 H x x x x DESL Nop L H H H x NOP Nop L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA Begin read/read with AP L H L L BA, CA, A10 WRIT/WRITA Begin write/write with AP L L H H BA, RA L L H L BA, A10 L L L H x L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL ACT 2 ILLEGAL 2 PRE/PALL Precharge/Precharge all banks 5 REF ILLEGAL H x x x x DESL Nop (Row active after burst end) L H H H x NOP Nop (Row active after burst end) L H H L x BST terminate burst, Row active L H L H BA, CA, A10 READ/READA terminate burst, Begin new read/ 6 6 read with AP L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL terminate burst, 6 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL Precharge/Precharge all banks Write L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Row active after tDPL) L H H H x NOP Nop (Row active after tDPL ) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA terminate burst, Begin read/read with AP 6 L H L L BA, CA, A10 WRIT/WRITA terminate burst, Begin new write/ L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL terminate burst, Precharge/Precharge all 6 banks L L L H x REF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL 6 write with AP Preliminary Data Sheet 2 17 PD45D128442, 45D128842, 45D128164 (2/3) Current state /CS /RAS /CAS /WE Address Command Action Notes Read with auto H x x x x DESL Nop (Precharge after burst end) precharge L H H H x NOP Nop (Precharge after burst end) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL Write with H x x x x DESL Nop (Idle after tDAL) auto precharge L H H H x NOP Nop (Idle after tDAL) L H H L x BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 Precharge Row activating 18 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Idle after tRP) L H H H x NOP Nop (Idle after tRP) L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Nop (Idle after tRP) 3 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Row active after tRCD) L H H H x NOP Nop (Row active after tRCD) L H H L x BST ILLEGAL 2 L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL L L L L Op-Code SRS ILLEGAL Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 (3/3) Current state Write recovering /CS /RAS /CAS /WE Address Command Action Notes H x x x x DESL Nop (Row active after tDPL) L H H H x NOP Nop (Row active after tDPL) L H H L x BST Nop (Row active after tDPL) L H L H BA, CA, A10 READ/READA Begin read/read with AP L H L L BA, CA, A10 WRIT/WRITA Begin new write/write with AP L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL Write recovering H x x x x DESL Nop (Idle after tDAL) with auto precharge L H H H x NOP Nop (Idle after tDAL) L H H L x BST L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H x REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL L L L L Op-Code EMRS ILLEGAL H x x x x DESL Nop (Idle after tRC) L H H H x NOP Nop (Idle after tRC) L H H L x BST Nop (Idle after tRC) 2 L H L x x READ/WRIT ILLEGAL 2 L L H x x ACT/PRE/PALL ILLEGAL 3 L L L x x REF/SELF/MRS/E ILLEGAL MRS Mode register H x x x x DESL Nop (Idle after tRSC) accessing L H H H x NOP Nop (Idle after tRSC) L H H L x BST ILLEGAL 2 L H x x x READ/WRIT ILLEGAL 2 L L x x x ACT/PRE/PALL/R ILLEGAL EF/SELF/MRS/EM RS 2 Refresh Remark ILLEGAL H = High level, L = Low level, x = High or Low level (Don't care), BA = Bank address, RA = Row address, CA = Column address, A10 = Precharge control address, Op-Code = Operand code, Nop = No operation, AP = Auto precharge, ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified states; function may be legal in the bank indicated by BA0, BA1 depending on the state of that bank. 3. Nop to bank precharging or in idle state. May precharge bank indicated by BA0, BA1. 4. ILLEGAL if any bank is not idle. 5. ILLEGAL if tRAS is not satisfied. 6. Must satisfy command interval and/or burst terminate condition. Preliminary Data Sheet 19 PD45D128442, 45D128842, 45D128164 4.5 Command Truth Table for CKE Current State Self refresh Self refresh recovery Power down All banks idle CKE /CS /RAS /CAS /WE Add Command Action n-1 n H x x x x x x L H x x x x x L L x x x x x H H H x x x x DESL Nop (Idle after tRC) H H L H H H x NOP Nop (Idle after tRC) H L x x x x x ILLEGAL(Impossible) SREX Exit S.R, self refresh recovery 2 Maintain self refresh ILLEGAL L x x x x x x ILLEGAL (Impossible) H x x x x x x ILLEGAL (Impossible) L H x x x x x PDEX Exit power down, Idle L L x x x x x Maintain power down H H V V V V x Refer to operative command table H L H x x x x PWDN Power down entry 1 PWDN Power down entry 1 H L L H H H x H L L x x L x ILLEGAL H L L H L x x ILLEGAL H L L L H x X H L L L L H X L X x x x x x ILLEGAL (Impossible) Row active H x x x x x x Refer to operative command table L x x x x x x Power down Any state except H H V V V V V Refer to operative command table listed above H L x x x x x ILLEGAL L x x x x x x ILLEGAL (Impossible) ILLEGAL SELF Self refresh entry Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid, Add = Address (A0 - A11, BA0, BA1), ILLEGAL = Device operation and/or data-integrity are not guaranteed Notes 1. Self refresh can be entered only from all banks idle state. Power down can be entered only from all banks idle or row active state. 2. CKE low to high transition will re-enable CLK and other inputs asynchronously. A Minimum setup time must be satisfied before any command other than exit. 20 Notes Preliminary Data Sheet 1 1 PD45D128442, 45D128842, 45D128164 5. Initialization The PD45D128xxx is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) After the pause, EMRS and MRS command must be performed to enable or disable DLL and reset DLL. The additional 200 cycles of clock input is required to lock the DLL and all banks must be precharged using the precharge command. In this case, PALL command is convenient. (3) After the precharge, the mode register can be programmed by MRS command. (4) Two or more REF command must be performed after or before MRS command. Case 1 : MRS after the REF Min. 200 cycles tRSC tRSC tRP tRC tRSC tRC CLK CKE EMRS MRS DLL enable / disable DLL reset Command PALL REF REF MRS Any Command Minimum of 2 times REF command must be performed. Remark CKE may be held low and CLK may be run until 1 cycle before EMRS command is asserted to ensure data-bus Hi-Z. Preliminary Data Sheet 21 PD45D128442, 45D128842, 45D128164 6. Programming the Mode Register The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields ; Option : BA0, BA1, A11 through A7 /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the mode critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. shows the relationship of /CAS latency to the clock period and speed grade of the device. Burst Length Burst length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 2, 4, 8. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 2, 4 and 8. 22 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 7. Mode Register BA1 BA0 A11 0 0 0 BA1 BA0 A11 x x x BA1 BA0 A11 0 1 0 BA1 BA0 A11 0 0 0 A10 A9 A8 A7 0 0 0 1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 x x 1 1 V V V V V V V A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 DLL A10 A9 A8 A7 0 0 DLL 0 Bit 8 A6 A5 A4 A3 A2 A1 A0 JEDEC standard test set (Refresh counter Test) A6 A5 LTMODE A4 A3 WT A2 A1 A0 Vender specific Extended mode register set Normal 1 Reset DLL 0 Enable 1 Disable Mode register set BL Bit 2 - Bit 0 WT = 0 WT = 1 000 R R 001 2 2 Burst 010 4 4 Length 011 8 8 100 R R 101 R R 110 R R 111 R R DLL 0 Bit 0 Remark V = Valid, x = Don't care CLK CKE Wrap Bit 3 Mode /CS Type 0 Sequential 1 Interleave Bit 6 - Bit 4 /CAS Latency 000 R 001 R Latency 010 2 Mode 011 R 100 R 101 R 110 2.5 111 R /RAS /CAS /WE A0 - A11, BA0, BA1 Mode register set timming Remark R : Reserved Preliminary Data Sheet 23 PD45D128442, 45D128842, 45D128164 7.1 Burst Length and Sequence [Burst Length = Two] Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A0, binary) (decimal) (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A1 - A0, binary) (decimal) (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [Burst Length = Four] [Burst Length = Eight] 24 Starting Address Sequential Addressing Sequence Interleave Addressing Sequence (column address A2 - A0, binary) (decimal) (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 8. Address Bits of Bank-Select and Precharge [Activate Command] A10 A9 A8 A6 A5 A4 A3 A2 A1 A0 Row Address A7 A6 A5 A4 A3 A2 A1 A0 Row Address A7 A6 A5 A4 A3 A2 A1 A0 Column Address BA1 BA0 A11 A7 BA1 BA0 Result 0 0 Select Bank A, ''Activate'' command 0 1 Select Bank B, ''Activate'' command 1 0 Select Bank C, ''Activate'' command 1 1 Select Bank D, ''Activate'' command [Precharge Command] BA1 BA0 A11 A10 A9 A8 BA1 BA0 A10 Result 0 0 0 Precharge Bank A 0 1 0 Precharge Bank B 1 0 0 Precharge Bank C 1 1 0 Precharge Bank D x x 1 Precharge All Banks Remark x = Don't care [Read/Write Command] BA1 BA0 A11 A10 A10 Result A9 A8 0 Disables Auto-Precharge 1 Enables Auto-Precharge BA1 BA0 Result 0 0 Enables Read/Write commands for Bank A 0 1 Enables Read/Write commands for Bank B 1 0 Enables Read/Write commands for Bank C 1 1 Enables Read/Write commands for Bank D Preliminary Data Sheet 25 PD45D128442, 45D128842, 45D128164 9. Precharge 9.1 Read to Precharge Command Interval The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. /CAS latency = 2 : (burst length/2) clocks after the read command is issued. /CAS latency = 2.5 : (burst length/2) clocks after the read command is issued. Burst length = 4 T0 T1 T2 T3 T4 T5 CLK /CLK CKE /CAS latency = 2 Command READ PRE Hi-Z DQS Q1 DQ Q2 Q3 Hi-Z Q4 /CAS latency = 2.5 Command READ PRE Hi-Z DQS DQ Q1 Q2 Q3 Q4 Hi-Z (Must satisfy tRAS) 26 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 9.2 Write to Precharge Command Interval In order to write all burst data to the memory cell correctly, the asynchronous parameter tDPL (MIN.) must be satisfied. The tDPL specification defines the earliest time that a precharge command can be issued. Burst length = 4 T0 T1 T2 T3 T4 T5 tDPL = 1 cycle CLK /CLK DM /CAS latency = 2, 2.5 Command WRITE PRE Preamble Postamble DQS Hi-Z DQ Q1 Q2 Q3 Q4 (Must satisfy tRAS) Preliminary Data Sheet 27 PD45D128442, 45D128842, 45D128164 10. Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begin automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. 10.1 Read with Auto Precharge When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from a read with auto precharge command. Burst length = 4 T0 T1 T2 T3 Burst length / 2 cycle T4 T5 tRP CLK /CLK CKE /CAS latency = 2 Command READA ACT Auto precharge starts Hi-Z Q1 DQ Q2 Q3 Q4 /CAS latency = 2.5 Command READA ACT Auto precharge starts Hi-Z DQ Q1 Q2 Q3 Q4 (When tRAS is satisfied) Remark READA means Read with Auto Precharge command 28 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 10.2 Write with Auto Precharge When a write with auto precharge command is issued, the auto precharge begins after tDPL(MIN.) is satisfied. Burst length = 2 T0 T1 T2 T3 T4 T5 tDAL = tDPL + tRP tDPL = 1 cycle tRP CLK /CLK CKE /CAS latency = 2, 2.5 Command Auto precharge starts ACT WRITEA DQS DQ D1 D2 (When tRAS is satisfied) Remark WRITEA means Write with Auto Precharge command Preliminary Data Sheet 29 PD45D128442, 45D128842, 45D128164 11. Read/Write Command Interval 11.1 Read to Read Command Interval During a read cycle, when new read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between commands is minimum 1 cycle. Each read command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 1 cycle CLK /CLK CKE /CAS latency = 2 Command READ A READ B Hi-Z DQ QA1 QA2 QB1 QB2 QB3 QB4 QA1 QA2 QB1 QB2 QB3 /CAS latency = 2.5 Command READ A READ B Hi-Z DQ 30 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 11.2 Write to Write Command Interval During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with new write command. WRITE will be interrupted by another WRITE. The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 1 cycle CLK /CLK CKE /CAS latency = 2, 2.5 Command WRITE A WRITE B DQS DQ DA1 DA2 DB1 DB2 Preliminary Data Sheet DB3 DB4 31 PD45D128442, 45D128842, 45D128164 11.3 Write to Read Command Interval The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance at least 1 cycle prior to the first output data. The minimum time interval between the rising clock edge after the last input data and the read command is 1 cycle. When the read command is issued, the invalid data from the burst write cycle must be masked by DM. T0 T1 T2 T3 T4 T6 T5 1 cycle CLK /CLK CKE /CAS latency = 2 , , ,,, ,,,,,, ,,, ,,, ,, , ,,,,,, ,,, ,,,,,, Command Write A Read B Hi-Z DQS DA1 DQ Hi-Z DA2 QB1 QB2 QB3 QB4 QB1 QB2 QB3 DM /CAS latency = 2.5 Command Write A Read B Hi-Z DQS DQ DA1 Hi-Z DA2 DM DQ and DQS : Input 32 DQ and DQS : Output Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 11.4 Read to Write Command Interval To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid data conflict. The data bus must be high impedance at least 1 cycle before the write command is issued. When the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 3 cycles prior to the write command. T0 T1 T2 T0 T3 T4 T1 T5 T6 T7 T8 T2 T9 T10 T3 T11 T12 T4 T13 T14Burst length = 8 T6 T5 CLK /CLK CKE /CAS latency = 2 Command Read A BST Write B Hi-Z DQS QA1 DQ QA2 QA3 QA4 Hi-Z DB1 DB2 DB DB1 DB2 DB /CAS latency = 2.5 Command Read A BST Write B Hi-Z DQS DQ QA1 QA2 QA3 DQ and DQS : Output Preliminary Data Sheet QA4 Hi-Z DQ and DQS : Input 33 PD45D128442, 45D128842, 45D128164 12. Burst Termination 12.1 Burst Stop Command in Read Cycle During a burst read cycle, when the burst stop command is issued at the rising edge of the clock (CLK), the burst read data are terminated and the data bus goes to high impedance after the /CAS latency from the burst stop command. T0 T1 T2 T3 T0 T4 T5 T1 T6 T7 T9 T8 T2 T10 T3 T11 T4 Burst length = 8 T5 CLK /CLK CKE /CAS latency = 2 Command READ BST Hi-Z DQ Q1 Q2 Q3 Q4 Q1 Q2 Q3 /CAS latency = 2.5 Command READ BST Hi-Z DQ Q4 (When tRAS is satisfied) Remark BST means Burst Stop command 34 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 12.2 Precharge Termination in Read Cycle During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge command. The precharge command can be issued after tRAS (MIN.) is satisfied. Burst length = Full page T0 T1 T2 T3 T4 T5 CLK /CLK CKE /CAS latency = 2 Command READ PRE Hi-Z Q1 DQ Q2 Q3 Q4 Q1 Q2 Q3 /CAS latency = 2.5 Command READ PRE Hi-Z DQ Q4 (When tRAS is satisfied) Preliminary Data Sheet 35 PD45D128442, 45D128842, 45D128164 12.3 Precharge Termination in Write Cycle During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same banks. In order to write the last input data to the memory cell correctly, tDPL (MIN.) must be satisfied. When the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle must be masked DM. Burst length = 8 T0 T1 T2 T3 T4 T5 tDPL = 1 cycle CLK /CLK CKE /CAS latency = 2, 2.5 , , ,,, ,,,, ,,, Command Write PRE DQS DQ D1 D2 DM 36 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 13. Electrical Specifications * All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute Power on sequence and CBR (auto) Refresh before proper device operation is achieved. 13.1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit VCC, VCCQ -0.5 to +3.6 V Voltage on any pin relative to VSS VT -0.5 to +3.6 V Short circuit output current IO 50 mA Power dissipation PD 1 W Storage temperature Tstg -55 to + 125 C Voltage on power supply pin relative to VSS Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 13.2 Recommended Operating Conditions Parameter Symbol Supply voltage Condition MIN. TYP. MAX. Unit VCC 2.375 2.5 2.625 V Supply voltage for DQ, DQS VCCQ 2.375 2.5 2.625 V Input reference voltage VREF 1.1875 1.25 1.3125 V VREF VTT VREF - 0.04 VREF + 0.04 V High level dc input voltage VIH (DC) VREF + 0.18 Vcc + 0.3 V Low level dc input voltage VIL (DC) -0.3 VREF - 0.18 V TA 0 70 C Termination voltage Operating ambient temperature 13.3 Pin Capacitance (TA = 25 C, f = 1 MHz) Parameter Symbol Condition MIN. TYP. MAX. Unit 5 Input capacitance CI1 A0 - A11, BA0, BA1 2.5 CI2 CLK, /CLK, CKE, /CS, /RAS, /CAS, /WE, DM, LDM, UDM 2.5 5 pF Data input/output capacitance CIO1 DQS, LDQS, UDQS 4 6.5 pF CIO2 DQ0 - DQ15 4 6.5 pF Preliminary Data Sheet pF 37 PD45D128442, 45D128842, 45D128164 13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Operating current ICC1 Test condition /CAS latency Grade x4 x8 x16 tRC tRC(MIN.), Io = 0 mA, CL = 2 -C10 110 120 135 -C12 95 100 115 -C10 120 130 145 -C12 105 110 125 CL = 2.5 Precharge standby current in power down mode ICC2P Precharge standby current in Non power down mode ICC2N Active standby current in power down mode ICC3P Active standby current in Non power down mode ICC3N Operating current ICC4 Maximum Unit Notes mA 1 CKE VIL(MAX.), tCK = 10 ns 25 mA CKE VIH(MIN.), tCK = 10 ns, /CS VIH(MIN.), 40 mA CKE VIL(MAX.), tCK = 10 ns 45 mA CKE VIH(MIN.), tCK = 10 ns, /CS VIH(MIN.), 50 mA Input signals are changed one time during 20 ns. Input signals are changed one time during 20 ns. (Burst mode) tCK tCK(MIN.), Io = 0 mA, CL = 2 -C10 -C12 125 140 165 CL = 2.5 -C10 190 210 250 -C12 150 170 200 All bank activated 150 170 200 mA 2 3 CBR (auto) refresh current ICC5 tRC tRC(MIN.) 290 mA Self refresh current ICC6 CKE 0.2 V 2 mA Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured condition that addresses are changed only one time during tCK(MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured condition that addresses are changed only one time during tCK(MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. MAX. Input leakage current II(L) VI = 0 to 3.6 V, all other pins not under test = 0 V -5 5 A Output leakage current IO(L) DOUT is disabled, VO = 0 to VCCQ + 0.3 V -5 5 A High level output voltage VOH IO = -12 mA Low level output voltage VOL IO = 12 mA 38 VTT + 0.6 V VTT - 0.6 Preliminary Data Sheet Unit Notes V PD45D128442, 45D128842, 45D128164 13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted) 13.6.1 Test Conditions Parameter Symbol Value Unit Input Reference voltage (Input timing measurement reference level) VREF VCCQ x 0.5 V Termination voltage (Output timing measurement reference level) VTT VREF V High level ac input voltage VIH(ac) VREF + 0.35 V Low level ac input voltage VIL(ac) VREF - 0.35 V Input signal slew rate SLEW 1 V/ns Notes 1 2 Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL(ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)VIL(ac))/ t VTT = 0.5 x VCCQ RS = 25 RT = 25 Output CLOAD = 30 pF Preliminary Data Sheet 39 PD45D128442, 45D128842, 45D128164 13.6.2 Timing Diagram ,, ,, ,,,, ,, ,, ,,,, ,,,,,,,, ,,, ,, , , ,, ,, ,, ,, tCK CLK /CLK tCH tCL VREF + 0.35 V VREF VREF - 0.35 V tCKSK tIS Command (Input) tIH tIH VREF + 0.35 V Valid Valid VREF - 0.35 V tIS Address (Input) tIS tIH tIS tIH VREF + 0.35 V Valid Valid VREF - 0.35 V tRPRE DQS (Output) (CL = 2) tDQSCK tDQSV VTT tDQSQ tAC tDV DQ (Output) (CL = 2) VTT Valid tRPRE tDQSCK tDQSV DQS (Output) (CL = 2.5) tDQSQ tAC tDV Valid tRPST tDQSCK VTT tDQSQ tAC tDV DQ (Output) (CL = 2.5) tRPST tQSCK Valid VTT tDQSQ tAC tDV Valid tDQSS VREF + 0.35 V DQS (Input) tWPRE VREF VREF - 0.35 V tWPRES tWPREH tWPST VREF + 0.35 V DQ and DM (Input) VREF Valid VREF - 0.35 V tDS, tDH, tDMS tDMH 40 Preliminary Data Sheet Valid PD45D128442, 45D128842, 45D128164 13.6.3 Synchronous Characteristics Parameter Symbol -C10 MIN. Frequency fCK Clock cycle time tCK -C12 MAX. MIN. Unit MAX. CL = 2.5 125 100 MHz CL = 2 100 83 MHz CL = 2.5 8 15 10 15 ns CL = 2 10 15 12 15 ns Parameter Symbol MIN. MAX. Unit CLK high time tCH 0.45 0.55 CLK CLK low time tCL 0.45 0.55 CLK CLK to /CLK skew tcksk 0.015 CLK Data access time from CLK tAC -0.1 x tCK 0.1 x tCK ns Data Strobe edge to CLK egde skew tDQSCK -0.1 x tCK 0.1 x tCK ns Data Strobe egde to Output Data edge skew tDQSQ -0.075 x tCK 0.075 x tCK ns tDV 0.3 x tCK ns Output Data Strobe valid window tDQSV 0.3 x tCK ns DQS entry to Low-Z to first rising edge delay (read) tRPRE 0.9 x tCK 1.1 x tCK ns DQS last falling edge to entry to Hi-z delay (read) tRPST 0.4 x tCK 0.6 x tCK ns Data to Strobe setup time tDS 0.075 x tCK ns Data to Strobe hold time tDH 0.075 x tCK ns Data mask to Strobe setup time tDMS 0.075 x tCK ns Data mask to Strobe hold time tDMH 0.075 x tCK ns CLK to DQS write preamble setup time tWPRES 0 ns CLK to DQS write preamble hold time tWPREH 0.25 x tCK ns DQS entry to Low-Z to first rising edge delay (write) tWPRE 0.4 x tCK 1.1 x tCK ns DQS last falling edge to entry to Hi-Z delay (write) tWPST 0.4 tCK 0.6 x tCK ns CLK to first rising edge of DQS tDQSS 0.75 x tCK 1.25 x tCK ns Input setup time tIS 0.15 x tCK ns Input hold time tIH 0.15 x tCK ns Transition time (CLK, /CLK, DQS, DQ, DM) tTD 0.5 ns Transition time (CMD, Add) tT 0.5 ns Output Data valid window Note Remark If the result of the nominal calculation contains more than one decimal place, the result is rounded up to the nearest decimal place. Preliminary Data Sheet 41 PD45D128442, 45D128842, 45D128164 13.6.4 Synchronous Characteristics Example Symbol fCK = 125 MHz, fCK = 100 MHz, tCK = 8 ns fCK = 83 MHz, tCK = 10 ns Unit tCK = 12 ns MIN. MAX. MIN. MAX. MIN. MAX. tCH 3.6 4.4 4.5 5.5 5.4 6.6 ns tCL 3.6 4.4 4.5 5.5 5.4 6.6 ns 0.2 ns tAC -0.8 0.8 -1 1 -1.2 1.2 ns tDQSCK -0.8 0.8 -1 1 -1.2 1.2 ns tDQSQ -0.6 0.6 -0.8 0.8 -0.9 0.9 ns tCKSK 0.2 0.2 tDV 2.4 3 3.6 ns tDQSV 2.4 3 3.6 ns tRPRE 7.2 8.8 tRPST 3.2 4.8 tDS 0.6 0.8 0.9 ns tDH 0.6 0.8 0.9 ns 9 11 4 6 10.8 13.2 4.8 7.2 ns ns tDMS 0.6 0.8 0.9 ns tDMH 0.6 0.8 0.9 ns tWPRES 0 0 0 ns tWPREH 2.0 tWPRE 3.2 8.8 4 11 4.8 13.2 ns tWPST 3.2 4.8 4 6 4.8 7.2 ns tDQSS 6.0 10.0 7.5 12.5 9.0 15.0 ns tIS 1.2 1.5 1.8 ns tIH 1.2 1.5 1.8 ns tTD 0.5 0.5 0.5 ns tT 0.5 0.5 0.5 ns 2.5 3.0 ns 13.6.5 Asynchronous Characteristics Parameter Symbol -C10 MIN. ACT to ACT delay (Same bank), -C12 MAX. MIN. Unit MAX. tRC 70 84 ns ACT to PRE delay tRAS 50 PRE to ACT delay tRP 20 24 ns ACT to READ/WRIT delay tRCD 20 24 ns ACT to ACT delay (Different bank) tRRD 20 24 ns CLK related with last Din to PRE delay tDPL 10 12 ns CLK related with last Din to ACT/REF delay tDAL 30 36 ns Mode register set cycle time tRSC 2 2 CLK Refresh time tREF REF to REF delay 120,000 60 120,000 ns (Auto precharge) 42 64 Preliminary Data Sheet 64 ms Note CKE /CLK Preliminary Data Sheet DQ DQS DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS T2 T3 T4 T5 tRC tRPRE T6 T7 T8 T9 T10 tIH T11 T12 T13 VTT VTT L tIS Hi-Z tIS tIH tIS tIH tCH Activate Command for Bank A tCK Hi-Z tCL tCH tRCD Read Command for Bank A tRAS tDV tAC tAC tDQSQ tDQSV tDV tDQSQ tDQSV tDQSCK tDQSCK tDQSCK tDQSCK tRPST ,,, ,,, ,,, ,,,, ,,, ,,,, ,, ,,, ,,,, ,,, ,,,, , ,,, ,, , ,,, , ,,, ,,,, ,,, ,,, ,, ,,,,, ,,, ,,,, , ,,, ,,, , ,, ,,, ,,, , ,,, ,,, ,,,,,, ,,, ,,,,,,,,,, ,,, ,,,,,,,,,,,, , , , ,, , ,, tCL T1 tAC tDV Precharge Command for Bank A tAC tDV tDQSQ tDQSQ tDQSV tRP Activate Command for Bank A ,,, CLK T0 tCK AC Parameters for Read Timing 1 (Manual Precharge, Burst Length = 4, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 43 Preliminary Data Sheet DQ DQS DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK VTT VTT Hi-Z Hi-Z tIS tCL tCH tIH tIS tIH tIS tCH tCL T1 Activate Command for Bank C tCK T0 tCK tRCD T2 T5 Auto Precharge Start for Bank C T4 tRRD Bank C Read Command with Auto Precharge tRAS T3 tRPRE T7 T8 tRC tDQSV tAC tDV tAC tDV tDQSQ tDQSQ tDQSV tDV tAC Activate Command for Bank D tAC tDV tDQSQ tDQSQ tDQSV tRPST tDQSCK tDQSCK tDQSCK tDQSCK T6 ,,, 44 T9 T10 tIH T11 T12 T13 Activate Command for Bank C ,, ,,, ,,, ,, ,,, ,,,, ,,, ,,,, , ,,, ,, ,,, ,,,, , ,,, ,,, ,,,, , ,,, ,, ,,, , , , , ,,, ,,, , ,, ,,,, , ,, , ,,, ,, , ,,, ,,, , , , , ,,, ,,, ,,, , ,,,,,,,,,,, ,,, , ,, ,,, ,,, ,,,,,,,,,,, ,,, , , ,,, AC Parameters for Read Timing 2 (Auto Precharge, Burst Length = 4, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 PD45D128442, 45D128842, 45D128164 Relationship between Frequency and Latency Speed version Clock cycle time [ns] -C10 -C12 8 10 10 12 Frequency [MHz] 125 100 100 83 /CAS latency 2.5 2 2.5 2 3 2 3 2 /RAS latency (/CAS latency + [tRCD]) 5.5 4 5.5 4 [tRC] 10 7 9 7 [tRAS] 7 5 6 5 [tRRD] 2 2 2 2 [tRP] 3 2 3 2 [tDPL] 2 1 2 1 [tDAL] 4 3 4 3 [tRSC] 2 2 2 2 [tRCD] Preliminary Data Sheet 45 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Hi-Z Hi-Z tIS tRCD tRRD tWPRES tDS tDH tDQSS tWPREH tRC Bank C Activate Activate Write Command Command Command for Bank C with Auto Precharge for Bank B tIS tIH tIS tIH tRAS Bank B Write Command without Auto Precharge tRCD tRC tDAL tDPL tWPST Activate Precharge Command Command for Bank C for Bank B Auto Precharge Start for Bank C tRP tIH Activate Command for Bank B ,, ,,, ,, ,, ,, ,,, , , ,, ,, ,, , , , ,, ,,, , ,,, ,, ,, , ,, ,, , , , ,, , ,,, , , , , ,, , , , ,, , , , , , ,, ,, ,, ,,, ,, ,, ,, ,,,, ,,,,,,,,,,,,,, ,,,, T1 ,,, ,,, ,,, ,,,,,, 46 T0 AC Parameters for Write Timing (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 VTT H Hi-Z T1 T2 T3 T4 tRSC T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet DQ DQS DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK VTT Hi-Z All Banks Precharge Command tRP Mode Register Set Command ADDRESS KEY Activate Command is valid ,, , , ,,,,,,,, ,, , , ,,,,,,,, ,, ,,,,,,,,,,,, , , ,,,,,,,, ,,, ,, ,,,,,,,,, ,,, , ,,,,,,,, ,, ,,, ,, ,, , ,,,,,,,,, ,,,,,,,, ,,,,,,,,,,,, ,,, ,, ,,,,,,,,, ,,,,,,,,,,,, CLK T0 Mode Register Set (Burst Length = 4, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 47 48 Preliminary Data Sheet VTT VTT DQS DQ DM ADD A10 BA0 BA1 /WE /CAS T2 T3 T4 Hi-Z Hi-Z T5 T6 T7 T8 T9 More than 200 cycle is necessary All Banks Extended Mode Mode Refresh Precharge Register Set Register Set Command Command Command Command is necessary is necessary (DLL enable / (DLL reset) disable) is necessary is necessary tRSC tRSC tRP ADDRESS KEY ADDRESS KEY Low level is necessary T1 T10 T12 T13 T14 tRC Refresh Command is necessary 2 refresh cycles are necessary T11 T15 T16 T17 tRC Mode Register Set Command is necessary ADDRESS KEY tRSC T18 T19 T20 Activate Command ,, ,, ,, ,, ,,, ,,,, ,, , ,, ,, ,, ,, ,,, , ,,,, ,, , ,, ,, ,,, , ,,,, ,, ,, ,, ,,,,,,,, , , ,, ,, ,, ,,,,,,,, ,, , , , , ,, ,, ,, ,,,,,,,,, ,, ,, ,,,,,,,,,,,, , ,,,,,,, ,, ,, ,,,,,,,,,,,, /RAS /CS CKE /CLK CLK T0 Power On Sequence and CBR (auto) Refresh PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet L DQ VTT DQS VTT Hi-Z Hi-Z Activate Command for Bank A RAa ADD DM RAa L BA0 T2 A10 L H T1 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T3 CAa T5 Read Command for Bank A T4 T6 /CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 2.5) Only /CS signal needs to be issued at minimum rate T8 T9 QAa1 QAa2 QAa3 QAa4 T7 CAb T11 Write Command for Bank A T10 T13 DAb1 DAb2 DAb3 DAb4 T12 T14 T15 T16 T17 T19 Precharge Command for Bank A T18 T20 T21 PD45D128442, 45D128842, 45D128164 49 50 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet Hi-Z DQ VTT DQS VTT PRECHARGE STANDBY Power Down Mode Entry Precharge Command for Bank A Hi-Z Power Down Mode Exit Activate Command for Bank A RAa ADD DM RAa tIS A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Read Command for Bank A CAa QAa1 QAa2 QAa3 QAa4 ,,,,,, , ,,,,,,, ,,,,, , , ,,,,,, ,, , ,,,,,,, ,,,,, , , ,,,,,,, ,,,,,, , ,, , ,,,,, , ,,,,,,, , ,,,, ,, ,,,,,,, ,, ,,,, ,, ,,,,,,, , ,, ,,,, ,,,,,,,, ,, ,,,, ,,,,,,,,,,,, T0 Power Down Mode (Burst Length = 4, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet DQ DQS DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK VTT VTT tRP Precharge CBR (auto) Refresh Command is necessary Hi-Z Hi-Z H tRC CBR (auto) Refresh tRC Activate Command Read Command Q1 Q2 ,, ,, ,,,, ,,,, ,, ,, , ,, ,, ,,,, ,,,, ,, ,, , , ,, , ,,, , ,, , ,, , ,,,, ,, , ,,,, ,,, ,, , , ,, , ,,,,,,,, , ,, ,, ,,,,,,,,, ,, ,, , ,,,,,,,, ,,, , ,, ,,,,,,,,,,,, ,,,,,,,,, , ,, ,,,,,,,,,,,, T0 CBR (auto) Refresh PD45D128442, 45D128842, 45D128164 51 52 Preliminary Data Sheet DQ VTT DQS VTT DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK Hi-Z Hi-Z Precharge Command is necessary T1 T2 tRP T4 Self Refresh Entry T3 Tn+1 Self Refresh Exit Tn Tm Tm+2 Self Refresh Self Refresh Entry Exit (or Activate Command) Tm+1 Next Clock Enable 200 cycles Tn+2 Tj Next Clock Enable Activate Command 200 cycles Tk Tj+1 Tj+2 ,, ,, ,,, ,,, ,,, ,,, ,, ,, ,,,,, ,,,, ,,, ,, ,, , ,,,,, , ,, ,,,, ,,, ,, , ,,,,, , ,, ,,,, ,, ,, ,,,,,,,,, ,,, ,,,,,,,,,, ,, ,,,,,,,,, ,,, ,, ,, ,,,,,,,,,, ,,,,,,,,,, ,, ,,,,,,,,,,,, ,,,,,,,,,,,, CLK T0 Self Refresh (Entry and Exit) PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet RAa ADD VTT VTT DQS DQ Activate Command for Bank A Hi-Z Hi-Z RAa H A10 BA0 BA1 /WE /CAS /RAS DM T1 T2 CAa T3 T4 CAb T5 CAc T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Read Command for Bank A Read Read Command Command for Bank A for Bank A Precharge Command for Bank A Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 RAd RAd Read Command for Bank A CAd QAd1 QAd2 QAd3 QAd4 ,,,,,,,,,,,, , , , ,, ,, ,, ,,,,,, ,, , , , ,, , ,, ,, , ,, , ,,,,,, , , , , ,, ,,,,,, ,, , ,, , ,, ,, , ,,, , ,, , , ,, ,,, , ,,,, ,, , ,, , ,, , ,,,,,, ,,,,,, ,, ,, ,, , ,, ,,,,,, , ,,,,,,,,,,,, ,,,,,,,,,,,, CKE /CLK CLK /CS T0 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 53 54 Preliminary Data Sheet VTT VTT DQS DQ T1 Activate Command for Bank A Hi-Z Hi-Z RAa ADD DM RAa H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T2 CAa T4 Read Command for Bank A T3 CAc T7 T8 T9 T10 T11 Precharge Command for Bank A T12 RAa RAa Activate Command for Bank A QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 T6 Read Read Command Command for Bank A for Bank A CAb T5 T13 T14 T15 T16 T17 T18 T19 T20 T21 Read Command for Bank A CAa QAd1 QAd2 QAd3 QAd4 ,,,,,,,,,,,,, ,, ,,, ,, ,, ,, ,, ,,,,, ,,, , ,, , ,, ,,, ,,, ,, ,, ,, ,, ,,,,, , ,,, , ,, ,,, ,, ,, ,, ,,,,, , ,,,, ,,, ,, ,, ,, , ,, ,, ,,,, ,, ,,,, ,,, ,,,, ,, ,, , ,, ,, ,,,,, ,, ,, ,, ,,,, , ,,,, ,, ,, ,,,, ,, ,, ,,,,,,,,,,,, ,,,,,,,,,,,, Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 T1 T2 CDa T3 T4 CDb T5 CDc T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Activate Command for Bank D Hi-Z RDa ADD DM RDa Hi-Z H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Write Command for Bank D Write Command for Bank D Write Command for Bank D DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 Precharge Command for Bank D Activate Command for Bank D RDd RDd Write Command for Bank D CDd DDd1 DDd2 DDd3 DDd4 ,,,,,,,,,,,, , , , ,,, ,, ,, ,,,,, ,, , , , ,, , ,,, ,, , ,, , ,,,,, , , , ,,, , ,,, ,,,, ,,,,, ,, ,, , ,, ,,,,, ,, , , ,,,, ,, , ,, , ,,, ,, ,, ,, ,, ,,,,, ,,,, ,, ,, ,, ,, , , ,,,, ,,, ,,,, ,,,, ,,,,,,,,,,,, ,,, ,,,,,,,, T0 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 55 56 T1 T2 T3 CDa T4 T5 CDb T6 CDc T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Activate Command for Bank D Hi-Z Hi-Z RDa ADD DM RDa L H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Write Command for Bank D Write Command for Bank D Write Command for Bank D DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 Precharge Command for Bank D Activate Command for Bank D RDd RDd Write Command for Bank D CDd DDd1 DDd2 DDd3 DDd4 ,,,,,,,,,,,, ,, , , ,, ,, , ,,, ,, ,, ,,, ,, ,, ,, , ,,, ,, , ,, ,, ,,, , , ,, ,,, ,,,, , ,,,, ,, ,, , ,,, ,, ,,, ,, , ,,, ,, ,, ,,, ,,,, , ,,, ,, ,, ,,, , ,, ,, ,, ,, ,, ,,, , ,, ,, ,, ,, ,, ,,, ,,,,,,,,,,,, ,,,, ,,,,, ,, ,,,, ,,,,,,, T0 Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet DQ VTT DQS VTT DM Activate Command for Bank D Hi-Z Read Command for Bank D T5 T6 CBa T7 T8 T9 T10 T11 T12 RDb RDb Activate Command for Bank B Precharge Command for Bank D Read Command for Bank B Activate Command for Bank D QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 RBa CDa RDa T4 ADD T3 RBa T2 RDa Hi-Z H T1 A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T13 T14 T15 T16 T17 T18 T19 T20 T21 Read Command for Bank D CDb QDb1 QDb2 QDb3 QDb4 QDb5 QDb6 QDb7 QDb8 ,,,,,,,,,,,, ,, ,, ,, ,, , ,,, ,,, , , ,, ,, ,, , ,,, ,, , ,, ,,, ,, , ,, , ,, , ,, , ,, ,,, ,, ,,, , , , , ,, ,,,, ,, ,,, ,, ,, , ,,,, , ,,,, ,,, ,, , , ,, ,,,, ,,,, , ,, ,,,,,,,,,,,,, ,, , , ,, ,,,, ,,,, ,,,,,,,,,,,, Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 57 58 Preliminary Data Sheet VTT VTT DQS DQ T1 Activate Command for Bank B Hi-Z RBa ADD DM RBa Hi-Z H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T2 CBa RAa RAa T4 T5 Activate Command for Bank A Read Command for Bank B T3 CAa T7 T8 T9 T10 T11 T12 T13 T14 RBb RBb Read Command for Bank A Precharge Command for Bank B Activate Command for Bank B QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 T6 T15 T16 T17 T18 T19 T20 T21 Read Command for Bank B CBb Precharge Command for Bank A QBb1 QBb2 QBb3 QBb4 QBb5 QBb6 QBb7 ,,,,,,,,,,,, ,, ,, ,, , ,, ,, , ,, , ,, ,, , ,, , ,,, ,, ,, ,, , ,, ,, ,, , ,, ,, ,, ,, , ,, ,, ,, ,, , ,,, ,, , , , , , , , , , , , ,, ,, ,, ,, ,, ,, , , , ,, ,, ,, ,, ,, ,, ,, , , , , , , , , , , ,,,,,,,,,,,, , ,, ,, ,, ,, ,, ,, ,, ,,,,,,,,,,,, Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet DQ DQS DM VTT VTT Activate Command for Bank A Hi-Z Hi-Z Write Command for Bank A T5 CDa T6 T7 T8 T9 T10 T11 RAb RAb Activate Command for Bank D Write Command for Bank D Precharge Command for Bank A Activate Command for Bank A DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 RDa CAa RAa T4 ADD T3 RDa T2 RAa L H T1 A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 Precharge Command for Bank D Write Command for Bank A CAb ,,,,,,,,,,,, ,, ,, ,, ,, ,, ,, ,, ,,,, ,, ,, ,, ,, , , ,, ,, , ,, ,,,, , , , ,,,, , ,, ,, ,, ,, ,, ,, ,, ,,,, ,, ,, , ,, ,, , ,, ,, ,,,, , , , , ,, , , ,,,,, ,,, , , , , ,, , , ,,,,, ,,,,,,,,,,,, ,,, ,, ,,, ,,, ,, ,,, Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 59 60 T1 T2 T3 CAa T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT DQ DQS VTT Activate Command for Bank A Hi-Z Hi-Z Hi-Z RAa ADD DM RAa L H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Activate Command for Bank D Write Command for Bank A CDa RAb RAb Write Command for Bank D Precharge Command for Bank A Precharge Command for Bank D Activate Command for Bank A DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 RDa RDa Write Command for Bank A CAb DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 ,,,,,,,,,,,, , , , , , , ,, ,, ,, ,, ,, ,, ,,, ,, , , ,,,, , ,, ,, ,, ,, ,,, , ,, ,,,, ,, ,, , ,,,, , ,, ,, ,, ,, , , , ,,,, ,,,, ,,, ,, ,, , , ,, ,,,, ,, ,, ,, ,, , ,, , ,,,, ,,,, ,, ,,,, , ,,, T0 Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 CKE /CLK Preliminary Data Sheet Hi-Z VTT VTT DQS DQ Activate Command for Bank A Hi-Z RAa ADD DM RAa A10 BA0 BA1 /WE /CAS /RAS /CS H T1 T2 CAa T3 T4 T6 T7 T8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 T5 T9 CAb T10 T12 Word Masking T11 T13 CAc T14 T15 T16 T18 T19 T20 QAc1 QAc2 QAc3 QAc4 QAc5 QAc6 QAc7 QAc8 T17 T21 Read Command for Bank A Hi-Z at the end of wrap function Read Command for Bank A DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 0-Clock Latency Write Command for Bank A DAb1 ,,,,,,,, ,,, ,,,,, , ,,,, , ,,, ,, ,,,,, , ,,,, ,,, ,,,,, , , ,, , ,, , ,,,, ,,,,, ,,,, ,,,, ,,, ,,,,, ,,,, ,, ,, ,,,, ,,,, ,,,, ,,,,,,, ,,,, ,, ,, ,,,,,,, , ,,, ,,,,,,, ,,,, CLK T0 Read and Write (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 61 62 Preliminary Data Sheet VTT VTT DQS DQ T1 Activate Command for Bank A Hi-Z RAa ADD DM RAa Hi-Z H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T2 CAa T4 Read Command for Bank A T3 T5 T7 T8 T9 T10 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 T6 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Write Command for Bank A CAb DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 0-Clock Latency DAb1 Word Masking Read Command for Bank A CAc QAc1 QAc2 QAc3 ,,,,,,,,,,,, , ,,,, ,,,,, ,,,, ,,, ,, ,,,,, , ,,,, ,,, ,,, , , , , ,, ,,,,, ,,,, ,,, ,, , ,, ,, , ,, ,, ,,,,, , ,,,, ,, ,,,, , ,,,, ,,, ,,, ,, ,, ,,,, ,,,, ,,, ,, ,, ,,,,,,,,, ,,,,,,, ,,, ,,,,,,, ,,, Read and Write (2/2) (Burst Length = 4, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 H T1 T2 CAa T3 T4 RDa T5 CDa T6 T7 T8 CDb T9 T11 CDc T10 T13 CAb T12 T15 CDd T14 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Activate Command for Bank A Hi-Z Hi-Z RAa ADD DQM RAa A10 BA0 BA1 /WE /CAS /RAS /CS CKE Read Command for Bank A Activate Command for bank D Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Read Command for Bank D Precharge Command for Bank A Precharge Command for Bank D Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Dd1 Dd2 Dd3 Dd4 Dd5 Dd6 Dd7 Dd8 RDa ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, , ,,, , , , ,, ,, ,,,, ,, ,, ,, , ,, ,, ,, ,, ,, ,,,, ,,,,, ,,,, ,, , ,, ,, ,, ,, ,,, ,,,,,, , ,, , ,, ,,, , , , ,, , ,, ,, ,, ,, ,, , ,,, ,,,,,,,,,,,,, ,, , ,,,, ,, ,,,, ,,,,,,, ,,,,, /CLK CLK T0 Interleaved Column Read Cycle (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 63 64 Preliminary Data Sheet VTT VTT DQS DQ DQM Activate Command for Bank A Hi-Z Hi-Z T5 Read Command for Bank A Activate Command for Bank D RDa CAa RAa T4 ADD T3 RDa T2 RAa L H T1 A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T7 CDa T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 CDb CDc CAb Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Db4 Dc1 Dc2 Dc3 Dc4 Ab1 Ab2 Ab3 Ab4 Ab5 Ab6 Ab7 Ab8 T6 T21 ,,,,,,,,,,,, , ,, ,,, ,, , , ,, ,, ,, , , ,, ,, ,, ,, , ,, , ,, , ,, , , ,, ,, ,, , ,, , ,,, , ,, , , ,, ,,,, ,, ,, ,, ,, ,, ,, ,, ,,, , , ,, ,, ,, ,, ,,, ,, ,, ,, ,,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, Interleaved Column Read Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet VTT VTT DQS DQ T1 Activate Command for Bank A Hi-Z Hi-Z RAa ADD DM RAa H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 CAa T3 Write Command for Bank A T2 RBa RBa T5 T6 CBa T7 T8 T9 T10 CBb T11 T12 T13 T14 T15 T16 T17 T18 T19 Activate Command for Bank B Write Command for Bank B Write Command for Bank B CAb CBd Write Command for Bank B Write Command for Bank A Write Command for Bank B Precharge Command for Bank A Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8 CBc Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 T4 T20 T21 Precharge Command for Bank B ,,,,,,,,,,,, ,, ,, ,, ,, ,, ,, ,, ,, ,,, , , ,, ,, ,, ,, ,, ,, ,, ,, , ,, ,, ,,, ,, ,, ,,,, ,, ,, ,, , ,, , ,, ,, , ,, ,,, , ,, ,, ,, ,, ,, ,, ,, ,,, , ,, ,, ,,,, , , ,, , , , ,, , ,, , , , ,,, ,, , , , , ,, ,,, ,, , , ,,,, ,, , , , , , , ,, ,,,, ,,,, ,, Interleaved Column Write Cycle (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 65 T2 T3 CAa T4 T5 T6 T7 CBa T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Activate Command for Bank A Hi-Z Hi-Z CBb CBc CAb CBd Write Command for Bank A Activate Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank A Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Ba1 Ba2 Ba3 Ba4 Bb1 Bb2 Bb3 Bb4 Bc1 Bc2 Bc3 Bc4 Ab1 Ab2 Ab3 Ab4 Bd1 Bd2 Bd3 Bd4 Bd5 Bd6 Bd7 Bd8 RBa RAa ADD DQM RBa RAa H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK ,,,,,,,,,,,, , , ,, ,, ,, , ,, , ,, ,, , ,, , ,, , , ,, ,, ,, , , ,, ,, ,, ,, , , ,, , , , ,, ,, ,, ,, , ,, , ,, , ,, , , , , , , , , , ,, , ,, ,, ,, ,, ,, , ,, , , , , , , , , ,,,,,,,,,,,, , ,, ,, ,, ,, ,, ,, ,, , , ,,,, , ,,,,,,,,,,,, ,,,, , T1 , 66 T0 Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 T1 T2 CAa T3 T4 T5 T6 CDa T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Bank D Read Command with Auto Precharge Activate Command for Bank D Bank A Read Command without Auto Precharge Activate Command for Bank A Hi-Z Hi-Z RDa RAa ADD DM RDa RAa H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Auto Precharge Start for Bank D Bank A Read Command with Auto Precharge CAb CDb Auto Precharge Start for Bank A Activate Command for Bank D RDb RDb Bank D Read Command with Auto Precharge Auto Precharge Start for Bank D Activate Command for Bank A RAc RAc CAc Bank A Read Command with Auto Precharge ,,,,,,,,,,,, ,, ,,,, ,, ,,, , ,, , , ,,, ,, , ,,,, ,, ,,, ,,, , ,, , , ,,, ,, ,, ,, , ,, ,, , ,, ,, , ,, ,,, ,, , ,, , , ,, ,,, , ,, , ,,, , ,, ,, ,, , ,,,, ,, , , ,, ,, ,,, ,,, ,,, ,, ,, ,, ,, ,,, ,,, ,,, ,,,,,,,,,,,, ,,,,,,,,,,,, T0 Auto Precharge after Read Burst (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 67 68 T1 T2 T3 CAa T4 T5 T6 T7 CDa T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet DQ VTT DQS VTT Activate Command for Bank A Hi-Z Hi-Z Bank A Read Command without Auto Precharge Activate Command for Bank D RDa RAa ADD DM RDa RAa H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Bank D Read Command with Auto Precharge Auto Precharge Start for Bank D Bank A Read Command with Auto Precharge CAb Activate Command for Bank D Auto Precharge Start for Bank A RDb RDb Bank D Read Command with Auto Precharge CDb ,,,,,,,,,,,, ,, ,, ,, ,,, ,,, ,, ,, ,, ,, ,,,, ,, ,,, ,,, ,, , ,,, ,, ,, ,, ,, ,,, ,,, ,, ,, , , , ,,,, ,, ,, ,,, ,, ,,, ,, ,,, ,,,, ,, ,,, , ,,,,, ,, ,, ,, ,,,,,,,,,,,,, ,,,, ,, ,,, ,, ,,,,,, ,, ,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,, T0 Auto Precharge after Read Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 T1 T2 CAa T3 T4 T5 T6 CDa T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet VTT VTT DQS DQ Bank D Write Command with Auto Precharge Activate Command for Bank D Bank A Write Command without Auto Precharge Activate Command for Bank A Hi-Z Hi-Z RDa RAa ADD DM RDa RAa L H A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Bank A Write Command with Auto Precharge CAb CDb Auto Precharge Start for Bank D CAc Bank A Write Command with Auto Precharge Activate Command for Bank A RAc RAc Auto Precharge Start for Bank A Bank D Write Command with Auto Precharge Activate Command for Bank D RDb RDb ,,,,,,,,,,,, ,, ,,,, ,, ,,, , ,,, , ,,, ,,,, , ,,, ,, ,, ,, ,, ,,, ,,, , , , , ,, ,, ,, ,, ,,, ,, ,,, ,, ,, , , , , ,, ,,,,,,,,,,,,, ,, ,, , ,, , ,,, ,, , ,,, ,, ,,, , ,,, ,,,, , ,, , , , , , , ,, ,, ,, ,, ,, ,, ,,,, ,,, , ,, ,,,,,,,,,,,, ,,, ,, T0 Auto Precharge after Write Burst (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 69 70 Preliminary Data Sheet VTT VTT DQS DQ DM Activate Command for Bank A Hi-Z Hi-Z T5 Bank A Write Command without Auto Precharge Activate Command for Bank D RDa CAa RAa T4 ADD T3 RDa T2 RAa H T1 A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T6 CDa T8 Bank D Write Command with Auto Precharge T7 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Auto Precharge Start for Bank D Bank A Write Command with Auto Precharge CAb CDb Bank D Write Command with Auto Precharge Auto Precharge Start for Bank A Activate Command for Bank D RDb RDb ,,,,,,,,,,,, ,, ,, ,, ,, ,, ,, ,, ,,,, ,,,, , , ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,, ,, ,, ,, ,, ,, ,, ,,,, ,, ,, ,,, , , ,, , ,, , , ,,, ,,,, ,, ,,, ,,,,,,,,,,,, , ,,, ,,, ,,,, ,, ,,,, ,,, Auto Precharge after Write Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 Preliminary Data Sheet VTT VTT VTT VTT UDQS Lower DQ Upper DQ Activate Command Hi-Z Hi-Z Hi-Z Hi-Z H T0 T2 Read Command T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Lower Byte Lower Byte not Write not Write Upper Byte not Write Read Command ,,,,,,,,,,,, , ,, ,,,, ,,,, ,,,,, , ,, ,,,, ,, ,,,, ,,, ,,,,, , , ,,,, ,,, ,,,,, , ,, ,,,, ,,, ,,,,, ,,, , ,,,, ,,, ,,,,, ,, ,,,,,,,,,,,, ,,,, ,,, ,,,,, ,,,,,, ,,,,, ,,,,,, ,,,,, LDQS UDM LDM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK Byte Write Operation (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 71 72 T1 T2 CAa T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Preliminary Data Sheet DQ DQS DM ADD A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK VTT VTT Activate Command for Bank A Hi-Z tRAS Precharge PRE Command Command for Bank A Termination Write Command for Bank A DAa1 DAa2 DAa3 DAa4 tRP Activate Command for Bank A RAb RAa Write Mask RAb RAa Hi-Z H tRAS Read Command for Bank A CAb Precharge Command for Bank A tRP Activate Command for Bank A QAb1 QAb2 QAb3 QAb4 QAb5 QAb6 RAc RAc PRE Command Termination ,,,,,,,,,,,, , ,, ,, ,, ,, ,, , , ,,, , ,,,, , , ,, ,, ,, ,, ,, ,, ,,, , ,, ,, ,,, ,, ,, ,, ,, , ,, ,, ,, ,, ,, ,, ,, , , , , ,, , ,, ,, ,,,, ,,, ,, , , ,, ,,, ,, ,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,, T0 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2) PD45D128442, 45D128842, 45D128164 Write Mask T6 T7 T8 T9 T10 Preliminary Data Sheet VTT VTT DQS DQ DM Activate Command for Bank A Hi-Z Hi-Z 73 tRAS PRE Command Termination Write Command for Bank A Precharge Command for Bank A DAa1 DAa2 DAa3 DAa4 tRP Activate Command for Bank A RAb CAa T5 RAa T4 ADD T3 RAb T2 RAa H T1 A10 BA0 BA1 /WE /CAS /RAS /CS CKE /CLK CLK T0 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 tRAS Read Command for Bank A CAb Activate Command PRE Command for Bank A Termination tRP Precharge Command for Bank A QAb1 QAb2 QAb3 QAb4 QAb5 QAb6 RAc RAc ,,,,,,,,,,,, ,,,, ,,,, ,, ,, ,, ,, ,, , , ,, ,, ,,,, ,,,, ,, ,, ,, ,,,, ,, ,, ,,,, ,, ,, ,,,, ,,,, ,, , , ,, ,, ,, ,,,, ,, ,,, , ,,, , ,,, , , ,, ,,,,,,,,,,,, ,, ,, ,,,, ,, ,,, ,,,,,,,,,,,, PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5) PD45D128442, 45D128842, 45D128164 PD45D128442, 45D128842, 45D128164 14. Package Drawing 66PIN PLASTIC TSOP (II) (400mil) detail of lead end 66 34 F G R P L S 1 E 33 A H I J S C D M N L S K M B NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. ITEM A MILLIMETERS 22.220.05 B 0.865 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.100.05 F 1.10.1 G 1.00 H 11.760.20 I 10.160.10 J 0.800.2 K 0.145 +0.025 -0.015 L M 0.50 0.12 N 0.10 P 3 +5 -3 R S 0.25 0.600.15 S66G5-65-9LG 74 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 15. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD45D128xxx. Type of Surface Mount Device PD45D128xxxG5 : 66-pin Plastic TSOP (II) (400 mil) Preliminary Data Sheet 75 PD45D128442, 45D128842, 45D128164 [MEMO] 76 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 [MEMO] Preliminary Data Sheet 77 PD45D128442, 45D128842, 45D128164 [MEMO] 78 Preliminary Data Sheet PD45D128442, 45D128842, 45D128164 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet 79 PD45D128442, 45D128842, 45D128164 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5