The information in this document is subject to change without notice.
© 1998
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
PRELIMINARY DATA SHEET
Document No. M13852EJ1V1DS00 (1st edition)
Date Published December 1998 NS CP(K)
Printed in Japan
The mark •
••
• shows major revised points.
Description
The
µ
PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic random-
access memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
• Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• Auto refresh (CBR refresh) and self refresh
• x4, x8, x16 organization
• Byte write control (x4, x8) by DM
• Byte write control (x16) by LDM and UDM
• 2.5 V ± 0.125 V Power supply for Vcc
• 2.5 V ± 0.125 V Power supply for VccQ
• Maximum clock frequency up to 133 MHz
• SSTL_2 compatible with all signals
• 4,096 refresh cycles/64 ms
• 66-pin Plastic TSOP (II) (400 mil)
• Burst termination by Precharge command and Burst stop command
2
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Ordering Information
Part Number Organization
(word x bit x bank)
Clock frequency
CL = 2
MHz (MAX.)
Package
µ
PD45D128442G5-C10-9LG 8M x 4 x 4 100 66-pin Plas t i c TSOP (II )
µ
PD45D128442G5-C12-9LG 83 (400 mil )
µ
PD45D128842G5-C10-9LG 4M x 8 x 4 100
µ
PD45D128842G5-C12-9LG 83
µ
PD45D128164G5-C10-9LG 2M x 16 x 4 100
µ
PD45D128164G5-C12-9LG 83
3
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Part Number
µ
NEC Memory
Capacity
128: 128M bits
Organization
4: x4
8: x8
Interface
2: SSTL_2
Package
G5: TSOP (II)
V
CC
C: 2.5 V
Minimum Cycle time
10: 10 ns (100MHz)
12: 12 ns (83MHz)
Data rate
D: Double
Synchrounous
DRAM
Number of Banks
4: 4Bank
[x4, x8]
[x16] 164
Organization
16: x16
Number of Banks
and Interface
4: 4Bank, SSTL_2
PD45D128 842 G5 - C10
4
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Pin Configuration
[
µ
PD45D128442]
66-pin Plastic TSOP (II) (400mil)
8M word x 4 bit x 4 bank
Vcc
NC
VccQ
NC
DQ0
VssQ
NC
NC
VccQ
NC
DQ1
VssQ
NC
NC
VccQ
NC
NC
Vcc
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Vss
NC
VssQ
NC
DQ3
VccQ
NC
NC
VssQ
NC
DQ2
VccQ
NC
NC
VssQ
DQS
NC
VREF
Vss
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A9, A11 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ3 : Data inputs/outputs
DQS : Data strobe
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DM : DQ write mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ and DQS
VSSQ : Ground for DQ and DQS
VREF : Input reference
NC : No connection
5
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
[
µ
PD45D128842]
66-pin Plastic TSOP (II) (400mil)
4M word x 8 bit x 4 bank
Vcc
DQ0
VccQ
NC
DQ1
VssQ
NC
DQ2
VccQ
NC
DQ3
VssQ
NC
NC
VccQ
NC
NC
Vcc
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Vss
DQ7
VssQ
NC
DQ6
VccQ
NC
DQ5
VssQ
NC
DQ4
VccQ
NC
NC
VssQ
DQS
NC
VREF
Vss
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A9 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ7 : Data inputs/outputs
DQS : Data strobe
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DM : DQ write mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ and DQS
VSSQ : Ground for DQ and DQS
VREF : Input reference
NC : No connection
6
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
[
µ
PD45D128164]
66-pin Plastic TSOP (II) (400mil)
2M word x 16bit x 4 bank
Vcc
DQ0
VccQ
DQ1
DQ2
VssQ
DQ3
DQ4
VccQ
DQ5
DQ6
VssQ
DQ7
NC
VccQ
LDQS
NC
Vcc
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
Vss
DQ15
VssQ
DQ14
DQ13
VccQ
DQ12
DQ11
VssQ
DQ10
DQ9
VccQ
DQ8
NC
VssQ
UDQS
NC
VREF
Vss
UDM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
Vss
A0 - A11 : Address inputs
A0 - A11 : Row address inputs
A0 - A8 : Column address inputs
BA0, BA1 : Bank select
DQ0 - DQ15 : Data inputs/outputs
LDQS,UDQS : Data stro be
CLK, /CLK : System clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
LDM, UDM : DQ write mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ, LDQS and UDQS
VSSQ : Ground for DQ, LDQS and UDQS
VREF : Input reference
NC : No connection
7
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Block Diagram
A0 - A11, BA0, BA1
/CS
/RAS
/CAS
/WE
Column Decoder
Input & Output Buffer
Latch Circuit
Data Control Circuit
Column Decoder
Row Decoder
Memory Cell Array
Bank A
Sense Amp.
Bank B
Bank C
Bank D
Control Logic
Column
Address
Buffer
and
Burst
Counter
Row
Address
Buffer
and
Refresh
Counter
Mode
Register
Clock
Generator
DQ
CLK
/CLK
CKE
DQS
DM
DLL
CLK, /CLK
8
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
CONTENTS
1. Input/Output Pin Function ..... 10
2. Commands ..... 11
3. Simplified State Diagram ..... 15
4. Truth Table ..... 16
4.1 Command Truth Table ..... 16
4.2 DM Truth Table ..... 16
4.3 CKE Truth Table ..... 16
4.4 Operative Command Table ..... 17
4.5 Command Truth Table for CKE ..... 20
5. Initialization ..... 21
6. Programming the Mode Register ..... 22
7. Mode Register ..... 23
7.1 Burst Length and Sequence ..... 24
8. Address Bits of Bank-Select and Precharge ..... 25
9. Precharge ..... 26
9.1 Read to Precharge Command Interval ..... 26
9.2 Write to Precharge Command Interval ..... 27
10. Auto Precharge ..... 28
10.1 Read with Auto Precharge ..... 28
10.2 Write with Auto Precharge ..... 29
11. Read/Write Command Interval ..... 30
11.1 Read to Read Command Interval ..... 30
11.2 Write to Write Command Interval ..... 31
11.3 Write to Read Command Interval ..... 32
11.4 Read to Write Command Interval ..... 33
9
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12. Burst Termination ..... 34
12.1 Burst Stop Command in Read Cycle ..... 34
12.2 Precharge Termination in Read Cycle ..... 35
12.3 Precharge Termination in Write Cycle ..... 36
13. Electrical Specifications ..... 37
13.1 Absolute Maximum Ratings ..... 37
13.2 Recommended Operating Conditions ..... 37
13.3 Pin Capacitance (TA = 25 °C, f = 1 MHz) ..... 37
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) ..... 38
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) ..... 38
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted) ..... 39
13.6.1 Test Conditions ..... 39
13.6.2 Timing Diagram ..... 40
13.6.3 Synchronous Characteristics ..... 41
13.6.4 Synchronous Characteristics Example ..... 42
13.6.5 Asynchronous Characteristics ..... 42
14. Package Drawing ..... 74
15. Recommended Soldering Conditions ..... 75
10
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
1. Input/Output Pin Function
Pin nam e Input/O ut put Function
CLK, /CLK Input CLK and /CLK are t he master clock inputs. The timing referenc e poi nt for the diff erent i al
clock is when CLK and /CLK cross.
All c ont rol and address inputs except for DQ, DM and CKE are lat c hed by a ri sing edge of
CLK. By both of rising and falling edges of CLK, output DQ and DQS are validat ed.
CKE I nput CKE controls power down mode. When the
µ
PD45 D12 8xxx is not in bur st m ode and CK E
is negated, the device enters power down mode. Duri ng power down mode, CK E must
remain low.
/CS Input /CS low start s a command input c yc l e. When /CS is hi gh, commands are ignored but the
current operations will be cont inued.
/RAS, /CAS,
/WE Input As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in
conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Ref er to
the command tabl e.
A0 – A11 Input Row address is det ermined by A0 - A11 at the rising edge of CLK in active c ommand
cycle.
It does not depend on the bit organization.
Column address is det ermined by A0 - A9, A11 at the risi ng edge of CLK in read or write
com mand cycle. It depends on t he bi t organization : A 0 - A 9, A11 for x4 device, A 0 - A 9
for x8 device, A 0 - A8 for x16 device.
A10 defines precharge mode. When A 10 i s high in precharge command cycle, all banks
are precharged; when A10 is l ow, only the bank selec t ed by BA0 and BA1 is precharged.
When A10 is hi gh i n read or write c ommand cycle, precharge starts aut omatic al l y af ter the
burst access.
BA0, B A1 Input BA0, B A1 are bank selec t signals. In command cycle, BA0 and BA1 l ow select Bank A ,
BA0 low and BA1 High select bank B, BA0 high and B A1 low select bank C and then BA0
and BA1 high s el ect bank D.
DQ0 – DQ15 Input/O ut put DQ pins have the same func tion as I/ O pi ns on conventional DRA Ms .
DQS, LDQS,
UDQS
Input/O ut put Acti ve on the both edges for dat a i nput and output.
DM, LDM, UDM Input DM's are latched by both of ris i ng and falling edges of the DQS. In write mode, DM's
control byt e mask. Unlike regular S DRA Ms , DM's do not control read operat i on.
VREF Input VREF is referenc e vol t age for SSTL input buffers.
VCC, VCCQ, VSS,
VSSQ(Power Supply) VCC and VSS are power supply pins for i nternal circui ts. VCCQ and VSSQ are power supply
pins for t he output buffers .
11
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
2. Commands
Extended mode register set command
(/CS, /RAS, /CAS, /WE Low)
The
µ
PD45D128xxx has an extended mode register that defines enabling or
disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data input
pins.
After power on, the extended mode register set command must be executed to
enabling or disabling DLL.
The extended mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the
µ
PD45D128xxx can not accept
any other commands.
Fig.1 Extended mode register set
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA1
BA0
Mode register set command
(/CS, /RAS, /CAS, /WE Low)
The
µ
PD45D128xxx has a mode register that defines how the device operates. In
this command, A0 through A11, BA0 and BA1 are the data input pins.
After power on, the mode register set command must be executed to initialize the
device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the
µ
PD45D128xxx can not accept
any other commands.
Fig.2 Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
µ
PD45D128xxx has four banks, each with 4,096 rows.
This command activates the bank and the row address selected by BA0 and BA1,
and by A0 through A11 respectively.
This command corresponds to a conventional DRAM's /RAS falling.
Fig.3 Bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0,BA1
Row
Row
12
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Precharge command
(/CS, /RAS, /WE= Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0, BA1 and
A10. When A10 is High, all banks are precharged, regardless of BA0 and BA1.
When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the
µ
PD45D128xxx can't a ccept the ac tivate command to
the precharging bank during tRP (precharge to activate command period).
This command can terminate the current burst operation.
This command corresponds to a conventional DRAM's /RAS rising.
Fig.4 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Precharge select)
A10
BA0, BA1
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
This command begins the burst read operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
Read data is available after /CAS latency requirements which have been met.
And it is synchronized wi th DQS.
Fig.5 Read command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select)
Col.
A10
BA0, BA1
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
This command begins burst write operation. The bank and the burst start column
address are selected by BA0 and BA1 and by A0 through A11 respectively.
Write data must be input by DQ0 through DQ15. Byte mask data must be input
by DM, LDM, and UDM. Both data must be synchronized with DQS that is inputted
after this command.
Fig.6 Write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select) Col.
A10
BA0, BA1
13
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
bank activate command.
During tRC (refresh command to refresh or activate command period), the
µ
PD45D128xxx cannot accept any other command.
Fig.7 CBR (auto) refresh
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low.
When CKE goes high, the
µ
PD45D128xxx will exit the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.8 Self refresh entry command
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current read burst operation.
Fig.9 Burst stop command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
14
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command.
This command doesn't begin or terminate any operation.
Fig.10 No operation
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
15
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
3. Simplified State Diagram
WRITA
PRE/PALL
PRE/PALL
READA
READ
BST
PRE (Precharge termination)
PRE (Precharge termination)
ACT
MRS REF
PWDN
PDEX
SELF
IDLE
Mode
Register
Set
CBR (auto)
Refresh
BANK
ACTIVE
Self
Refresh
Power
Down
Precharge
READ
READA
POWER
ON
WRIT READ
Automatic sequence
Manual input
READ
Self
Refresh
Recovery
Bank
Activating
SREX
WRITA
READA
READA
(t
RP
)
(Burst end)
(t
DPL/
t
DAL
)
(t
DPL
)
(Burst end)
(t
RSC
)(t
RC
)
WRITA
WRIT
READA
WRITA
WRIT
PRE (Precharge termination)
PRE (Precharge termination)
PWDN
PDEX
16
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
4. Truth Table
4.1 Command Truth Table
Function Symbol CKE /CS /RAS /CAS /WE Address
n-1 n BA0 BA1 A10 A0-7,A11
Device des el ect DESL H x H x x x x x x
No operation NOP H x L H H H x x x
Burst stop BST H x L H H L x x x
Read READHxLHLH V L V
Read with auto precharge READA H
Write WRIT H x L H L L V L V
Write with auto prec harge WRITA H
Bank active ACT H x L L H H V
Prechrage sel ect bank PRE H x L L H L V L x
Precharge all banks PALL x H x
Mode register s et MRS H x LLLLLLL V
Extended mode register set EMRS H L L V
4.2 DM Truth Table
CKE DMFunction Symbol
n-1 n U L
Data write enable ENB H x L
Data mask MASK H x H
Upper byte write enable ENBU H x L x
Lower byte write enable ENBL H x x L
Upper byte write inhibit MASKU H x H x
Lower byte write inhibit MASKL H x x H
4.3 CKE Truth Table
Current St at e Function Symbol CKE /CS /RAS /CAS /WE Address
n-1 n
Idle CB R (auto) refresh command REF H H L L L H x
Idle Sel f refresh entry SELF H L
Self ref resh Self ref resh exit SREX L H x x x x x
Idle Power down entry PWDN H L x x x x x
Power down Power down exit PDEX L H x x x x x
Remark H = High level, L = Low level, V = Valid, x = High or Low level (Don't care)
17
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
4.4 Operative Command Table Note1
(1/3)
Current state /CS /RAS /CAS /WE Address Comm and Acti on Notes
Idle H x x x x DESL Nop or P ower down
L H H H x NOP Nop or Power down
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT Bank activat i ng
L L H L BA, A10 PRE/PALL Nop 3
L L L H x RE F/ SELF CBR (aut o) refresh or Self refresh 4
LLLLOp-CodeMRS Mode register set 4
LLLLOp-CodeEMRS Extended m ode regi s ter set 4
Row active H x x x x DES L Nop
LHHHx NOP Nop
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA Begin read/read with A P
L H L L BA, CA, A 10 WRIT/WRIT A Begin write/write with AP
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE /PALL P recharge/Precharge all banks 5
LLLHx REF ILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Read H x x x x DESL Nop (Row active after burst end)
L H H H x NOP Nop (Row active after burst end)
L H H L x BST t erminate burs t, Row active 6
L H L H BA, CA, A10 READ/READA term i nat e burst, Begin new read/
read with AP
6
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L B A, A10 PRE/PALL terminat e burst,
Precharge/Precharge all banks
6
LLLHx REF/SELFILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Write H x x x x DESL Nop (Row active aft e r tDPL)
L H H H x NOP Nop (Row active after tDPL )
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA term i nat e burst, Begin read/read with AP 6
L H L L BA, CA, A 10 WRIT/WRIT A terminat e burst, Begin new write/
write with AP
6
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE /PALL t erminate burs t , Precharge/P rec harge al l
banks 6
LLLHx REF ILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
18
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
(2/3)
Current state /CS /RAS /CAS /WE Address Comm and Acti on Notes
Read with auto H x x x x DESL Nop (P recharge after burst end)
precharge L H H H x NOP Nop (Precharge after burst end)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/W RITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
LLLHx REF/SELFILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Write with H x x x x DESL Nop (I dl e af ter tDAL)
auto precharge L H H H x NOP Nop (Idle aft er tDAL)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/W RITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
LLLHx REF/SELFILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Precharge H x x x x DESL Nop (Idle after tRP)
L H H H x NOP Nop (Idle af ter tRP)
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL Nop (Idle after tRP)3
LLLHx REF/SELFILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Row activati ng H x x x x DESL Nop (Row active after tRCD)
L H H H x NOP Nop (Row active after tRCD)
L H H L x BST ILLEGAL 2
L H L H BA, CA, A10 READ/READA ILLEGAL 2
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
LLLHx REF/SELFILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
LLLLOp-CodeSRS ILLEGAL
19
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
(3/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Write reco veri ng H x x x x DESL Nop (Row active aft er tDPL)
L H H H x NOP Nop (Row active after tDPL)
L H H L x BST Nop (Row active aft er tDPL)
L H L H BA, CA, A10 READ/READA Begin read/read with A P
L H L L BA, CA, A 10 WRIT/WRIT A Begi n new write/write with AP
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
LLLHx REF/SELF ILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Write reco veri ng H x x x x DESL Nop (Idle after tDAL)
with auto precharge L H H H x NOP Nop (Idle af ter tDAL)
L H H L x BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE/PALL ILLEGAL 2
LLLHx REF/SELF ILLEGAL
LLLLOp-CodeMRS ILLEGAL
LLLLOp-CodeEMRS ILLEGAL
Refresh H x x x x DESL Nop (Idle after t RC)
L H H H x NOP Nop (Idle af ter tRC)
L H H L x BST Nop (Idle after t RC)2
L H L x x READ/WRIT ILLEGAL 2
L L H x x ACT/PRE/PALL ILLEGAL 3
L L L x x REF/SELF/MRS/E
MRS ILLEGAL
Mode register H x x x x DESL Nop (Idle after tRSC)
acces sing L H H H x NOP Nop (Idle af ter tRSC)
L H H L x BST ILLEGAL 2
L H x x x READ/WRIT ILLEGAL 2
L L x x x ACT/PRE/PALL/R
EF/SELF/MRS/EM
RS
ILLEGAL 2
Remark H = High level, L = Low level, x = High or Low level (Don't care),
BA = Bank address, RA = Row address, CA = Column address, A10 = Precharge control address,
Op-Code = Operand code, Nop = No operation, AP = Auto precharge,
ILLEGAL = Device operation and/or data-integrity are not guaranteed
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock
cycle.
2. ILLEGAL to bank in specified states; function may be legal in the bank indicated by BA0, BA1 depending on
the state of that bank.
3. Nop to bank precharging or in idle state. May precharge bank indicated by BA0, BA1.
4. ILLEGAL if any bank is not idle.
5. ILLEGAL if tRAS is not satisfied.
6. Must satisfy command interval and/or burst terminate condition.
20
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
4.5 Command Truth Table for CKE
Current St at e CKE /CS /RAS /CAS /WE Add Command Action Notes
n-1 n
Self refresh Hxxxxxx ILLEGAL(Impossible)
L H x x x x x SREX Exit S.R, self refresh recovery 2
L L x x x x x Maintain self refresh
Self refresh recovery H H H x x x x DESL Nop (I dl e after tRC)
H H L H H H x NOP Nop (I dl e af ter tRC)
HLxxxxx ILLEGAL
Lxxxxxx ILLEGAL (Impossible)
Power down Hxxxxxx ILLEGAL (Impossible)
L H x x x x x PDE X Exit power down, Idle
L L x x x x x Maintain power down
All bank s i dl e H H V V V V x Refer t o operative command table
H L H x x x x PWDN Power down entry 1
H L L H H H x PWDN Power down entry 1
H L L x x L x ILLEGAL
H L L H L x x ILLEGAL
HLLLHxX ILLEGAL
HLLLLHX SELFSelf refresh entry 1
L X x x x x x ILLE GAL (Impossible)
Row active Hxxxxxx Refer to operative comm and table
Lxxxxxx Power down 1
Any state except H H V V V V V Refer to operati ve comm and table
list ed above H L x x x x x ILLEGAL
Lxxxxxx ILLEGAL (Impossible)
Remark H = High level, L = Low level, x = High or Low level (Don't care), V = Valid,
Add = Address (A0 - A11, BA0, BA1),
ILLEGAL = Device operation and/or data-integrity are not guaranteed
Notes 1. Self refresh can be entered only from all banks idle state.
Power down can be entered only from all banks idle or row active state.
2. CKE low to high transition will re-enable CLK and other inputs asynchronously.
A Minimum setup time must be satisfied before any command other than exit.
21
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
5. Initialization
The
µ
PD45D128xxx is initialized in t he power- on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100
µ
s or longer pause must precede any signal toggling.
(2) After the pause, EMRS and MRS command must be performed to enable or disable DLL and reset DLL. The
additional 200 cycles of clock input is required to lock the DLL and all banks must be precharged using the
precharge command.
In this case, PALL command is convenient.
(3) After the precharge, the mode register can be programmed by MRS command.
(4) Two or more REF command must be performed after or before MRS command.
Case 1 : MRS after the REF
CLK
Command REF MRS
t
RP
t
RSC
t
RC
t
RC
PALL REF
Any
Command
t
RSC
DLL
enable / disable DLL reset
CKE
Min. 200 cycles
t
RSC
MRSEMRS
Minimum of 2 times REF command must be performed.
Remark CKE may be held low and CLK may be run until 1 cycle before EMRS command is asserted to ensure
data-bus Hi-Z.
22
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0
as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields ;
Option : BA0, BA1, A11 through A7
/CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the mode critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device.
shows the relationship of /CAS latency to the clock period and speed grade of the device.
Burst Length
Burst length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 2, 4, 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing.
7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 2, 4 and 8.
23
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
7. Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 JEDEC standard test set
0000001 (Refresh counter Test)
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Vender specific
xxxxx11VVVVVVV
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0100000000000DLL
Extended mode register set
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register set
00000DLL0 LTMODE WT BL
Remark V = Valid, x = Don't care
/WE
/CAS
/RAS
/CS
CKE
CLK
A0 - A11,
BA0, BA1
Mode register set timming
Bit 8 DLL
0Normal
1 Reset
Bit 0 DLL
0 Enable
1 Disable
Bit 2 - Bit 0 WT = 0 WT = 1
000 R R
001 2 2
Burst 010 4 4
Length 011 8 8
100 R R
101 R R
110 R R
111 R R
Wrap Bit 3 Mode
Type 0 Sequential
1 Interleave
Bit 6 - B i t 4 /CAS Latency
000 R
001 R
Latency 010 2
Mode 011 R
100 R
101 R
110 2.5
111 R
Remark R : Reserved
24
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
7.1 Burst Length and Sequence
[Burst Length = Two]
Starti ng Address
(column address A0 , binary)
Sequential Addressing S equenc e
(decimal)
Interleave A ddressing Sequenc e
(decimal)
0 0, 1 0, 1
1 1, 0 1, 0
[Burst Length = Four]
Starti ng Address
(column address A1 - A 0, binary)
Sequential Addressing S equenc e
(decimal)
Interleave A ddressing Sequenc e
(decimal)
00 0, 1, 2, 3 0, 1, 2, 3
01 1, 2, 3, 0 1, 0, 3, 2
10 2, 3, 0, 1 2, 3, 0, 1
11 3, 0, 1, 2 3, 2, 1, 0
[Burst Length = Eight]
Starti ng Address
(column address A2 - A 0, binary)
Sequential Addressing S equenc e
(decimal)
Interleave A ddressing Sequenc e
(decimal)
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
25
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
8. Address Bits of Bank-Select and Precharge
[Activate Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row Address
BA1 BA0 Result
0 0 S el ect Bank A , ''Activate'' command
0 1 S el ect Bank B , ''Activate'' command
1 0 S el ect Bank C, ''Acti vat e'' com mand
1 1 S el ect Bank D, ''Acti vat e'' com mand
[Precharge Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Row Address
BA1 BA0 A10 Result
0 0 0 P recharge Bank A
0 1 0 P recharge Bank B
1 0 0 P recharge Bank C
1 1 0 P recharge Bank D
x x 1 Precharge All Banks
Remark x = Don't care
[Read/Write Command]
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Column Address
A10 Result
0 Disables Auto-Precharge
1 Enables A uto-Precharge
BA1 BA0 Result
0 0 E nabl es Read/Write c ommands for Bank A
0 1 E nabl es Read/Write c ommands for Bank B
1 0 E nabl es Read/Write c ommands for Bank C
1 1 E nabl es Read/Write c ommands for Bank D
26
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
9. Precharge
9.1 Read to Precharge Command Interval
The precharge command can be issued anytime after tRAS (MIN.) is satisfied. Soon after the precharge command is
issued, precharge operation performed and the DDR SDRAM enters the idle state after tRP is satisfied. The
parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as
follows.
/CAS latency = 2 : (burst length/2) clocks after the read command is issued.
/CAS latency = 2.5 : (burst length/2) clocks after the read command is issued.
CLK
T0 T2T1 T3 T4 T5
Burst length = 4
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(Must satisfy t
RAS
)
PRE
PRE
Hi-Z
Hi-Z
DQS
DQS
Hi-Z
Hi-Z
27
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
9.2 Write to Precharge Command Interval
In order to write all burst data to the memory cell correctly, the asynchronous parameter tDPL (MIN.) must be satisfied.
The tDPL specification defines the earliest time that a precharge command can be issued.
CLK
Burst length = 4
Q1 Q2 Q3
WRITE
DQ
Command
Q4
/CAS latency = 2, 2.5
/CLK
DM
(Must satisfy t
RAS
)
PRE
Hi-Z
DQS Preamble Postamble
t
DPL
= 1 cycle
T0 T2T1 T3 T4 T5
28
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the read or
write command (read with auto precharge command or write with auto precharge command), auto precharge is
selected and begin automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
10.1 Read with Auto Precharge
When a read with auto precharge command is issued, the auto precharge begins (Burst length / 2) clocks later from
a read with auto precharge command.
CLK
Burst length = 4
Q1 Q2 Q3
READA
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READA
Burst length / 2 cycle
(When t
RAS
is satisfied)
ACT
ACT
Hi-Z
Hi-Z
t
RP
Auto precharge starts
Auto precharge starts
T0 T2T1 T3 T4 T5
Remark READA means Read with Auto Precharge command
29
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
10.2 Write with Auto Precharge
When a write with auto precharge command is issued, the auto precharge begins after tDPL(MIN.) is satisfied.
CLK
Burst length = 2
D1
WRITEA
DQ
Command
DQS
/CAS latency = 2, 2.5
/CLK
CKE
ACT
t
DPL
= 1 cycle
(When t
RAS
is satisfied)
D2
t
RP
Auto precharge starts
t
DAL
= t
DPL
+ t
RP
T0 T2T1 T3 T4 T5
Remark WRITEA means Write with Auto Precharge command
30
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11. Read/Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between commands is minimum 1 cycle. Each read command can be issued in every clock without any
restriction.
CLK
Burst length = 4
QB1 QB2 QB3
READ A
DQ
Command
QB4
DQ
Command
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ A
1 cycle
READ B
READ B
Hi-Z
Hi-Z
QA1 QA2
QB1 QB2 QB3
QA1 QA2
T0 T2T1 T3 T4 T5
31
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.2 Write to Write Command Interval
During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will
begin with new write command. WRITE will be interrupted by another WRITE.
The interval between commands is minimum 1 cycle. Each write command can be issued in every clock without any
restriction.
CLK
Burst length = 4
WRITE A
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
1 cycle
DA1DQ DA2 DB1 DB2 DB3 DB4
WRITE B
T0 T2T1 T3 T4 T5
32
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.3 Write to Read Command Interval
The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance
at least 1 cycle prior to the first output data.
The minimum time interval between the rising clock edge after the last input data and the read command is 1 cycle.
When the read command is issued, the invalid data from the burst write cycle must be masked by DM.
CLK
Write A
DQS
Command
/CAS latency = 2
/CLK
CKE
Read B
DQ DA1
,
,,
,,,
,,,
DM
QB1 QB2 QB3 QB4
,,,,,,
Write A
DQS
Command Read B
DQ DA1 DA2
,
,
,,
,,
,,,
DM
QB1 QB2
,,,,,,
,,,,,,
/CAS latency = 2.5
DQ and DQS : Input DQ and DQS : Output
DA2
1 cycle
QB3
T0 T2T1 T3 T4 T5 T6
Hi-Z
Hi-Z
Hi-Z
Hi-Z
33
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.4 Read to Write Command Interval
To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid
data conflict. The data bus must be high impedance at least 1 cycle before the write command is issued.
When the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop
command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 3 cycles prior to the write
command.
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8 Burst length = 8
T9
Read A
DQS
Command
/CAS latency = 2
/CLK
CKE
T10 T11
Write B
DQ QA1 QA2
T12 T13 T14
DB1 DB2
Read A
DQS
Command Write B
DQ QA1 QA4
/CAS latency = 2.5
DQ and DQS : Output DQ and DQS : Input
BST
BST
DB1 DB2
QA3 QA4
Hi-Z
Hi-Z
QA2 QA3
DB
DB
T0 T2T1 T3 T4 T5 T6
Hi-Z
Hi-Z
34
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12. Burst Termination
12.1 Burst Stop Command in Read Cycle
During a burst read cycle, when the burst stop command is issued at the rising edge of the clock (CLK), the burst
read data are terminated and the data bus goes to high impedance after the /CAS latency from the burst stop
command.
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8 Burst length = 8
T9
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
T10 T11
READ
(When t
RAS
is satisfied)
BST
BST
Hi-Z
Hi-Z
T0 T2T1 T3 T4 T5
Remark BST means Burst Stop command
35
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12.2 Precharge Termination in Read Cycle
During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of
the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read
operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge
command. The precharge command can be issued after tRAS (MIN.) is satisfied.
CLK
Burst length = Full page
Q1 Q2 Q3
READ
DQ
Command
Q4
Q1 Q2DQ
Command
Q3 Q4
/CAS latency = 2
/CAS latency = 2.5
/CLK
CKE
READ
(When t
RAS
is satisfied)
PRE
PRE
Hi-Z
Hi-Z
T0 T2T1 T3 T4 T5
36
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12.3 Precharge Termination in Write Cycle
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of
the same banks. In order to write the last input data to the memory cell correctly, tDPL (MIN.) must be satisfied. When
the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle
must be masked DM.
CLK
Burst length = 8
Write
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
tDPL = 1 cycle
PRE
DQ D1 D2
,
,,
,,,
,,,
DM
,,,,
T0 T2T1 T3 T4 T5
37
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13. Electrical Specifications
•All voltages are referenced to VSS (GND).
•After power up, wait more than 100
µ
s and then, execute Power on sequence and CBR (a uto) Refresh before
proper device operation is achieved.
13.1 Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin rel ative to VSS VCC, VCCQ−0.5 to +3.6 V
Voltage on any pin rel ative to VSS VT−0.5 to +3.6 V
Short ci rcuit output c urrent IO50 mA
Power dissipat i on PD1W
Storage temperature Tstg −55 to + 125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
13.2 Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply volt age VCC 2.375 2.5 2.625 V
Supply volt age for DQ, DQS VCCQ 2.375 2.5 2.625 V
Input reference voltage VREF 1.1875 1.25 1.3125 V
Termination voltage VTT VREF − 0. 04 VREF VREF + 0.04 V
High level dc i nput voltage VIH (DC) VREF + 0.18 V cc + 0.3 V
Low level dc input voltage VIL (DC) −0.3 VREF − 0.18 V
Operating ambient temperature TA070
°C
13.3 Pin Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11, BA0, BA1 2.5 5 pF
CI2 CLK, /CLK, CKE, /CS, /RAS, /CAS, /WE, DM, LDM, UDM 2.5 5 pF
Data input/ output capaci t ance CIO1 DQS , LDQS, UDQS 4 6.5 pF
CIO2 DQ0 - DQ15 4 6.5 pF
38
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition Maximum Unit Notes
/CAS
latency Grade
x4 x8 x16
Operating current ICC1 tRC ≥ tRC(MIN.), Io = 0 mA, CL = 2 -C10 110 120 135 mA 1
-C12 95 100 115
CL = 2.5 -C10 120 130 145
-C12 105 110 125
Precharge standby current
in power down mode ICC2P CKE ≤ VIL(MAX.), tCK = 10 ns 25 mA
Precharge standby current
in Non power down mode ICC2N CKE ≥ VIH(MIN.), tCK = 10 ns, /CS ≥ VIH(MIN.),
Input si gnal s are changed one time during 20 ns.
40 mA
Act i ve standby current i n
power down mode ICC3P CKE ≤ VIL(MAX.), tCK = 10 ns 45 m A
Act i ve standby current i n
Non power down mode ICC3N CKE ≥ VIH(MIN.), tCK = 10 ns, /CS ≥ VIH(MIN.),
Input si gnal s are changed one time during 20 ns.
50 mA
Operating current ICC4 tCK ≥ tCK(MIN.), I o = 0 mA, CL = 2 -C10 150 170 200 mA 2
(Burst mode) All bank activated -C12 125 140 165
CL = 2.5 -C10 190 210 250
-C12 150 170 200
CBR (auto) ref resh current ICC5 tRC ≥ tRC(MIN.) 290 mA 3
Self ref resh current I CC6 CKE ≤ 0.2 V 2 mA
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured condition that addresses are changed only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test c ondi t i on MIN. MAX. Unit Notes
Input leak age current II(L) VI = 0 to 3.6 V, al l other pins not under t es t = 0 V −55
µ
A
Output leak age current IO(L) DOUT is disabled, VO = 0 to VCCQ + 0.3 V −55
µ
A
High level out put voltage VOH IO = −12 mA VTT + 0.6 V
Low level output voltage VOL IO = 12 mA VTT − 0.6 V
39
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)
13.6.1 Test Conditions
Parameter Symbol Value Unit Notes
Input Reference voltage (Input t i ming m easurement ref erence level) VREF VCCQ x 0.5 V
Termination voltage (Output timing measurem ent reference level) VTT VREF V1
High level ac i nput voltage VIH(ac) VREF + 0.35 V
Low level ac input voltage VIL(ac) VREF − 0.35 V
Input si gnal slew rate SLEW 1 V/ns 2
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level.
2. Slew rate is to be maintained in the VIL(ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)-
VIL(ac))/ ∆t
Output R
S
= 25 ΩR
T
= 25 Ω
C
LOAD
= 30 pF
V
TT
= 0.5 x V
CC
Q
40
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.6.2 Timing Diagram
t
CK
t
DQSCK
t
DQSCK
t
CH
t
CL
t
IS
t
IH
,,
,,
t
IS
t
IH
,,
,,
,,,,
,,,,
t
IS
t
IH
,,
t
IS
t
IH
,,
,,,,
,
,
,
,,
,,
,
,
Valid Valid
t
RPRE
t
DQSV
,
,
Valid
t
AC
t
AC
t
DV
t
DV
t
DQSQ
t
RPST
t
DQSCK
Valid Valid
Valid Valid
t
DQSV
t
QSCK
Valid
t
DQSQ
,
,,
,,
t
DH,
t
DMH
t
DS,
t
DMS
t
WPST
Valid Valid
t
RPST
t
AC
t
AC
t
DQSQ
t
DQSQ
t
DV
t
DV
t
WPRES
t
WPREH
t
DQSS
CLK
DQS
(Output)
(CL = 2.5)
DQ
(Output)
(CL = 2.5)
/CLK
Command
(Input)
Address
(Input)
DQS
(Output)
(CL = 2)
DQ
(Output)
(CL = 2)
DQS
(Input)
DQ and DM
(Input)
V
REF
+ 0.35 V
V
REF
- 0.35 V
t
CKSK
V
REF
V
TT
V
TT
V
TT
V
TT
V
REF
+ 0.35 V
V
REF
- 0.35 V
V
REF
+ 0.35 V
V
REF
- 0.35 V
V
REF
+ 0.35 V
V
REF
- 0.35 V
V
REF
+ 0.35 V
V
REF
- 0.35 V
V
REF
V
REF
t
RPRE
t
WPRE
41
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.6.3 Synchronous Characteristics
Parameter Symbol -C10 -C12 Unit
MIN. MAX. MIN. MAX.
Frequency fCK CL = 2. 5 125 100 MHz
CL = 2 100 83 MHz
Clock cycle time tCK CL = 2.5 8 15 10 15 ns
CL = 210151215ns
Parameter Symbol MIN. MAX. Unit Note
CLK high time tCH 0.45 0.55 CLK
CLK low time tCL 0.45 0.55 CLK
CLK to /CLK skew tcksk 0.015 CLK
Data access time from CLK tAC −0.1 x tCK 0.1 x tCK ns
Data Strobe edge to CLK egde skew tDQSCK −0.1 x tCK 0.1 x tCK ns
Data Strobe egde to Output Data edge s kew tDQSQ −0.075 x tCK 0.075 x tCK ns
Output Data val i d window tDV 0.3 x tCK ns
Output Data Strobe valid window tDQSV 0.3 x tCK ns
DQS entry to Low-Z to f i rs t rising edge delay (read) tRPRE 0.9 x tCK 1.1 x tCK ns
DQS last falling edge to entry to Hi-z del ay (read) tRPST 0.4 x tCK 0.6 x tCK ns
Data to Strobe setup time tDS 0.075 x tCK ns
Data to Strobe hold time t DH 0.075 x tCK ns
Data m as k to Strobe s etup tim e tDMS 0.075 x tCK ns
Data m as k to Strobe hol d t i me tDMH 0.075 x tCK ns
CLK to DQS write preamble setup time tWPRES 0ns
CLK to DQS write preamble hold time tWPREH 0.25 x tCK ns
DQS entry to Low-Z to f i rs t rising edge delay (write) tWPRE 0.4 x tCK 1.1 x tCK ns
DQS last falling edge to ent ry t o Hi -Z del ay (write) tWPST 0.4 t CK 0.6 x tCK ns
CLK to fi rst rising edge of DQS tDQSS 0.75 x tCK 1. 25 x tCK ns
Input setup tim e tIS 0.15 x tCK ns
Input hold t i me tIH 0.15 x tCK ns
Transition time (CLK, /CLK, DQS, DQ, DM) tTD 0.5 ns
Transiti on t i me (CMD, Add) tT0.5 ns
Remark If the result of the nominal calculation contains more than one decimal place, the result is rounded up to the
nearest decimal place.
42
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.6.4 Synchronous Characteristics Example
Symbol fCK = 125 MHz,
tCK = 8 ns
fCK = 100 MHz,
tCK = 10 ns
fCK = 83 MHz,
tCK = 12 ns
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
tCH 3.6 4.4 4.5 5.5 5.4 6.6 ns
tCL 3.6 4.4 4.5 5.5 5.4 6.6 ns
tCKSK 0.2 0.2 0.2 ns
tAC −0.8 0.8 −11
−1.2 1.2 ns
tDQSCK −0.8 0.8 −11
−1.2 1.2 ns
tDQSQ −0.6 0.6 −0.8 0.8 −0.9 0.9 ns
tDV 2.4 3 3.6 ns
tDQSV 2.4 3 3.6 ns
tRPRE 7.2 8.8 9 11 10.8 13.2 ns
tRPST 3.2 4.8 4 6 4.8 7.2 ns
tDS 0.6 0.8 0.9 ns
tDH 0.6 0.8 0.9 ns
tDMS 0.6 0.8 0.9 ns
tDMH 0.6 0.8 0.9 ns
tWPRES 000ns
tWPREH 2.0 2.5 3.0 ns
tWPRE 3.2 8.8 4 11 4.8 13.2 ns
tWPST 3.2 4.8 4 6 4.8 7.2 ns
tDQSS 6.0 10.0 7.5 12.5 9.0 15.0 ns
tIS 1.2 1.5 1.8 ns
tIH 1.2 1.5 1.8 ns
tTD 0.5 0.5 0.5 ns
tT0.5 0.5 0.5 ns
13.6.5 Asynchronous Characteristics
Parameter Symbol -C10 -C12 Unit Note
MIN. MAX. MIN. MAX.
ACT to ACT delay (Same bank),
REF to REF delay
tRC 70 84 ns
ACT to PRE delay tRAS 50 120,000 60 120,000 ns
PRE to ACT delay tRP 20 24 ns
ACT to READ/WRIT delay tRCD 20 24 ns
ACT to ACT delay (Dif ferent bank) tRRD 20 24 ns
CLK related with last Din to PRE delay tDPL 10 12 ns
CLK related with last Din to ACT/REF delay
(Auto precharge)
tDAL 30 36 ns
Mode register set cycle ti me tRSC 22CLK
Refresh ti me tREF 64 64 ms
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
43
AC Parameters for Read Timing 1 (Manual Precharge, Burst Length = 4, /CAS Latency = 2.5)
,,,
,,,
,,
,,
,,,,
,,,,
,,,
,,,
,,,
,,,
,,,,
,,,,
,,,
,,,,
,,,
,,,
,,,,
,,,
,,,,
,,,
,,,,
,,,
,,,
,,,,
,,,
,,,
,,,,
,,,
,,,
,,,
,,,,,,
,,,,,,
,,,
,,,
t
RAS
t
RC
,,,,
,,,,
,,,
,,,
,,,
,,,
BA1
t
IH
t
RP
,,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
,,
,,
,
,,
,,
,
,
,
,
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
t
RCD
t
IS
t
CH
t
CL
t
CK
t
IS
t
IH
L
Activate
Command
for Bank A
Precharge
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
t
CK
t
CL
t
CH
/CLK
t
IS
t
IH
DQS
DQ
,
,
,
,
,
,
,
,
,
,
,
,
t
AC
t
DQSQ
,
,
,
,
,
,
,
,
t
DQSQ
t
DQSQ
t
DQSQ
t
AC
t
AC
t
AC
,
,
t
DV
t
DV
t
DV
t
DV
t
DQSV
t
DQSV
t
DQSV
t
DQSCK
t
DQSCK
t
DQSCK
t
DQSCK
t
RPRE
t
RPST
Hi-Z
V
TT
Hi-Z
V
TT
,,,,,,,,,,,,
Preliminary Data Sheet
44
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
AC Parameters for Read Timing 2 (Auto Precharge, Burst Length = 4, /CAS Latency = 2.5)
,,,
,,,
,,
,,
,,,
,,
,,,,
,,,
,,,
,,,,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,,
,,,
,,,,
,,,,
,,,
,,,,
,,,
,,,,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,,
,,,
,,,
,,,
,,,
tRAS
tRRD
tRC
,,,,
,,,
,,,,
BA1
tIH
,,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
,,
,
,
,,
,,
,,
,
,
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
tRCD
tIS
tCH tCL
tCK
tIS tIH
tIS tIH
,,,
,,,
,,,
Activate
Command
for Bank C
Activate
Command
for Bank D
Bank C
Read Command
with Auto Precharge
Activate
Command
for Bank C
DQS
DQ
Hi-Z
VTT
,
,
,
,
,
,
tAC
tDQSQ
,
,
,
,
tDQSQ tDQSQ tDQSQ
tAC tAC tAC
,
tDV tDV tDV tDV
tDQSV tDQSV
tDQSV
tDQSCK
tDQSCK
tDQSCK
tDQSCK
tRPRE tRPST
t
CK
t
CL
t
CH
/CLK
Auto Precharge
Start for Bank C
Hi-Z
V
TT
,,,,,,,,,,,
,,,,,,,,,,,
45
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Relationship between Frequency and Latency
Speed version -C10 -C12
Clock cycle time [ns] 8 10 10 12
Frequency [MHz] 125 100 100 83
/CAS latency 2.5 2 2.5 2
[tRCD] 3232
/RAS latency
(/CAS latency + [tRCD]) 5.5 4 5.5 4
[tRC]10797
[tRAS]7565
[tRRD]2222
[tRP]3232
[tDPL]2121
[tDAL]4343
[tRSC]2222
Preliminary Data Sheet
46
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
AC Parameters for Write Timing (Burst Length = 8, /CAS Latency = 2.5)
,,
,,
,,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,,
,,,
,,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,,
,,
,,
,,
,,,
,,
,,
,,
,,
,,,
,,
,,,
,,,
,,
,,
,,,
,,,
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,
,,
,,
CLK
CKE
BA1
A10
ADD
DM
DQ Hi-Z
t
IS
t
IH
tRCD tRC
tRRD tRCD tRAS tRC
tDPL tRP
t
IH
,,
t
IS
t
IH
tIS
/CS
/RAS
/CAS
/WE
,,
,,,
,,,
,,
BA0
,,
,,
Auto Precharge
Start for Bank C
,,
Activate
Command
for Bank C
Activate
Command
for Bank B
Bank B
Write Command
without Auto Precharge
Activate
Command
for Bank B
Bank C
Write Command
with Auto Precharge
Precharge
Command
for Bank B
Activate
Command
for Bank C
/CLK
tDS tDH
DQS
tDQSS tWPST
Hi-Z
VTT
VTT
tWPRES tWPREH
tDAL
,,,,
,,,,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
47
Mode Register Set (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,,
,,
,,,,,,,,
,,,,,,,,
,
,
,
,
,,
,,
,,,,,,,,
,,,,,,,,
,
,
,
,
,,
,
,
,,,,,,,,
,,,
,,
,
,,
,,,,,,,,
,,,
,,,
,,
,,
,,,,,,,,,
,,,,,,,,,
,,
,,,,,,,,,
,,,,,,,,,
,,
,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
BA0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
V
TT
t
RSC
ADDRESS KEY
t
RP
All Banks
Precharge
Command
Mode
Register Set
Command
Activate
Command
is valid
H
V
TT
DQS
/CLK
Hi-Z
Hi-Z
Preliminary Data Sheet
48
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Power On Sequence and CBR (auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,,
,,
,,
,,
,,
,,
,,
,,
,,,,,,,
,,
,,
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
Hi-Z
,,
,,
,,
,,
,,,
,,,
,,,
,,,
,
,
,
,
,,
,,
,,
,
,
Low level is necessary
2 refresh cycles are necessary
tRP tRC
All Banks
Precharge
Command
is necessary
Mode
Register Set
Command
is necessary
Refresh
Command
is necessary
Activate
Command
Refresh
Command
is necessary
BA1
,,
,,
,
,
,
,
DQS Hi-Z
/CLK
More than 200 cycle is necessary
,,,,
,,,,
,,,,
tRSC
,,,,
ADDRESS KEY
,
,,
,,
,,
,,
,,,,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
VTT
VTT
tRC
,,
,
ADDRESS KEY
,,,,,,,
ADDRESS KEY
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,
,,
Extended Mode
Register Set
Command
(DLL enable /
disable)
is necessary
Mode
Register Set
Command
(DLL reset)
is necessary
tRSC tRSC
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
49
/CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 2.5)
Only /CS signal needs to be issued at minimum rate
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
H
L
Hi-Z
L
BA1 L
RAa
QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
RAa CAa CAb
/CLK
DQS Hi-Z
VTT
VTT
Preliminary Data Sheet
50
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Power Down Mode (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,,,,,,
,,,,
,,
,,
QAa3
CAa
,,,,,,
,,
,
,
,,
,
,,
,,
,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,,
Hi-Z
RAa
,,,,,
,,,,,
,
,
,,,,,
,,,,,
,
,
,,,,,
,
,,
,,
,,,,
,,,,
BA1
,
,,,,,,,,
,,,,,,
,
,,,,,
,,,,
t
IS
QAa1 QAa2
Activate
Command
for Bank A
Power Down
Mode Entry
Read
Command
for Bank A
Precharge
Command
for Bank A
PRECHARGE STANDBY
Power Down
Mode Exit
QAa4
/CLK
DQS Hi-Z
V
TT
V
TT
,,,,,,,,,,,,
,,
,
,
,,,,,,,
,,,,,,,
,
,,,,,,,
,,,,,,,
RAa
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
51
CBR (auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,,
,,
,
,
,,,,,,,,,
,,
,
,,,,,,,,
,,,,,,,,
,
,
BA1
,,
,,
,,,,,,,,,
,,
,,
,,
,,
,,
,,
,,,,
,,,,
,,
,,,,
,,,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,,,
,,,,
,,
,
,
,,,,
,,,,
,,
,,
,,
,,
,,
,,
,,,,
,,
,,
,,,,
,
,,
,,
,,
,,
,
VTT
tRP
H
tRC tRC
Q1
Precharge
Command
is necessary
CBR (auto) Refresh CBR (auto) Refresh Activate
Command Read
Command
,,,,,,,,
,,
,,
/CLK
Q2
VTT
DQS Hi-Z
Hi-Z
,,,,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
Preliminary Data Sheet
52
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Self Refresh (Entry and Exit)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,,,,,
,,
,,
,,,,,,,,,,
T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tm+2 Tk Tj Tj+1 Tj+2
t
RP
,,,,,
,,,,,
,,,,
,,,,
,,,,
,,,,
,,,
,,,
,,,
,,,
,,
,,
,,
,,
,,
,,,,,
,,,,,
,,,
,,,
,,,
,,,
,,
,,,,,,,,
BA1
,,,
,,,
,,
,,
,,,,,,,,,
,,,,,,,,,
Hi-Z
Precharge
Command
is necessary
Self Refresh
Entry Self Refresh
Exit
Next Clock
Enable
Self Refresh
Entry
(or Activate Command)
Activate
Command
Self Refresh
Exit
Next Clock
Enable
/CLK
,,
DQS Hi-Z
V
TT
V
TT
200 cycles 200 cycles
,,,,,,,,,,,,
,,,,,,,,,,,,
,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
53
Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,,,,,,,,,,,
,,
,
,,
,
,,,
,,
,
,
,,
,,
,,
VTT
,,,,,,
,,,,,,
QAa1 QAa2
,,,,,,,,,,,,
,
,
,
,,,,,,
,,,,,,
,,,,,,
,,,,,,
,,
,,
,,
,,
,
,
,,
QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
,,,
H
RAd
RAa CAdCAcCAa RAdCAb
,
,
,,
,,
,,
,,
BA1
,
,
,,,
,
,
,,,,,,
,,,,,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,
,,
,
,
,
,
,
,
,
RAa
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
QAd1 QAd2 QAd3 QAd4
DQS
VTT
/CLK
,,,,,,,,,,,,
,,,,,,,,,,,,
Hi-Z
Hi-Z
Preliminary Data Sheet
54
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,,,,
,,,,,,,,,,,,
,,,
,,
,,,
,,
,,,
,,
,,
,,
,,
,,
,,
,
,,,,
,,,,
,,,,
,,,,,,,,,,,,,
,,
,,
,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
H
RAa
RAa CAaCAcCAa RAaCAb
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
BA1
,,
,,
,,,,
,,
,,
,,,,,
,,,,,
,,
,,
,,,,
,,,
,,,
,,
,,
,,,
,,,
,,,
,,
,,
,,
,,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,
,
RAa
,,
,,
/CLK
DM
DQ
VTT
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
QAd1 QAd2 QAd3 QAd4
DQS
VTT
,,,,,,,,,,,,
,,,,,,,,,,,,
Hi-Z
Hi-Z
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
55
Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
DM
,
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,,
,,,,,,,,,,,,
,,
,
,,
,
,,
,
,
,,
,,
,,
,,,,
,,,,
,,,,,,,,,,,,
,
,
,
,,,,,
,,,,,
,,,,,
,,,
,,,
,,,
,,
,,
,,
,,,,
,,
H
RDd
RDa CDdCDcCDa RDdCDb
,
,
,
,
,,
,
,
,,,,
,
,
,,,,,
,,,,,
,,,
,,,
,,,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,
,
,
RDa
,,
,,,
,,,,,
,,
,
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
/CLK
DQ
DQS VTT
DDd1 DDd2 DDd3 DDd4
VTT
Hi-Z
BA1
BA0
,,,
,,,
,,,,
,,,,
,,,,
,,,,
Preliminary Data Sheet
56
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,,,,
,,,,,,,,,,,,
,,
,,
,,
,,
,
,,
,
,
,,
,,
,,
,
L
Hi-Z
,,,
,,,
,,,
DDa1 DDa2
,,,,,,,,,,,,
,
,
,,
,,,
,,,
,,,
,,,
,,,
,,,
,,
,,
,,
,
,,
DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
,,,,
H
RDd
RDa CDdCDcCDa RDdCDb
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
,
,
,,,
,,,
,,,
,,,
,,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,,
,
,
RDa
,,
,,
,,,
,,,
,,
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
/CLK
BA1
DM
DQ
BA0
DQS V
TT
DDd1 DDd2 DDd3 DDd4
V
TT
Hi-Z
,,,,
,,,,
,,
,,
,,,,,
,,,,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
57
Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,,
,,,,,,,,,,,,
,
,,
,,
,
,,
,
,
,,
,,
,
,
,,
,,
,
,
Hi-Z
,,
,,
,
,,,,
,,,,
,,,,
,,,,
QDa1 QDa2
,,,,,,,,,,,,
,,
,,
,,
,,
,,,
,,,
,,,
,,,
QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5
H
RDb
RDa CDbCBaCDa RDbRBa
,,
,,
,,,,
,,,,
,
,
,,,
,,,
,
,,,,
,,,,
,,
,,
,,
,,
,,
RDa
,
,,,
,,
,,
,,
,
,
,,,
,,,
,,
,
,
,,
,,
,,
,,
,,,
,,
BA1
,,
,,
,,
,
,
,
,,
,,,,
,,
,,,,
,
,
,
,,
RBa
,
,
,
,
QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank D
QDb1 QDb2 QDb3 QDb4 QDb5 QDb6 QDb7 QDb8
DQS
Hi-Z
V
TT
V
TT
/CLK
,,,,,,,,,,,,
Preliminary Data Sheet
58
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,,,,,,,,,,,
,,
,,
,,
,
,,,
,,,
,,
,,
,
,
Hi-Z
,,
,,,,,,,,,,,,
,,
,,
,,
H
RBb
RBa CBbCAaCBa RBbRAa
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RBa
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
RAa
,,
,,
,
,
,
,
,
,
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,
,,
,
,,
BA0
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
,,
,,
,
,
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 QBb1 QBb2 QBb3 QBb4 QBb5 QBb6
/CLK
,,
,,
,,
,,
,,
,,
DQS
,,,,,,,,,,,,
V
TT
V
TT
Hi-Z
QBb7
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
59
Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
DM
DQ
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,,,
,,,,,,,,,,,,
,
,,
,,
,
,
,,
,,
,
,
,
,
L
,,,,,
DAa5 DAa6
,,,,,,,,,,,,
,,
,,
DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8
H
RAa CAbCDaCAa RDa
,,
,,
,
,
,,
,
RAa
,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
RDa
,
,
,,,,,
,,,,,
,,,,
,,,,
,,,,
,,,,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,,,
,,,,
,,
,,
,,
,,
,
,,
RAb
RAb
,
,
DAa1 DAa2 DAa3 DAa4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
,,
,,
,,
,,
,,
,,
,,
,,
,,
BA1
Hi-Z
BA0
/CLK
DQS Hi-Z
V
TT
V
TT
DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
,,,
,,,
,,,
,,,
,,
,,
Preliminary Data Sheet
60
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,,,
,,
,,
,,
,
,,
,
L
,,,,,,,,,,,,
,,
,,
,,
H
RAa CAbCDaRDa
,,
,,
,,
,,
,,
RAa
,,
,,
,,
,,
,,
,,,
RDa
,,
,,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
,,,,
,,,,
,,,
,,,
,,,
,,
RAb
,,
,,
,,
,,
,,
,,
,,
,,
CAa
,
,
,,
,,
,,,
RAb
,,
,,
,,,,
,,,,
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank D
Write
Command
for Bank A
A10
ADD
DM
DQ
BA1
Hi-Z
BA0
/CLK
DQS
Hi-Z
V
TT
V
TT
,,
,,
,
,,,,
,,,,
,,,,
,,,,
,,,,
DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8DAa1 DAa2 DAa3 DAa4 DAb1 DAb2 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8
Hi-Z
,
,,,
,,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
61
Read and Write (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DM
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
,
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,
,
,
,
,
,,,,
,,,,
,,,,
,,
,,,,
,,,,
Hi-Z at the end of
wrap function
,,,,
,,,
,,,
,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,
,,,,
,,,,
,,,,
,,
,,,,,
H
RAa CAcCAb
,,,,
,,
BA1
,
,
,,,,
,,,,
,,,,,
,,,,,
,,,
,,,
,,,,
,
,
,
,
,
,
,,
CAa
,,
RAa
,,,,
,,,
,,,,
Word Masking
/CLK
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 DAb1 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 QAc1 QAc2 QAc3 QAc4 QAc5 QAc6 QAc7 QAc8
DQS
Hi-Z
V
TT
V
TT
Hi-Z
,,,,,,,
,,,,,,,
,,,,
,,,,
Preliminary Data Sheet
62
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
,
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,
,
,
,
,,
,
,,,,,
,,,,,
,,,,
,,
,,,
,,,
,,,,,,,,,,,,
,,,,,
,,,,
,,,,
,,,,
,,,
,,,
,,,
,,,
,,,,
,,,,
,,,,
,,,,
,,
,
H
RAa CAcCAb
,,,,,
,,
,,
,,
,,
,,
,,
CAa
,,
,,,,
,,,
,,
RAa
,,
,
BA1
,
,
,,,,,
,,,,,
,,,
,,,
,,,,
,,,,
,,
,,
,,
,
,,
,
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
/CLK
DM
DQ
Word Masking
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 DAb1 DAb3 DAb4 DAb5 DAb6 DAb7 DAb8 QAc1 QAc2 QAc3
DQS
Hi-Z
V
TT
V
TT
Hi-Z
,,,,,,,
,,,,,,,
,,,
,,,
QAc1 QAc2 QAc3
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
63
Interleaved Column Read Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,
,
,
,
H
RAa RDa
,,
,,
,
,
,,
,,
,,
,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,,
,
,
,,
,
,
BA1
,,
,,
,,
,,
,,
,,
,
,,
,,
,
,,
,,
,,
,,
,,
RAa
,
,
RDa
CAa
,
CDa CDb CDc CAb
,,,,,
,
CDd
,,
,,
,,
,,
,,
,,
Activate
Command
for Bank A Activate
Command
for bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
Read
Command
for Bank A
DQ
VTT
DQS
VTT
Dc4
Dc1 Dc2 Dc3
Db4
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Ab4
Ab1 Ab2 Ab3 Dd1 Dd2 Dd3 Dd4 Dd5 Dd6 Dd7 Dd8
/CLK
Hi-Z
Hi-Z
,,,,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
Preliminary Data Sheet
64
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Interleaved Column Read Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,,
,,
,,
,,
,,
,
,
L
,,
,,
,,
,,,
,,,
,,,,,,,,,,,,
,
,
,
,
,,
,,
,,
,,
,,
H
,,
,,
,,
,,
,,
,,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,
,
,
,
,
,
,,
,,
,
,
,,
,,
,
,
,,
,,
,,
,,
,
,
,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
RAa
,,
,,
RDa
,,
,,
,,
,,
,,
,,
,,,
,,,
BA1
,,
,
,
,
,,
,,
,
,
,,
,,
,,
,,
,,
,,,,,,,,,,,,
RAa CAb
CDc
RDa CDaCAa
Activate
Command
for Bank A Activate
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A Precharge
Command
for Bank D
Precharge
Command
for Bank A
Read
Command
for Bank A
CDb
DQ
V
TT
DQS
V
TT
Dc4
Dc1 Dc2 Dc3
Db4
Aa1 Aa2 Aa3 Aa4 Aa5 Aa6 Aa7 Aa8 Da1 Da2 Da3 Da4 Db1 Db2 Db3 Ab4
Ab1 Ab2 Ab3 Ab5 Ab6 Ab7 Ab8
/CLK
Hi-Z
Hi-Z
,,,,,,,,,,,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
65
Interleaved Column Write Cycle (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,
,
,,
,,
,,
,,
,
,
Hi-Z
,
,
,
,,,,,,,,,,,,
,,
,,
,,
,,
,
,
,
,
,
,
,
H
RAa RBa
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,
,
,
,
,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,,
,,,
,,,
,,,
,,
,
,
,,
,,
,
,
,
,
,
,
,
,,
,,
RAa
,
RBa
CAa
,
CBa CBb CBc CAb
,,,,
,
CBd
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,
,,
,,
,
,,
,,
BA0
,
,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,
,,
,,
,,
,,
,
Activate
Command
for Bank A
Write
Command
for Bank A Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
,,
,,
,,
,,
,,
,,
,,
,,
,,
/CLK
Aa1 Aa2 Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2 Bd3 Bd4
Ab1 Ab2
Bb1 Bb2
Aa5 Aa6 Aa7 Aa8 Ba3 Ba4 Bc3 Bc4 Bd5 Bd6 Bd7 Bd8
Ab3 Ab4
Bb3 Bb4
DQS Hi-Z
VTT
V
TT
,,,,
,,,,
,,
,,
Preliminary Data Sheet
66
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Interleaved Column Write Cycle (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,
,,
,
Hi-Z
,,
,,,,,,,,,,,,
,
,
,,
,,
,,
H
,
,
,,
,,
,,
,
,
,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
RAa
,,
RBa
,,
,,
,,
,,
,,,,,,,,,,,,
,,,,,,,,,,,,
RAa CAb
CBc
RBa CBa CBbCAa
,,
,,
,,
,
,
,
,,
,,
,,
,,
,
,
,,
,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
CBd
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
,,
,,
BA0
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,
,,
,,
,,
,,
,,
,,
Aa1 Aa2 Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2 Bd3 Bd4
Ab1 Ab2
Bb1 Bb2
Aa5 Aa6 Aa7 Aa8 Ba3 Ba4 Bc3 Bc4 Bd5 Bd6 Bd7 Bd8
Ab3 Ab4
Bb3 Bb4
DQS
/CLK
Hi-Z
VTT
VTT
,,,,
,,,,
,
,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
67
Auto Precharge after Read Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,
,,
,,
,,
,,,,,,,,,,,,
,,
,,
,,,
,,,
,,,
,
,
H
,,
,,
,,,
,,
,
,,
,,
,
,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,
,,
,,
,,,
,
,,
,,
,,
,,
,,
,
,
,,
,
,
,
,
,,
,,
,,
,,
BA0
,
,,,
,
,,
,,,
,,
,
,
,,
,
,
,,
,,
,,,
,
,,
,
,,,
,,,
,,
,,
,,,
,,,
RDb
,,,
,,,
RAc
,
,,
,,
,,
RDa
,,
,,
RAa
,,,,,,,,,,,,
,,,,,,,,,,,,
RAa CAbCAa RDbCDaRDa CAcCDb RAc
Activate
Command
for Bank A
Activate
Command
for Bank D
Bank A
Read Command
without Auto Precharge
Bank D
Read Command
with Auto Precharge
Activate
Command
for Bank D
Bank A
Read Command
with Auto Precharge
Auto Precharge
Start for Bank D Bank D
Read Command
with Auto Precharge
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Activate
Command
for Bank A
Bank A
Read Command
with Auto Precharge
V
TT
DQS
V
TT
/CLK
Hi-Z
Hi-Z
,,,,,,,,,,,,
Preliminary Data Sheet
68
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Auto Precharge after Read Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,,
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,
,,,,,,,,,,,,
,,,
,,,
,,,
H
,,,
,,,
,,,
,,,
,,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,,
,,
,,
,,,
,,
,,
,,
,,
,,
,,
,
,,
,,,
,,
,,,,
RDb
,,
,,
,,,
,,,,
RAa
,,,,,,,,,,,,,
,,,,,,,,,,,,,
RAa CAbCAa RDbCDaRDa CDb
,,
,,
,
BA0
,,
,,
,,
,,,
,,,
,,
,,
,,,
,,
,
RDa
Activate
Command
for Bank A
Activate
Command
for Bank D
Bank A
Read Command
without Auto Precharge
Bank D
Read Command
with Auto Precharge Activate
Command
for Bank D
Bank A
Read Command
with Auto Precharge
Auto Precharge
Start for Bank A Bank D
Read Command
with Auto Precharge
Auto Precharge
Start for Bank D
VTT
DQS
VTT
/CLK
Hi-Z
Hi-Z
,,,,,,,,,,,,,
,,,,,,,,,,,,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
69
Auto Precharge after Write Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
Activate
Command
for Bank A Bank A
Write Command
without Auto Precharge
Activate
Command
for Bank D
Activate
Command
for Bank D
Bank D
Write Command
with Auto Precharge
Bank D
Write Command
with Auto Precharge
Bank A
Write Command
with Auto Precharge
Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A
Activate
Command
for Bank ABank A
Write Command
with Auto Precharge
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,
L
,,,,,,,,,,,,
,,,
,
H
,,
,,
,,
,,,
,,,
,,
,
,
,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,,
,
,
,
,
,,
,,,
,
,,
,,
,,
,,,
,
,
,
,
,
,
,
,
,
,
,,
,,
,,
,,,,
,,
RDb
,,,
RAc
,
,,
,,
RDa
,,
RAa
,,,,,,,,,,,,
,,,,,,,,,,,,
RAa CAbCAa RDbCDaRDa CAcCDb RAc
,,
,,
,
,,,
,
,,
,,,
,,
,,
,
,,,
,
,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,,
,,,
,
,
,
,
,
,
,
,
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ Hi-Z
BA0
/CLK
DQS Hi-Z
VTT
VTT
,,
,,
,,,
,,
Preliminary Data Sheet
70
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Auto Precharge after Write Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
ADD
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,,,,,,,,,,,
,,
H
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,,
,,,
,,,,
,,,,
RDb
,
,
,,,
,,,
,,,
,,,
RAa
,,,,,,,,,,,,
RAa CAbCAa RDbCDaRDa CDb
,,
,,
RDa
,,
,,
,
,,,
,,,
,,
,,
,,,
,
,,,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
Activate
Command
for Bank A Bank A
Write Command
without Auto Precharge
Activate
Command
for Bank D Bank D
Write Command
with Auto Precharge
Bank A
Write Command
with Auto Precharge
Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A
Activate
Command
for Bank D Bank D
Write Command
with Auto Precharge
BA1
DM
DQ Hi-Z
BA0
/CLK
DQS Hi-Z
VTT
VTT
,,
,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
71
Byte Write Operation (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
LDM
Upper DQ
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
,
,
,
,,
,,,,
,,,,
,,,,,
,,,,,
,,,,,
,,,,,,,,,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,
,,,
,,,
,,,
,,,,
,,,,
H
Hi-Z
Hi-Z
,,,,
,,
BA0
,
,
,,,,
,,,,
,,,,,
,,,,,
,,,
,,,
,
,
,,
,,
,,
,,
,,
,,
,,,,,,,,,,,,
,,,,,,
,,,,,
,,,,,,
,,,,,,
,,,,,
,,,,,
UDM
Lower DQ
Activate
Command Read
Command Lower Byte
not Write Upper Byte
not Write
/CLK
UDQS
LDQS
V
TT
V
TT
V
TT
V
TT
Hi-Z
Hi-Z
Read
Command
Lower Byte
not Write
Preliminary Data Sheet
72
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
,,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,,
,,
,,,,,,,,,,,,
H
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,
,,
,,
,
,
,,,,
,,
,
,
,,
,,
,
,,,
,,,,,
,,,,,,,,,,,,
,,,,,,,,,,,,
RAa RAb
CAa
,
RAa RAb
CAb
tRP tRPtRAS
Activate
Command
for Bank A Activate
Command
for Bank A
Write
Command
for Bank A
PRE Command
Termination PRE Command
Termination
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
tRAS
,
,
,
,
,
,
,,
,,
RAc
RAc
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
BA0
DQS
/CLK
Hi-Z
Write
Mask
DAa1 DAa2 DAa3 DAa4 QAb1 QAb2 QAb3 QAb4 QAb5 QAb6
Hi-Z
VTT
VTT
,,,
,,,,,,,,,
,,
,,
Preliminary Data Sheet
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
73
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 2.5)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DM
DQ
,
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
,
Hi-Z
,,,,,,,,,,,,
H
,,
,,
,,
,,
,,
,
,
,,
,,
,,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
BA0
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
,,,,
,,,
,,,
,,,,,,,,,,,,
RAa RAb
CAa
,,
,,
RAa RAb
CAb
t
RP
t
RP
t
RAS
Activate
Command
for Bank A Activate
Command
for Bank A
Write
Command
for Bank A
PRE Command
Termination
Precharge
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
PRE Command
Termination
,,
,,
t
RAS
Write
Mask
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
RAc
RAc
,,
,,
DAa1 DAa2 DAa3 DAa4 QAb1 QAb2 QAb3 QAb4 QAb5 QAb6
DQS
/CLK
Hi-Z
V
TT
V
TT
,,,,,,,,,
,,,
,,
,,
,,
,,
74
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
14. Package Drawing
S66G5-65-9LG
66PIN PLASTIC TSOP (II) (400mil)
ITEM MILLIMETERS
A 22.22±0.05
B 0.865 MAX.
J 0.80±0.2
K 0.145
L 0.50
M 0.12
N 0.10
+0.025
−0.015
C 0.65 (T.P.)
D 0.24
E 0.10±0.05
F 1.1±0.1
G 1.00
H 11.76±0.20
I 10.16±0.10
P3°
+0.08
−0.07
+5°
−3°
M
66 34
133
P
A
CN
B
M
D
L
K
J
H
I
G
Fdetail of lead end
NOTES
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
R 0.25
S 0.60±0.15
S
S
E
R
L
S
75
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
15. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD45D128xxx.
Type of Surface Mount Device
µ
PD45D128xxxG 5 : 66-pi n P lasti c TSOP (II) (400 mil)
76
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
[MEMO]
77
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
[MEMO]
78
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
[MEMO]
79
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
µ
µµ
µ
PD45D128442, 45D128842, 45D128164
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
