Clocks for 4.5G Radio Access Networks SEPTEMBER 2017 Complete Timing Portfolio Leader in high performance clocks and oscillators Frequency flexibility + ultra-low jitter Best-in-class integration single IC clock trees Highly programmable with quick-turn samples 2 XO/VCXO Clock Generators Clock Buffers Synchronization Jitter Attenuating Clocks Wireless Clocks Road to 5G Starts Now Distributed Antenna Systems Boost coverage inside buildings, stadiums, subways, malls, airports Backhaul Equipment High bandwidth fiber or microwave 5G Small Cells Raisecoverage awareness Expand andof new products capacity in dense Si534x, urban Si538x, Si54x/Si56x, metro environments Si52200, Si5332 Silicon Labs Confidential Timing Focus Markets Trends Applications Core / Metro Data Center Wireless 10G 100G / 400G 40G 100G Mobile Edge Computing LTE-Advanced, 4.5G, 5G Massive MIMO, IEEE 1588 Core Router Servers Packet-Optical Transport Switches Data Center Interconnect Storage Small Cells MDAS RRH BBU Fronthaul / Backhaul Delivering optimized timing solutions combining highest performance and integration History of Innovation Industry's first quad frequency XO/VCXOs Industry's first jitter attenuating CLK IC 2002 Industry's first any-rate CLK generator 2005 2007 Industry's first 100 fs any-rate jitter attenuating CLK Industry's first multi-format low jitter buffer Industry's first any-rate jitter attenuating CLK 2008 Available Now! Industry's first LTE + Ethernet CLKs 2012 Industry's first Industry's first Coherent optical <100 fs any-rate CLK XOs 2014 2016 2017 DSPLL Simplifies Low Jitter Clock Generation Two-Stage Cascaded PLL: 1st stage: jitter cleaning, 2nd stage: clock generation Requires discrete VCXO, loop filters, LDOs Susceptible to board-level noise coupling High power, BiCMOS technology >100 U.S. and international patents issued or filed for Silicon Labs timing technology Low Phase Noise Clock Generation XO Phase Detector Loop Filter VCO DCO OUT Frac-N Divider Two-Stage Nested DSPLL: Provides jitter cleaning and clock generation DSPLL Inner Loop No external VCXO, loop filters; eliminates VCXO LDO fIN Jitter Cleaning Phase Detector & ADC Digital Loop Filter Frac-N Divider DSPLL Outer Loop DCO fOUT Highly immune to board-level noise >50% lower power, 55 nm CMOS technology MultiSynth Technology = Any Frequency Flexibility Conventional approach Fractional Divider Frac-N Divider fVCO fOUT Configuration-dependent jitter No phase error cancellation Highly variable jitter generation Divider Select Non-zero ppm frequency synthesis error Silicon Labs approach MultiSynth Dynamic phase error cancellation minimizes jitter fVCO Frac-N Divider fDIV Phase Error Cancellation Divider Select (DIV1, DIV2) Phase Adjust e fOUT Consistent, low jitter operation Zero ppm frequency synthesis error Any frequency with <100 fs rms jitter Simplifying Timing For Small Cells, DAS and Backhaul Traditional Approach Fiber Microwave Mm-wave 8 SerDes Clock Generator 4G/LTE JESD204B Clocking VCXO Loop Filter Si5386/81 Jitter Cleaning Clock DFE / FPGA / Baseband Processor DACs ADCs DACs DACs Wireless PLL Ethernet PLL Fiber Microwave Mm-wave SerDes Gen. Purpose Clocking DFE / FPGA / Baseband Processor DACs ADCs DACs DACs Requires 2 clock IC's and VCXO Single IC highest integration Not optimized for size, power, cost Optimized LTE + Ethernet clocking 339 mm2 PCB area 94 mm2 PCB area 2.4 W power consumption 1.1 W power consumption Silicon Labs Confidential Low Phase Noise - DSPLL Replaces 30.72 MHz VCXO-Based PLLs Si538x with no VCXO at 122.88MHz LMK04828 with 30.72 MHz VCXO at 122.88MHz Better performance without the cost and PCB area of a VCXO 9 Silicon Labs Confidential The Si538x Integration Advantage is Clear BOM Components DUT area VCXO area Loop filter area Power supply filtering Fractional Clock IC area Other PCB area Total PCB footprint Power Consumption Cascaded PLL Si5381/82/86 DSPLL 81 151 9 31 49 18 339 mm2 2.4 W 81 8 0 4 0 2 95 mm2 1.0 - 1.5 W 70% smaller and 55% lower power than competing devices 10 Silicon Labs Confidential Si5386 1-DSPLL Wireless Clock Si5386 Part Number Integrated XO Circuit No. of Clock Domains Clock Inputs/ Outputs Input Frequency Output Frequency Phase Jitter (fs RMS) PLL Bandwidth Package 4/12 7.68 MHz to 750 MHz 100 Hz to 2.94912 GHz 80 10 Hz to 4 kHz 64 LGA 9x9 mm IN_SEL OSC IN0 /INT IN1 /INT Si5386 5 DSPLL IN2 IN3/FB_IN /INT OUT0A /INT OUT0 0 /INT OUT1 Multi Synth /INT OUT2 Multi Synth /INT OUT3 /INT OUT4 0 /INT OUT5 Multi Synth /INT OUT6 Multi Synth /INT OUT7 /INT OUT8 0 /INT OUT9 /INT OUT9A /INT Multi Synth I2C_SEL SDA/SDIO A1/SDO SCLK A0/CS SPI/ I2 C NVM LOL INTR Status Monitors PDN 11 APPLICATIONS /INT RST SYNC OE Small cells Fixed wireless Pico cells, femto cells Distributed Antenna Systems FEATURES 5 independent frequency domains RF transceivers Data converter clocks CPRI, Ethernet, CPU clocks No external VCXO, crystal, loop filters Hitless switching, holdover Optional zero delay mode Low phase noise, spurious & jitter Noise floor: -165 dBc/Hz Spur: -103 dBc @ 122.88 MHz 80 fs RMS jitter Configurable swing: 200-3200 mVpp New Solutions for Wireless Si5381 CPRI 30.72MHz x N DSPLL B LTE SyncE 8kHz x N DSPLL A SyncE XO DSPLL C FPGA Base Band Unit DSPLL for 4G/LTE Clocks to ADC/DAC DSPLL for SyncE DSPLL for FPGA clocking Si5386 CPRI 30.72MHz x N or eCPRI 156.25MHz DSPLL Wireless MultiSynth Ethernet Small Cells / Distributed Antenna Systems DSPLL for RF transceiver MultiSynth channel generates Ethernet frequencies Si5381/82 Multi-DSPLL Wireless Clock Si5381/82 Part Number # PLLs Si5381 4 Integrated XO Circuit OSC IN0 /INT DSPLL C IN1 /INT DSPLL D IN2 /INT DSPLL A IN3 /INT DSPLL B /INT OUT0A /INT OUT0 /INT OUT1 /INT OUT2 /INT OUT3 /INT OUT4 /INT OUT5 /INT OUT6 Si5381 Si5382 /INT Output Frequency Phase Jitter (fs rms) PLL Bandwidth Package 4/12 8 kHz to 750 MHz 100 Hz to 2.94912 GHz 80 10 Hz to 4 kHz 64 QFN 9x9 mm 2 APPLICATIONS Mobile backhaul Fixed wireless LTE-Advanced, 4.5G Base band units, micro-BTS FEATURES 2 or 4 independent timing paths ANY in to ANY out frequency per DSPLL /INT OUT8 No external VCXO, crystal, loop filters /INT OUT9 Hitless switching, holdover /INT OUT9A Optional zero delay mode 2 I C/SPI 13 Input Frequency OUT7 NVM Control/ Status Si5382 Clock Inputs/ Outputs DSPLL B optimized for wireless Noise floor: -165 dBc/Hz Spur: -103 dBc @ 122.88 MHz 80 fs RMS jitter DSPLL A/C/D for reference & data FPGA, CPU, SyncE Silicon Labs Confidential Product Comparison Table Feature No. Of Clock Inputs/Outputs No. of DSPLLs No. of Frequency Domains Integrated VCXO and Loop Filter Si5386 4/12 (differential) 4/12 (differential) 4/2 Four independent DSPLLs 1 Five MultiSynths Yes Yes Zero Delay Mode Yes: no external xtals or oscillators Yes Yes: no external xtals or oscillators Yes Package 9x9 mm 64-LGA 9X9 mm 64-LGA Power Consumption 1.4W/1.1W 1.0W Integrated Reference 14 Si5381/Si5382 Si538x Development Tools Find the right clock and customize it for your application Start Here Test on an Evaluation Board Create custom part number Contact Sales or Distributor and place sample order Receive pre-programmed samples in 2 weeks Click here to download ClockBuilder Pro Si538x development kits: Si5381E-E-EVB, Si5382E-E-EVB, Si5386E-E-EVB 15 Silicon Labs Confidential Summary: Si538x Simplify Wireless Clock Trees 16 Best-in-class integration Highest level of integration Eliminates clocks ICs, VCXO, loop filters, LDOs Simplifies PCB layout, power supply filtering Carrier-grade performance Low phase noise Excellent spurious performance More reliable than VCXO-based PLL Simple, easy to use Simplified PCB layout and design Intuitive ClockBuilder Pro software Silicon Labs Confidential www.silabs.com/timing