CS5381 120 dB, 192 kHz, Multi-Bit Audio A/D Converter Features General Description Advanced Multi-bit Delta-Sigma Architecture 24-Bit Conversion 120 dB Dynamic Range -110 dB THD+N Supports all Audio Sample Rates Including 192 kHz Less than 32 5mW Power Consumption High Pass Filter or DC Offset Calibration Supports Logic Levels Between 5 and 2.5V Differential Analog Architecture Low Latency Digital Filtering Overflow Detection Pin compatible with the CS5361 VQ FILT + REFGND O V FL The CS5381 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. The CS5381 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5381 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. ORDERING INFORMATION CS5381-KS -10 to 70 C 24-pin SOIC CS5381-KZ -10 to 70 C 24-pin TSSOP CDB5381 Evaluation Board 2 .5 V - 5 .0 V VL SCLK LRCK S DOUT MCLK RST S eria l O utp u t In terfa ce Vo lta g e R e fe re n ce I 2 S /LJ M /S A IN L - + A IN L + L P F ilter - D ig ita l D e cim atio n F ilter H ig h P ass F ilte r D ig ita l D e cim atio n F ilter H ig h P ass F ilte r S /H H PF M D IV DAC A IN R - + A IN R + L P Filte r - S /H M ODE0 MO DE1 DAC VA 5 .0 V GND Advance Product Information Cirrus Logic, Inc. http://www.cirrus.com GND VD 3.3 V - 5 .0 V This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) OCT `03 DS563A2 1 CS5381 TABLE OF CONTENTS 1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPECIFIED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ANALOG CHARACTERISTICS (CS5381-KS/KZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Operational Mode/Sample Rate Range Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 High Pass Filter and DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Overflow Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6.1 OVFL Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 Grounding and Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 Synchronization of Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 PARAMETER DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contacting Cirrus Logic Support F or all p rod uct q ue stio ns an d inq uirie s c ont act a Cir r us Logic Sal es Re pres e n t ative. To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or im plied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of s ale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of an y items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this inform ation, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information cont ained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export per mit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS M AY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOM ER OR CUSTOMERS CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS , EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 2 CS5381 LIST OF FIGURES Figure 1. Master Mode, Left Justified SAI ....................................................................................... 9 Figure 2. Slave Mode, Left Justified SAI ......................................................................................... 9 Figure 3. Master Mode, I 2S SAI ...................................................................................................... 9 Figure 4. Slave Mode, I2S SAI ........................................................................................................ 9 Figure 5. OVFL Output Timing ........................................................................................................ 9 Figure 6. Left Justified Serial Audio Interface ............................................................................... 10 Figure 7. I2S Serial Audio Interface............................................................................................... 10 Figure 8. OVFL Output Timing, I 2S Format................................................................................... 10 Figure 9. OVFL Output Timing, Left-Justified Format ................................................................... 10 Figure 10. Typical Connection Diagram ........................................................................................ 12 Figure 11. CS5381 Master Mode Clocking ................................................................................... 13 Figure 12. Recommended Analog Input Buffer............................................................................. 15 Figure 13. Single Speed Mode Stopband Rejection ..................................................................... 20 Figure 14. Single Speed Mode Transition Band ........................................................................... 20 Figure 15. Single Speed Mode Transition Band (Detail)............................................................... 20 Figure 16. Single Speed Mode Passband Ripple ......................................................................... 20 Figure 17. Double Speed Mode Stopband Rejection.................................................................... 20 Figure 18. Double Speed Mode Transition Band.......................................................................... 20 Figure 19. Double Speed Mode Transition Band (Detail) ............................................................. 21 Figure 20. Double Speed Mode Passband Ripple ........................................................................ 21 Figure 21. Quad Speed Mode Stopband Rejection ...................................................................... 21 Figure 22. Quad Speed Mode Transition Band............................................................................. 21 Figure 23. Quad Speed Mode Transition Band (Detail)................................................................ 21 Figure 24. Quad Speed Mode Passband Ripple........................................................................... 21 LIST OF TABLES Table 1. Revision History ................................................................................................................ 3 Table 2. CS5381 Mode Control..................................................................................................... 13 Table 3. CS5381 Common Master Clock Frequencies................................................................. 14 Table 4. CS5381 Slave Mode Clock Ratios .................................................................................. 14 Release Date A1 December, 2002 A2 October, 2003 Changes Advanced Release Changed front page description of digital filter (pag e1) Improved distortion specification from -105dB to -110dB (page6) Modified serial port timing specifications for slave mode operation (page8) Added pull-down resistors to recommended input buffer ( page15) Table 1. Revision History 3 CS5381 1 PIN DESCRIPTIONS RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF I2S/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ AINR+ AINRVA GND AINLAINL+ OVFL M1 M0 Power Supply and Ground Pin Name # Pin Description RST 1 Reset (Input) - The device enters a low power mode when low. M/S 2 Master/Slave Mode (Input) - Selects operation as either clock master or slave. LRCK 3 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK 4 Serial Clock (Input/Output) - Serial clock for the serial audio interface. MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VD 6 Digital Power (Input) - Positive power supply for the digital section. GND 7,18 Ground (Input) - Ground reference. Must be connected to analog ground. VL 8 Logic Power (Input) - Positive power for the digital input/output. SDOUT 9 Serial Audio Data Output (Output) - Output for two's complement serial audio data. MDIV 10 MCLK Divider (Input) - Enables a master clock divide by two function. HPF 11 High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter. I2S/LJ 12 Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI. M0 M1 13, Mode Selection (Input) - Determines the operational mode of the device. 14 OVFL 15 AINL+ AINL- 16, Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma 17 modulators via the AINL+/- pins. VA 19 AINR+ AINR- 20, Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma 21 modulators via the AINR+/- pins. VQ 22 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. REF_GND 23 Reference Ground (Input) - Ground reference for the internal sampling circuits. FILT+ 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. 4 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. Analog Power (Input) - Positive power supply for the analog section. CS5381 2 CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at VA = 5. 0V, VD = VL = 3. 3V, and TA = 25C. SPECIFIED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Typ Max Units VA VD VL 4.75 3.1 2.37 5.0 - 5.25 5.25 5.25 V V V TA -10 - +70 C DC Power Supply DC Power Supplies: Positive Analog Positive Digital Positive Logic Ambient Operating Temperature (Power Applied) ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 3) Parameter Symbol Min Typ Max Units Analog Logic Digital VA VL VD -0.3 -0.3 -0.3 - +6.0 +6.0 +6.0 V V V Input Current (Note 1) Iin - - 10 mA Analog Input Voltage (Note 2) V IN GND-0.7 - VA+0.7 V Digital Input Voltage (Note 2) VIND -0.7 - VL+0.7 V Ambient Operating Temperature (Power Applied) TA -50 - +95 C Storage Temperature Tstg -65 - +150 C DC Power Supplies: Notes: 1. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 2. The maximum over/under voltage is limited by the input current. 3. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 5 CS5381 ANALOG CHARACTERISTICS (CS5381-KS/KZ) (Test conditions (unless otherwise specified): Input test signal is a 1kHz sine wave; measurement bandwidth is 10Hz t o 20kHz.) Parameter Fs = 48kHz A-weighted unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1dB Quad Speed Mode Fs = 192kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB 40 kHz bandwidth -1dB Dynamic Performance for All Modes Interchannel Isolation Interchannel Phase Deviation DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled Analog Input Characteristics Full-scale Input Voltage Input Impedance (Differential) (Note 5) Common Mode Rejection Ratio Symbol Single Speed Mode Dynamic Range 6 Measured between AIN+ and AIN- Typ Max Unit 114 111 120 117 - dB dB - -110 -97 -57 -104 - dB dB dB 114 111 - 120 117 114 - dB dB dB - -110 -97 -57 -107 -104 - dB dB dB dB 114 111 - 120 117 114 - dB dB dB - -110 -97 -57 -107 -104 - dB dB dB dB - 110 0.0001 - dB Degree - 0.1 100 0 100 5 - dB % ppm/C LSB LSB 1.9 37 - 2.0 100 2.1 - Vrms k dB THD+N THD+N THD+N CMRR Notes: 4. Referred to the typical full-scale input voltage. 5. Min CS5381 DIGITAL FILTER CHARACTERISTICS (Note 6) Parameter Symbol Min Typ Max Unit 0 - 0.47 Fs - - 0.035 dB 0.58 - - Fs -95 - - dB - 12/Fs - s (Note 7) 0 - 0.45 Fs - - 0.035 dB (Note 7) 0.68 - - Fs -92 - - dB - 9/Fs - s 0 - 0.24 Fs - - 0.035 dB 0.78 - - Fs -97 - - dB - 5/Fs - s - 1 20 - Hz Hz - 10 - Deg - - 0 dB Single Speed Mode (2 kHz to 50 kHz sample rates) Passband (-0.1 dB) (Note 7) Passband Ripple Stopband (Note 7) Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd Double Speed Mode (50 kHz to 100 kHz sample rates) Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd Quad Speed Mode (100 kHz to 200 kHz sample rates) Passband (-0.1 dB) (Note 7) Passband Ripple Stopband (Note 7) Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd High Pass Filter Characteristics Frequency Response Phase Deviation -3.0 dB -0.13 dB (Note 8) @ 20 Hz (Note 8) Passband Ripple Filter Setting Time 105/Fs s Notes: 6. Amplitude vs. Frequency response plots of this data are available in "Appendix" on page20. 7. The filter frequency response scales precisely with Fs. 8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 7 CS5381 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter Symbol Min Typ Max Unit Fs Fs Fs 2 50 100 - 50 100 200 kHz kHz kHz OVFL to LRCK edge setup time tsetup 16/fsclk - - s OVFL to LRCK edge hold time thold 1/fsclk - - s - 740 680 - ms ms Output Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode OVFL time-out on overrange condition Fs = 44.1, 88.2, 176.4 kHz Fs = 48, 96, 192 kHz MCLK Specifications MCLK Period tclkw 40 - 1953 ns MCLK Duty Cycle tclkhl 40 - 60 % Master Mode SCLK falling to LRCK tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo 0 - 32 ns - 50 - % 2 - 50 kHz 40 50 60 % SCLK Duty Cycle Slave Mode Single Speed Output Sample Rate Fs LRCK Duty Cycle SCLK Period tsclkw 163 - - ns SCLK Low tsclkhl 55 - - ns SCLK falling to SDOUT valid tdss - - 32 ns SCLK falling to LRCK edge tslrd -20 - 20 ns Fs 50 - 100 kHz 40 50 60 % - - ns Double Speed Output Sample Rate LRCK Duty Cycle SCLK Period tsclkw 163 SCLK Low tsclkhl 55 - - ns SCLK falling to SDOUT valid tdss - - 32 ns SCLK falling to LRCK edge tslrd -20 - 20 ns Fs 100 - 200 kHz 40 50 60 % Quad Speed Output Sample Rate LRCK Duty Cycle SCLK Period tsclkw 81 - - ns SCLK Low tsclkhl 40 - - ns SCLK falling to SDOUT valid tdss - - 32 ns SCLK falling to LRCK edge tslrd -8 - 8 ns 8 CS5381 t sclkh t sclkl SCLK output SCLK input t sclkw t sl rd t mslr LRCK output LRCK input t sdo t lrdss MSB S DOUT MSB-1 MSB SDOUT Figure 1. Master Mode, Left Justified SAI t dss MSB-1 MSB-2 Figure 2. Slave Mode, Left Justified SAI t sclkh t sclkl SCLK input SC LK output t sclkw t m slr LRCK input LR C K output t dss t sdo MSB S DO UT MSB SDOUT Figure 3. Master Mode, I2S SAI MSB-1 Figure 4. Slave Mode, I2S SAI LRCK t setup t hold OVFL Figure 5. OVFL Output Timing 9 CS5381 LRC K L e ft C h a n n e l R ig h t C h a n n e l SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 6. Left Justified Serial Audio Interface LR CK L e ft C h a n n e l R ig h t C h a n n e l SCLK SD A TA 2 3 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 Figure 7. I2S Serial Audio Interface LRCK SCLK OVFL_R OVFL OVFL_L OVFL_R Figure 8. OVFL Output Timing, I2S Format LRCK SCLK OVFL OVFL_R OVFL_L Figure 9. OVFL Output Timing, Left-Justified Format 10 OVFL_R CS5381 DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode) Parameter Symbol Min Typ Max Unit VA VL,VD = 5 V VL,VD = 3.3 V IA ID ID - 50 30 20 55 33 22 mA mA mA VA VL,VD=5 V IA ID - 100 100 - uA uA VL, VD =5V VL, VD = 3.3 V (Power-Down Mode) - - 400 316 1 440 348 - mW mW mW PSRR - 65 - dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - 2.5 25 0.01 - k Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink - 5 35 0.01 - Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 9) Power Consumption (Normal Operation) Power Supply Rejection Ratio (1 kHz) (Note 10) V mA V k mA Notes: 9. Power-Down Mode is defined as RST = Low with all clocks and data lines held static. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage (% of VL) Symbol Min Typ Max Units VIH 70% - - V Low-Level Input Voltage (% of VL) VIL - - 30% V High-Level Output Voltage at Io = 100 A (% of VL) VOH 70% - - V Low-Level Output Voltage at I o = 100 A (% of VL) VOL - - 15% V Iin - - 10 A Input Leakage Current 11 CS5381 3 TYPICAL CONNECTION DIAGRAM +5 V to 3.3 V +5V + 1 F 0.01 F 0.01 F * + 1 F VA VD VL FILT+ 47 F + VL 0.01 F 10 k REFGND + 1 F 0.01 F VQ Analog Input Buffer (Figure 3) +5Vto 2.5 V 1 F 0.01F 5.1 0.01 F + AINL+ CS5381 A/D CONVERTER OVFL RST 2 I S/LJ M/S HPF M0 M1 MDIV Power Down and Mode Settings SDOUT Audio Data Processor AINL- Analog Input Buffer (Figure 3) AINR+ LRCK SCLK MCLK Timing Logic and Clock AINR- GND GND Figure 10. Typical Connection Diagram 12 * Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD. CS5381 4 APPLICATIONS 4.1 Operational Mode/Sample Rate Range Select The output sample rate, Fs, can be adjusted from 2kHz to 200kHz. The CS5381 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 2. M1 (Pin 14) M0 (Pin 13) 0 0 0 1 1 0 1 1 MODE Single Speed Mode Double Speed Mode Quad Speed Mode Reserved Output Sample Rate (Fs) 2 kHz - 50 kHz 50 kHz - 100 kHz 100 kHz - 200 kHz Table 2. CS5381 Mode Control 4.2 System Clocking The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0. 4.2.1 Master Mode In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 11. Refer to Table 3 for common master clock frequencies. /1 / 256 Single Speed 00 / 128 Double Speed 01 / 64 Quad Speed 10 LRCK Output (Equal to Fs) 0 M1 M0 MCLK /2 1 MDIV /4 Single Speed 00 /2 Double Speed 01 /1 Quad Speed 10 SCLK Output Figure 11. CS5381 Master Mode Clocking 13 CS5381 MDIV = 0 MCLK (MHz) 8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288 SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 176.4 192 MDIV = 1 MCLK (MHz) 16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576 Table 3. CS5381 Common Master Clock Frequencies 4.2.2 Slave Mode LRCK and SCLK operate as inputs in Slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 4 for required clock ratios. Single Speed Mode Fs = 2 kHz to 50 kHz Double Speed Mode Fs = 50 kHz to 100 kHz Quad Speed Mode Fs = 100 kHz to 200 kHz MCLK/LRCK Ratio 256x, 512x 128x, 256x 64x*, 128x SCLK/LRCK Ratio 64x, 128x 64x 64x * Only available in Master mode. Table 4. CS5381 Slave Mode Clock Ratios 4.3 Power-up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance. 4.4 Analog Connections The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2, ... refer to Figure 12 which shows the suggested filter that will attenuate any noise energy at 6. 144MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 14 CS5381 634 470 pF COG 91 10 uF A DC A IN+ + A IN+ 100 k 10 k COG VQ 2700 pF 10 k 10 uF A IN- + 100 k - 91 A DC A IN- 470 pF COG 634 Figure 12. Recommended Analog Input Buffer 4.5 High Pass Filter and DC Offset Calibration The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into the A/D converter. The CS5381 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS5381 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5381. 15 CS5381 4.6 Overflow Detection The CS5381 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon as an overrange condition in either channel is detected. The data will remain low as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any other overrange condition detected. Please note that an overrange condition on either channel will restart the timeout period for both channels. 4.6.1 OVFL Output Timing In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 8 and 9. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow status. In I2S format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status. 4.7 Grounding and Power Supply Decoupling As with any high resolution converter, the CS5381 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 10 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5381 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. 4.8 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5381's in the system. If only one master clock source is needed, one solution is to place one CS5381 in Master mode, and slave all of the other CS5381's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5381 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge. 16 CS5381 5 PACKAGE DIMENSIONS 24L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c D L SEATING PLANE A e A1 INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.40 7.60 1.02 1.52 10.00 10.65 0.40 1.27 0 8 17 CS5381 24L TSSOP (4. 4mm BODY) PACKAGE DRAWING N D E11 A2 E A b2 e A1 END VIEW L SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4 MILLIMETERS MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8 MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0 NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4 NOTE MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8 2,3 1 1 JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.0 7mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 a nd 0.25mm from lead tips. 6 THERMAL CHARACTERISTICS Parameter Symbol Allowable Junction Temperature Junction to Ambient Thermal Impedance 18 JA Min Typ Max Unit - - 135 C - 70 - C/W CS5381 7 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60dBFS signal. 60dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 1 0Hz to 2 0kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 19 CS5381 APPENDIX 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 Amplitude (dB) Amplitude (dB) 8 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -140 0.40 1.0 Frequency (normalized to Fs) 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Figure 13. Single Speed Mode Stopband Rejection Figure 14. Single Speed Mode Transition Band 0.10 0 -1 0.08 -2 0.05 0.03 -4 Amplitude (dB) Amplitude (dB) -3 -5 -6 0.00 -0.03 -7 -0.05 -8 -0.08 -9 -10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Frequency (normalized to Fs) -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (normalized to Fs) Figure 17. Double Speed Mode Stopband Rejection 20 Figure 16. Single Speed Mode Passband Ripple Amplitude (dB) Amplitude (dB) F igu re 15 . S in gle S p eed M od e T ra n sitio n B an d (D eta il) 1.0 -140 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 Frequency (normalized to Fs) Figure 18. Double Speed Mode Transition Band 0.70 CS5381 0.10 0 -1 0.08 -2 0.05 -3 0.03 Amplitude (dB) Amplitude (dB) -4 -5 -6 0.00 -0.03 -7 -0.05 -8 -9 -0.08 -10 0.40 0.43 0.45 0.48 0.50 0.53 -0.10 0.00 0.55 Frequency (normalized to Fs) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Figure 19. Double Speed Mode Transition Band (Detail) Figure 20. Double Speed Mode Passband Ripple 0 0 -10 -10 -20 -20 -30 -30 -40 Amplitude (dB) Amplitude (dB) -40 -50 -60 -70 -50 -60 -70 -80 -80 -90 -90 -100 -100 -110 -110 -120 -130 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.2 0.25 0.3 0 0.10 -1 0.08 -2 0.06 -3 0.04 -4 0.02 -5 -6 -0.04 -0.06 -9 -0.08 -10 0.25 0.3 0.35 0.4 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.00 -8 0.2 0.45 -0.02 -7 0.15 0.4 Figure 22. Quad Speed Mode Transition Band Amplitude (dB) Amplitude (dB) Figure 21. Quad Speed Mode Stopband Rejection 0.1 0.35 Frequency (normalized to Fs) Frequency (normalized to Fs) 0.45 0.5 0.55 0.6 Frequency (normalized to Fs) Figure 23. Quad Speed Mode Transition Band (Detail) -0.10 0.00 0.05 0.10 0.15 0.20 0.25 Frequency (normalized to Fs) Figure 24. Quad Speed Mode Passband Ripple 21